STM32L4: Review of last PR + Move separate stm32l4_flash.h; move hardware-specific definitions to chip/stm32l4_flash.h
This commit is contained in:
Gregory Nutt
parent
1f6970ea2f
commit
3091050963
267
arch/arm/src/stm32l4/chip/stm32l4_flash.h
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267
arch/arm/src/stm32l4/chip/stm32l4_flash.h
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@ -0,0 +1,267 @@
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/************************************************************************************
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* arch/arm/src/stm32l4/chip/stm32l4_flash.h
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*
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* Copyright (C) 2009, 2011, 2015, 2017 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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* Juha Niskanen <juha.niskanen@haltian.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_FLASH_H
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#define __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_FLASH_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Flash size is known from the chip selection:
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*
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* When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the
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* CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based on the chip
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* part number. This value can be overridden with CONFIG_STM32L4_FLASH_OVERRIDE_x
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*
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* Parts STM32L4xxE have 512Kb of FLASH
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* Parts STM32L4xxG have 1024Kb of FLASH
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*
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* N.B. Only Single bank mode is supported
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*/
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#define _K(x) ((x)*1024)
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#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_G)
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# define CONFIG_STM32L4_FLASH_OVERRIDE_E
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# warning "Flash size not defined defaulting to 512KiB (E)"
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#endif
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/* Override of the Flash has been chosen */
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#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT)
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# undef CONFIG_STM32L4_FLASH_CONFIG_B
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# undef CONFIG_STM32L4_FLASH_CONFIG_C
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# undef CONFIG_STM32L4_FLASH_CONFIG_E
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# undef CONFIG_STM32L4_FLASH_CONFIG_G
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# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
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# define CONFIG_STM32L4_FLASH_CONFIG_B
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# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C)
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# define CONFIG_STM32L4_FLASH_CONFIG_C
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# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_E)
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# define CONFIG_STM32L4_FLASH_CONFIG_E
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# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G)
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# define CONFIG_STM32L4_FLASH_CONFIG_G
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# endif
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#endif
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/* Define the valid configuration */
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#if defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
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# define STM32L4_FLASH_NPAGES 64
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# define STM32L4_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
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# define STM32L4_FLASH_NPAGES 128
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# define STM32L4_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */
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# define STM32L4_FLASH_NPAGES 256
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# define STM32L4_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
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# define STM32L4_FLASH_NPAGES 512
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# define STM32L4_FLASH_PAGESIZE 2048
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#else
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# error "unknown flash configuration!"
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#endif
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#ifdef STM32L4_FLASH_PAGESIZE
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# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE)
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#endif
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/* Register Offsets *****************************************************************/
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#define STM32L4_FLASH_ACR_OFFSET 0x0000
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#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004
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#define STM32L4_FLASH_KEYR_OFFSET 0x0008
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#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c
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#define STM32L4_FLASH_SR_OFFSET 0x0010
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#define STM32L4_FLASH_CR_OFFSET 0x0014
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#define STM32L4_FLASH_ECCR_OFFSET 0x0018
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#define STM32L4_FLASH_OPTR_OFFSET 0x0020
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#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024
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#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028
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#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c
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#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044
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# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048
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# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c
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# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050
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#endif
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/* Register Addresses ***************************************************************/
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#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET)
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#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET)
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#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET)
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#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET)
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#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET)
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#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET)
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#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET)
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#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET)
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#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET)
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#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET)
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#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET)
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#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET)
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET)
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# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET)
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# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET)
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# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Flash Access Control Register (ACR) */
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#define FLASH_ACR_LATENCY_SHIFT (0)
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#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
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# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states , for Vcore range 1 2 */
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# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states <=16 <=6 */
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# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state <=32 <=12 */
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# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states <=48 <=18 */
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# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states <=64 <=26 */
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# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states <=80 <=26 */
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#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
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#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
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#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
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#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
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#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
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#define FLASH_ACR_RUN_PD (1 << 13) /* Bit 13: Flash mode during Run */
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#define FLASH_ACR_SLEEP_PD (1 << 14) /* Bit 14: Flash mode during Sleep */
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/* Flash Status Register (SR) */
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#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
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#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
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#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
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#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
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#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
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#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
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#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
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#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */
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#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
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#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
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#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */
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#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
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#if defined(CONFIG_STM32L4_STM32L4X3)
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# define FLASH_SR_PEMPTY (1 << 17) /* Bit 17: Program empty */
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#endif
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/* Flash Control Register (CR) */
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#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */
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#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */
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#define FLASH_CR_MER1 (1 << 2) /* Bit 2 : Mass Erase Bank 1 */
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#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-10: Page number */
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#define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT)
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#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */
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# define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */
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#endif
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#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */
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#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */
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#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */
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#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
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#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
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#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
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#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */
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#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */
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#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
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/* Flash ECC Register (ECCR) */
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#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 8-15: Read protect */
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#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */
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#endif
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#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
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#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
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#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
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#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
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/* Flash Option Control Register (OPTCR) */
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#define FLASH_OPTCR_NRST_STOP (1 << 12) /* Bit 12: Generate reset when entering the Stop mode */
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#define FLASH_OPTCR_NRST_STDBY (1 << 13) /* Bit 13: Generate reset when entering the Standby mode */
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#define FLASH_OPTCR_NRST_SHDW (1 << 14) /* Bit 14: Generate reset when entering the Shutdown mode */
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#define FLASH_OPTCR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
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#define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
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#define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
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#define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
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#if defined(CONFIG_STM32L4_STM32L4X6)
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# define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */
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# define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */
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#endif
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#define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
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#define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
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#define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
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#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX)
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# define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
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# define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
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#endif
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#define FLASH_OPTCR_BORLEV_SHIFT (8) /* Bits 8-10: BOR reset Level */
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#define FLASH_OPTCR_BORLEV_MASK (7 << FLASH_OPTCR_BORLEV_SHIFT)
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#define FLASH_OPTCR_VBOR0 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */
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#define FLASH_OPTCR_VBOR1 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */
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#define FLASH_OPTCR_VBOR2 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* 010: BOR Level 2 (2.2 V) */
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#define FLASH_OPTCR_VBOR3 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */
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#define FLASH_OPTCR_VBOR4 (4 << FLASH_OPTCR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */
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#define FLASH_OPTCR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */
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#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT)
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#define FLASH_OPTCR_RDP_NONE (0xAA << FLASH_OPTCR_RDP_SHIFT)
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#define FLASH_OPTCR_RDP_CHIP (0xCC << FLASH_OPTCR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */
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#endif /* __ARCH_ARM_SRC_STM32L4_CHIP_STM32L4_FLASH_H */
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@ -62,7 +62,6 @@
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#include "up_arch.h"
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#if !(defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L4X6))
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# error "Unrecognized STM32 chip"
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#endif
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@ -39,224 +39,11 @@
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#define __ARCH_ARM_SRC_STM32L4_STM32L4_FLASH_H
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/************************************************************************************
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* Pre-processor Definitions
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* Included Files
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************************************************************************************/
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/* Flash size is known from the chip selection:
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*
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* When CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT is set the
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* CONFIG_STM32L4_FLASH_CONFIG_x selects the default FLASH size based on the chip
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* part number. This value can be overridden with CONFIG_STM32L4_FLASH_OVERRIDE_x
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*
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* Parts STM32L4xxE have 512Kb of FLASH
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* Parts STM32L4xxG have 1024Kb of FLASH
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*
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* N.B. Only Single bank mode is supported
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*/
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#define _K(x) ((x)*1024)
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#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_B) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_C) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_E) && \
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!defined(CONFIG_STM32L4_FLASH_OVERRIDE_G) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_B) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_C) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_E) && \
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!defined(CONFIG_STM32L4_FLASH_CONFIG_G)
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# define CONFIG_STM32L4_FLASH_OVERRIDE_E
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# warning "Flash size not defined defaulting to 512KiB (E)"
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#endif
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/* Override of the Flash has been chosen */
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#if !defined(CONFIG_STM32L4_FLASH_OVERRIDE_DEFAULT)
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# undef CONFIG_STM32L4_FLASH_CONFIG_B
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# undef CONFIG_STM32L4_FLASH_CONFIG_C
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# undef CONFIG_STM32L4_FLASH_CONFIG_E
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# undef CONFIG_STM32L4_FLASH_CONFIG_G
|
||||
# if defined(CONFIG_STM32L4_FLASH_OVERRIDE_B)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_B
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_C)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_C
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_E)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_E
|
||||
# elif defined(CONFIG_STM32L4_FLASH_OVERRIDE_G)
|
||||
# define CONFIG_STM32L4_FLASH_CONFIG_G
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Define the valid configuration */
|
||||
|
||||
#if defined(CONFIG_STM32L4_FLASH_CONFIG_B) /* 128 kB */
|
||||
# define STM32L4_FLASH_NPAGES 64
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_C) /* 256 kB */
|
||||
# define STM32L4_FLASH_NPAGES 128
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_E) /* 512 kB */
|
||||
# define STM32L4_FLASH_NPAGES 256
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
#elif defined(CONFIG_STM32L4_FLASH_CONFIG_G) /* 1 MB */
|
||||
# define STM32L4_FLASH_NPAGES 512
|
||||
# define STM32L4_FLASH_PAGESIZE 2048
|
||||
#else
|
||||
# error "unknown flash configuration!"
|
||||
#endif
|
||||
|
||||
#ifdef STM32L4_FLASH_PAGESIZE
|
||||
# define STM32L4_FLASH_SIZE (STM32L4_FLASH_NPAGES * STM32L4_FLASH_PAGESIZE)
|
||||
#endif
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32L4_FLASH_ACR_OFFSET 0x0000
|
||||
#define STM32L4_FLASH_PDKEYR_OFFSET 0x0004
|
||||
#define STM32L4_FLASH_KEYR_OFFSET 0x0008
|
||||
#define STM32L4_FLASH_OPTKEYR_OFFSET 0x000c
|
||||
#define STM32L4_FLASH_SR_OFFSET 0x0010
|
||||
#define STM32L4_FLASH_CR_OFFSET 0x0014
|
||||
#define STM32L4_FLASH_ECCR_OFFSET 0x0018
|
||||
#define STM32L4_FLASH_OPTR_OFFSET 0x0020
|
||||
#define STM32L4_FLASH_PCROP1SR_OFFSET 0x0024
|
||||
#define STM32L4_FLASH_PCROP1ER_OFFSET 0x0028
|
||||
#define STM32L4_FLASH_WRP1AR_OFFSET 0x002c
|
||||
#define STM32L4_FLASH_WRP1BR_OFFSET 0x0030
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# define STM32L4_FLASH_PCROP2SR_OFFSET 0x0044
|
||||
# define STM32L4_FLASH_PCROP2ER_OFFSET 0x0048
|
||||
# define STM32L4_FLASH_WRP2AR_OFFSET 0x004c
|
||||
# define STM32L4_FLASH_WRP2BR_OFFSET 0x0050
|
||||
#endif
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32L4_FLASH_ACR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ACR_OFFSET)
|
||||
#define STM32L4_FLASH_PDKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PDKEYR_OFFSET)
|
||||
#define STM32L4_FLASH_KEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_KEYR_OFFSET)
|
||||
#define STM32L4_FLASH_OPTKEYR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTKEYR_OFFSET)
|
||||
#define STM32L4_FLASH_SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_SR_OFFSET)
|
||||
#define STM32L4_FLASH_CR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_CR_OFFSET)
|
||||
#define STM32L4_FLASH_ECCR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_ECCR_OFFSET)
|
||||
#define STM32L4_FLASH_OPTR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_OPTR_OFFSET)
|
||||
#define STM32L4_FLASH_PCROP1SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1SR_OFFSET)
|
||||
#define STM32L4_FLASH_PCROP1ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP1ER_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1AR_OFFSET)
|
||||
#define STM32L4_FLASH_WRP1BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP1BR_OFFSET)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# define STM32L4_FLASH_PCROP2SR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2SR_OFFSET)
|
||||
# define STM32L4_FLASH_PCROP2ER (STM32L4_FLASHIF_BASE+STM32L4_FLASH_PCROP2ER_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2AR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2AR_OFFSET)
|
||||
# define STM32L4_FLASH_WRP2BR (STM32L4_FLASHIF_BASE+STM32L4_FLASH_WRP2BR_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
/* Flash Access Control Register (ACR) */
|
||||
|
||||
#define FLASH_ACR_LATENCY_SHIFT (0)
|
||||
#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
|
||||
# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states , for Vcore range 1 2 */
|
||||
# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states <=16 <=6 */
|
||||
# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state <=32 <=12 */
|
||||
# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states <=48 <=18 */
|
||||
# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states <=64 <=26 */
|
||||
# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states <=80 <=26 */
|
||||
|
||||
#define FLASH_ACR_PRFTEN (1 << 8) /* Bit 8: Prefetch enable */
|
||||
#define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
|
||||
#define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
|
||||
#define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
|
||||
#define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
|
||||
#define FLASH_ACR_RUN_PD (1 << 13) /* Bit 13: Flash mode during Run */
|
||||
#define FLASH_ACR_SLEEP_PD (1 << 14) /* Bit 14: Flash mode during Sleep */
|
||||
|
||||
/* Flash Status Register (SR) */
|
||||
|
||||
#define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
|
||||
#define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
|
||||
#define FLASH_SR_PROGERR (1 << 3) /* Bit 3: Programming error */
|
||||
#define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
|
||||
#define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
|
||||
#define FLASH_SR_SIZERR (1 << 6) /* Bit 6: Size error */
|
||||
#define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
|
||||
#define FLASH_SR_MISERR (1 << 8) /* Bit 8: Fast programming data miss error */
|
||||
#define FLASH_SR_FASTERR (1 << 9) /* Bit 9: Fast programming error */
|
||||
#define FLASH_SR_RDERR (1 << 14) /* Bit 14: PCROP read error */
|
||||
#define FLASH_SR_OPTVERR (1 << 15) /* Bit 15: Option validity error */
|
||||
#define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3)
|
||||
# define FLASH_SR_PEMPTY (1 << 17) /* Bit 17: Program empty */
|
||||
#endif
|
||||
|
||||
/* Flash Control Register (CR) */
|
||||
|
||||
#define FLASH_CR_PG (1 << 0) /* Bit 0 : Program Page */
|
||||
#define FLASH_CR_PER (1 << 1) /* Bit 1 : Page Erase */
|
||||
#define FLASH_CR_MER1 (1 << 2) /* Bit 2 : Mass Erase Bank 1 */
|
||||
|
||||
#define FLASH_CR_PNB_SHIFT (3) /* Bits 3-10: Page number */
|
||||
#define FLASH_CR_PNB_MASK (0xFF << FLASH_CR_PNB_SHIFT)
|
||||
#define FLASH_CR_PNB(n) ((n) << FLASH_CR_PNB_SHIFT) /* Page n (if BKER=0) or n+256 (if BKER=1), n=0..255 */
|
||||
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# define FLASH_CR_BKER (1 << 11) /* Bit 11: Page number MSB (Bank selection) */
|
||||
# define FLASH_CR_MER2 (1 << 15) /* Bit 15: Mass Erase Bank 2 */
|
||||
#endif
|
||||
#define FLASH_CR_START (1 << 16) /* Bit 16: Start Erase */
|
||||
#define FLASH_CR_OPTSTRT (1 << 17) /* Bit 17: Options modification Start */
|
||||
#define FLASH_CR_FSTPG (1 << 23) /* Bit 23: Fast programming */
|
||||
#define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
|
||||
#define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
|
||||
#define FLASH_CR_RDERRIE (1 << 26) /* Bit 26: PCROP read error interrupt enable */
|
||||
#define FLASH_CR_OBL_LAUNCH (1 << 27) /* Bit 27: Option Byte Loading */
|
||||
#define FLASH_CR_OPTLOCK (1 << 30) /* Bit 30: Option Lock */
|
||||
#define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
|
||||
|
||||
/* Flash ECC Register (ECCR) */
|
||||
|
||||
#define FLASH_ECCR_ADDR_ECC_SHIFT (0) /* Bits 8-15: Read protect */
|
||||
#define FLASH_ECCR_ADDR_ECC_MASK (0x07ffff << FLASH_ECCR_ADDR_ECC_SHIFT)
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# define FLASH_ECCR_BK_ECC (1 << 19) /* Bit 19: ECC fail bank */
|
||||
#endif
|
||||
#define FLASH_ECCR_SYSF_ECC (1 << 20) /* Bit 20: System Flash ECC fail */
|
||||
#define FLASH_ECCR_ECCCIE (1 << 24) /* Bit 24: ECC correction interrupt enable */
|
||||
#define FLASH_ECCR_ECCC (1 << 30) /* Bit 30: ECC correction */
|
||||
#define FLASH_ECCR_ECCD (1 << 31) /* Bit 31: ECC detection */
|
||||
|
||||
/* Flash Option Control Register (OPTCR) */
|
||||
|
||||
#define FLASH_OPTCR_NRST_STOP (1 << 12) /* Bit 12: Generate reset when entering the Stop mode */
|
||||
#define FLASH_OPTCR_NRST_STDBY (1 << 13) /* Bit 13: Generate reset when entering the Standby mode */
|
||||
#define FLASH_OPTCR_NRST_SHDW (1 << 14) /* Bit 14: Generate reset when entering the Shutdown mode */
|
||||
#define FLASH_OPTCR_IWDG_SW (1 << 16) /* Bit 16: Independent watchdog selection */
|
||||
#define FLASH_OPTCR_IWDG_STOP (1 << 17) /* Bit 17: Independent watchdog counter freeze in Stop mode */
|
||||
#define FLASH_OPTCR_IWDG_STDBY (1 << 18) /* Bit 18: Independent watchdog counter freeze in Standby mode*/
|
||||
#define FLASH_OPTCR_WWDG_SW (1 << 19) /* Bit 19: Window watchdog selection */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X6)
|
||||
# define FLASH_OPTCR_BFB2 (1 << 20) /* Bit 20: Dual bank boot */
|
||||
# define FLASH_OPTCR_DUALBANK (1 << 21) /* Bit 21: Dual bank enable */
|
||||
#endif
|
||||
#define FLASH_OPTCR_NBOOT1 (1 << 23) /* Bit 23: Boot configuration */
|
||||
#define FLASH_OPTCR_SRAM2_PE (1 << 24) /* Bit 24: SRAM2 parity check enable */
|
||||
#define FLASH_OPTCR_SRAM2_RST (1 << 25) /* Bit 25: SRAM2 Erase when system reset */
|
||||
#if defined(CONFIG_STM32L4_STM32L4X3) || defined(CONFIG_STM32L4_STM32L496XX)
|
||||
# define FLASH_OPTCR_NSWBOOT0 (1 << 26) /* Bit 26: Software BOOT0 */
|
||||
# define FLASH_OPTCR_NBOOT0 (1 << 27) /* Bit 27: nBOOT0 option bit */
|
||||
#endif
|
||||
|
||||
#define FLASH_OPTCR_BORLEV_SHIFT (8) /* Bits 8-10: BOR reset Level */
|
||||
#define FLASH_OPTCR_BORLEV_MASK (7 << FLASH_OPTCR_BORLEV_SHIFT)
|
||||
#define FLASH_OPTCR_VBOR0 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* 000: BOR Level 0 (1.7 V) */
|
||||
#define FLASH_OPTCR_VBOR1 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* 001: BOR Level 1 (2.0 V) */
|
||||
#define FLASH_OPTCR_VBOR2 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* 010: BOR Level 2 (2.2 V) */
|
||||
#define FLASH_OPTCR_VBOR3 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* 011: BOR Level 3 (2.5 V) */
|
||||
#define FLASH_OPTCR_VBOR4 (4 << FLASH_OPTCR_BORLEV_SHIFT) /* 100: BOR Level 4 (2.8 V) */
|
||||
#define FLASH_OPTCR_RDP_SHIFT (0) /* Bits 0-7: Read Protection Level */
|
||||
#define FLASH_OPTCR_RDP_MASK (0xFF << FLASH_OPTCR_RDP_SHIFT)
|
||||
#define FLASH_OPTCR_RDP_NONE (0xAA << FLASH_OPTCR_RDP_SHIFT)
|
||||
#define FLASH_OPTCR_RDP_CHIP (0xCC << FLASH_OPTCR_RDP_SHIFT) /* WARNING, CANNOT BE REVERSED !! */
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/stm32l4_flash.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user