LPC1788 updates from Rommel Marcelo
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5696 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
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commit
309c3c2ff5
@ -70,10 +70,10 @@
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# define LPC17_EXTSRAM_CS2 0x98000000 /* Chip select 2 /up to 64MB/ */
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# define LPC17_EXTSRAM_CS3 0x9c000000 /* Chip select 3 /up to 64MB/ */
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# define LPC17_EXTDRAM_CS0 0x9c000000 /* Chip select 0 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS1 0x9c000000 /* Chip select 1 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS2 0x9c000000 /* Chip select 2 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS3 0x9c000000 /* Chip select 3 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS0 0xa0000000 /* Chip select 0 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS1 0xb0000000 /* Chip select 1 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS2 0xc0000000 /* Chip select 2 /up to 256MB/ */
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# define LPC17_EXTDRAM_CS3 0xd0000000 /* Chip select 3 /up to 256MB/ */
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#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
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#define LPC17_SCS_BASE 0xe000e000
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@ -119,7 +119,7 @@
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#define LPC17_UART2_BASE 0x40098000 /* -0x4009bfff: UART 2 */
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#define LPC17_UART3_BASE 0x4009c000 /* -0x4009ffff: UART 3 */
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#define LPC17_I2C2_BASE 0x400a0000 /* -0x400a3fff: I2C 2 */
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/* -0x400a7fff: Reserved */
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#define LPC17_UART4_BASE 0x400a4000 /* -0x400a7fff: UART4 */
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#define LPC17_I2S_BASE 0x400a8000 /* -0x400abfff: I2S */
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#define LPC17_SSP2_BASE 0x400ac000 /* -0x400affff: SSP2 */
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/* -0x400b3fff: Reserved */
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@ -76,7 +76,7 @@
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#define GPIO_I2S_RXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_CAN2_RD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_CAP2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_LCD_VD0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_LCD_VD0_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
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#define GPIO_I2S_RXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5)
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#define GPIO_CAN2_TD_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5)
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@ -87,25 +87,25 @@
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#define GPIO_SSP1_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_MAT2p0_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_UART1_RTS_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_LCD_VD8_1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_LCD_VD8_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
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#define GPIO_I2S_TXCLK_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_SSP1_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_MAT2p1_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_RTC_EV0_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_LCD_VD9_1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_LCD_VD9_1 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
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#define GPIO_I2S_TXWS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_SSP1_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_MAT2p2_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_RTC_EV1_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_LCD_VD16 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_LCD_VD16 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
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#define GPIO_I2S_TXSDA_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_SSP1_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_MAT2p3_1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_RTC_EV2_1 (GPIO_ALT4 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_LCD_VD17 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_LCD_VD17 (GPIO_ALT7 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
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#define GPIO_UART2_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
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#define GPIO_I2C2_SDA_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
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@ -129,19 +129,19 @@
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#define GPIO_UART1_TXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15)
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#define GPIO_SSP0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15)
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#define GPIO_SPIFI_IO2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15)
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#define GPIO_SPIFI_IO2 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN15)
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#define GPIO_UART1_RXD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16)
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#define GPIO_SSP0_SSEL_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16)
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#define GPIO_SPIFI_IO3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16)
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#define GPIO_SPIFI_IO3 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN16)
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#define GPIO_UART1_CTS_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
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#define GPIO_SSP0_MISO_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
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#define GPIO_SPIFI_IO1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
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#define GPIO_SPIFI_IO1 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN17)
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#define GPIO_UART1_DCD_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_SSP0_MOSI_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_SPIFI_IO0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_SPIFI_IO0 (GPIO_ALT5 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN18)
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#define GPIO_UART1_DSR_1 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19)
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#define GPIO_SD_CLK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN19)
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@ -57,7 +57,7 @@
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/* Memory Mapping Control register (MEMMAP - 0x400F C040) */
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#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control register */
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#define LPC17_SYSCON_MEMMAP_OFFSET 0x0040 /* Memory Mapping Control Register */
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/* Clocking and power control - Phase locked loops */
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@ -289,16 +289,16 @@
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/* Bits 9-31: Reserved */
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/* USB Clock Configuration register */
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#define SYSCON_USBCLKSEL_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */
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#define SYSCON_USBCLKSEL_USBDIV_MASK (0x1f << SYSCON_USBCLKSEL_USBDIV_SHIFT)
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# define SYSCON_USBCLKSEL_USBDIV_DIV1 (1 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
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# define SYSCON_USBCLKSEL_USBDIV_DIV2 (2 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
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# define SYSCON_USBCLKSEL_USBDIV_DIV3 (3 << SYSCON_USBCLKSEL_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
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#define SYSCON_USBCLKCFG_USBDIV_SHIFT (0) /* Bits 0-4: PLL0/1 divide value USB clock */
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#define SYSCON_USBCLKCFG_USBDIV_MASK (0x1f << SYSCON_USBCLKCFG_USBDIV_SHIFT)
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# define SYSCON_USBCLKCFG_USBDIV_DIV1 (1 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 48MHz */
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# define SYSCON_USBCLKCFG_USBDIV_DIV2 (2 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 96MHz */
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# define SYSCON_USBCLKCFG_USBDIV_DIV3 (3 << SYSCON_USBCLKCFG_USBDIV_SHIFT) /* PLL0/1 output must be 144MHz */
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/* Bits 5-7: Reserved */
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#define SYSCON_USBCLKSEL_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */
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#define SYSCON_USBCLKSEL_USBSEL_MASK (3 << SYSCON_USBCLKSEL_USBSEL_SHIFT)
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#define SYSCON_USBCLKSEL_USBSEL_PLL0 (1 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */
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#define SYSCON_USBCLKSEL_USBSEL_PLL1 (2 << SYSCON_USBCLKSEL_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */
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#define SYSCON_USBCLKCFG_USBSEL_SHIFT (8) /* Bits 8-9: Input clock to USBDIV */
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#define SYSCON_USBCLKCFG_USBSEL_MASK (3 << SYSCON_USBCLKCFG_USBSEL_SHIFT)
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#define SYSCON_USBCLKCFG_USBSEL_PLL0 (1 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 01: PLL0 is used as input clock to USBDIV */
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#define SYSCON_USBCLKCFG_USBSEL_PLL1 (2 << SYSCON_USBCLKCFG_USBSEL_SHIFT) /* 10: PLL1 is used as input clock to USBDIV */
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/* 11: unused */
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/* Bits 10-31: Reserved */
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/* CAN0/1 Sleep Clear Register */
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@ -134,9 +134,13 @@ void lpc17_clockconfig(void)
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL to report that it is connected and enabled */
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# if defined(LPC176x)
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC))
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!= (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC));
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# elif defined(LPC178x)
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE))
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!= (SYSCON_PLL0STAT_PLLE));
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# endif
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#endif
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/* PLL1 receives its clock input from the main oscillator only and can be used to
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@ -173,14 +177,19 @@ void lpc17_clockconfig(void)
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL to report that it is connected and enabled */
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# if defined(LPC176x)
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC))
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!= (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC));
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# elif defined(LPC178x)
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE))
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!= (SYSCON_PLL1STAT_PLLE));
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# endif
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#else
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/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
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#ifdef LPC176x
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putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG);
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#endif
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#endif /* LPC176x */
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/* Disable all peripheral clocks. They must be configured by each device driver
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* when the device driver is initialized.
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@ -273,8 +273,8 @@ static int lpc17_configiocon(unsigned int port, unsigned int pin,
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regaddr = LPC17_IOCON_P(port, pin);
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regval = getreg32(regaddr);
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regval &= value;
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regval &= ~typemask;
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regval |= value;
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regval &= typemask;
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putreg32(regval, regaddr);
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return OK;
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@ -702,6 +702,10 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
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#elif defined(LPC178x)
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uint32_t regval = 0;
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/* Set the alternate pin */
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regval |= (alt & IOCON_FUNC_MASK);
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/* Select open drain output */
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if ((cfgset & GPIO_OPEN_DRAIN) != 0)
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@ -709,21 +713,6 @@ static int lpc17_configalternate(lpc17_pinset_t cfgset, unsigned int port,
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regval |= IOCON_OD_MASK;
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}
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//~ /* Select slew output */
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//~
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//~ if ((cfgset & GPIO_SLEW) != 0)
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//~ {
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//~ regval |= IOCON_SLEW_MASK;
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//~ }
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/* Set pull-up mode */
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regval |= ((cfgset & GPIO_PUMODE_MASK) >> GPIO_PINMODE_SHIFT);
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/* Set the alternate pin */
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regval |= (alt & ~IOCON_FUNC_MASK);
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/* Set IOCON register */
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lpc17_configiocon(port, pin, regval);
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@ -69,7 +69,7 @@
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* Port number: PPP (0-4)
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* Pin number: NNNNN (0-31)
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*/
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/* Pin Function bits: FFF
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* Only meaningful when the GPIO function is GPIO_PIN
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*/
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@ -173,7 +173,7 @@
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#elif defined(LPC178x)
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/* Encoding: TTTT TTTT FFFF MMOV PPPN NNNN
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*
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*
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* Special Pin Functions: TTTT TTTT
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* Pin Function: FFFF
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* Pin Mode bits: MM
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@ -182,7 +182,7 @@
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* Port number: PPP (0-4)
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* Pin number: NNNNN (0-31)
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*/
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/* Special Pin Functions
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* For pins that has ADC/DAC, USB, I2C
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*/
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@ -241,13 +241,13 @@
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/* Pin Mode: MM */
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#define GPIO_PINMODE_SHIFT (7)
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#define GPIO_PINMODE_SHIFT (7)
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#define GPIO_PUMODE_SHIFT (10) /* Bits 10-11: Pin pull-up mode */
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#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
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# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
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# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
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# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
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# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
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# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
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# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
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# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
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# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
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/* Open drain: O */
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@ -85,8 +85,8 @@
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* The input to the divider (PLLCLK) will be determined by the PLL output.
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*/
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#define BOARD_CCLKCFG_DIVIDER 6
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#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_CCLKDIV_SHIFT)
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#define BOARD_CCLKCFG_DIVIDER 1
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#define BOARD_CCLKCFG_VALUE (BOARD_CCLKCFG_DIVIDER | SYSCON_CCLKCFG_CCLKSEL)
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/* PLL0. PLL0 is used to generate the CPU clock (PLLCLK).
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*
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@ -109,11 +109,11 @@
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/* PLL1 : PLL1 is used to generate clock for the USB */
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#undef CONFIG_LPC17_PLL1
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#define CONFIG_LPC17_PLL1 1
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#define BOARD_PLL1CFG_MSEL 4
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#define BOARD_PLL1CFG_PSEL 2
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#define BOARD_PLL1CFG_VALUE \
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#undef CONFIG_LPC17_PLL1
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//~ #define CONFIG_LPC17_PLL1 1
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#define BOARD_PLL1CFG_MSEL 4
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#define BOARD_PLL1CFG_PSEL 2
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#define BOARD_PLL1CFG_VALUE \
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(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLLCFG_MSEL_SHIFT) | \
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((BOARD_PLL1CFG_PSEL-1) << SYSCON_PLLCFG_PSEL_SHIFT))
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@ -135,7 +135,7 @@
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/* Flash access use 6 CPU clocks - Safe for any allowed conditions */
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#define BOARD_FLASHCFG_VALUE SYSCON_FLASHCFG_TIM_5
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#define BOARD_FLASHCFG_VALUE (SYSCON_FLASHCFG_TIM_5 | 0x03a)
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/* Ethernet configuration */
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@ -65,7 +65,7 @@ fi
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export TOOLCHAIN_BIN="${WD}/../misc/buildroot/build_arm_nofpu/staging_dir/bin"
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# The Olimex-lpc1766stk/tools directory
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export LPCTOOL_DIR="${WD}/configs/olimex-lpc1766stk/tools"
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export LPCTOOL_DIR="${WD}/configs/open1788/tools"
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# Add the path to the toolchain and tools directory to the PATH varialble
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export PATH="${TOOLCHAIN_BIN}:${LPCTOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}"
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@ -37,8 +37,8 @@
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/* The LPC1788 has 512Kb of FLASH beginning at address 0x0000:0000 and
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* 96Kb of total SRAM: 64Kb of SRAM in the CPU block beginning at address
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* 0x10000000 and 32Kb of Peripheral SRAM in two banks, 8Kb at addresses
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* 0x20000000 bank0 first and 8kb at 0x20020000 at bank0 second. And 16Kb
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* at 0x20040000 on bank1.
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* 0x20000000 bank0 first and 8kb at 0x20002000 at bank0 second. And 16Kb
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* at 0x20004000 on bank1.
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*
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* Here we assume that .data and .bss will all fit into the 64Kb CPU SRAM
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* address range.
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@ -48,8 +48,9 @@ MEMORY
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{
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FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 512K
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SRAM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K
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PSRAM0 (rwx) : ORIGIN = 0x20000000, LENGTH = 16K /* Peripheral SRAM Bank 0 */
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PSRAM1 (rwx) : ORIGIN = 0x20040000, LENGTH = 16K /* Peripheral SRAM Bank 1 */
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AHBRAM8_B0A(rwx): ORIGIN = 0x20000000, LENGTH = 8K
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AHBRAM8_B0B(rwx): ORIGIN = 0x20002000, LENGTH = 8K
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AHBRAM16(rwx): ORIGIN = 0x20004000, LENGTH = 16K
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}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
@ -86,6 +87,7 @@ SECTIONS
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > FLASH
|
||||
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
@ -105,20 +107,8 @@ SECTIONS
|
||||
*(COMMON)
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > SRAM
|
||||
/*
|
||||
.psram0 (NOLOAD) :
|
||||
{
|
||||
*(.psram0)
|
||||
. = ALIGN(4)
|
||||
} > PSRAM0
|
||||
|
||||
|
||||
.psram1 (NOLOAD) :
|
||||
{
|
||||
*(.psram1)
|
||||
. = ALIGN(4)
|
||||
} > PSRAM1
|
||||
*/
|
||||
/* Stabs debugging sections */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user