diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c
index f034f124c0..e9d1972f1e 100644
--- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c
+++ b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c
@@ -295,8 +295,8 @@ static void stm32_selectlcd(void)
 
   /* Bank1 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(2)  | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) |
-           FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
+  putreg32(FSMC_BTR_ADDSET(2)  | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) |
+           FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
            FSMC_BTR_ACCMODA,
            STM32_FSMC_BTR1);
 
diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c b/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c
index 46875308cf..788a81c3b8 100644
--- a/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c
+++ b/boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c
@@ -374,8 +374,8 @@ static void stm32_selectlcd(void)
 
   /* Bank1 NOR/SRAM timing register configuration */
 
-  putreg32(FSMC_BTR_ADDSET(1)  | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) |
-           FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
+  putreg32(FSMC_BTR_ADDSET(1)  | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) |
+           FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
            FSMC_BTR_ACCMODA,
            STM32_FSMC_BTR1);
 
diff --git a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c b/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c
index 4484fb9d5f..7e95b9210b 100644
--- a/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c
+++ b/boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c
@@ -53,11 +53,11 @@
  */
 
 #define SRAM_ADDRESS_SETUP_TIME      3
-#define SRAM_ADDRESS_HOLD_TIME       0
+#define SRAM_ADDRESS_HOLD_TIME       1
 #define SRAM_DATA_SETUP_TIME         6
 #define SRAM_BUS_TURNAROUND_DURATION 1
-#define SRAM_CLK_DIVISION            0
-#define SRAM_DATA_LATENCY            0
+#define SRAM_CLK_DIVISION            1
+#define SRAM_DATA_LATENCY            2
 
 /****************************************************************************
  * Public Data
diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c
index d5af1b7ae0..bfa7533448 100644
--- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c
+++ b/boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c
@@ -45,11 +45,11 @@
 /* SRAM Timing */
 
 #define SRAM_ADDRESS_SETUP_TIME      3
-#define SRAM_ADDRESS_HOLD_TIME       0
+#define SRAM_ADDRESS_HOLD_TIME       1
 #define SRAM_DATA_SETUP_TIME         6
 #define SRAM_BUS_TURNAROUND_DURATION 1
-#define SRAM_CLK_DIVISION            0
-#define SRAM_DATA_LATENCY            0
+#define SRAM_CLK_DIVISION            1
+#define SRAM_DATA_LATENCY            2
 
 /* SRAM pin definitions */
 
diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c
index 591853f04f..09193624ea 100644
--- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c
+++ b/boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c
@@ -45,11 +45,11 @@
 /* SRAM Timing */
 
 #define SRAM_ADDRESS_SETUP_TIME      3
-#define SRAM_ADDRESS_HOLD_TIME       0
+#define SRAM_ADDRESS_HOLD_TIME       1
 #define SRAM_DATA_SETUP_TIME         6
 #define SRAM_BUS_TURNAROUND_DURATION 1
-#define SRAM_CLK_DIVISION            0
-#define SRAM_DATA_LATENCY            0
+#define SRAM_CLK_DIVISION            1
+#define SRAM_DATA_LATENCY            2
 
 /* SRAM pin definitions */
 
diff --git a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c
index 6732cd6555..88be606edc 100644
--- a/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c
+++ b/boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c
@@ -443,8 +443,8 @@ static void stm32_selectlcd(void)
   /* Bank1 NOR/SRAM timing register configuration */
 
   putreg32(
-      FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) |
-      FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) |
+      FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) |
+      FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) |
       FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
       FSMC_BTR_ACCMODA,
       STM32_FSMC_BTR1);