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Fix Error: board/stm32_selectsram.c:163:13: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]

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FSMC_BTR_ADDHLD(SRAM_ADDRESS_HOLD_TIME) |
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:164:42: note: expanded from macro 'FSMC_BTR_ADDHLD'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
                                                     ^
Error: board/stm32_selectsram.c:166:13: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
            FSMC_BTR_CLKDIV(SRAM_CLK_DIVISION) |
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:176:42: note: expanded from macro 'FSMC_BTR_CLKDIV'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'
                                                     ^
Error: board/stm32_selectsram.c:167:13: error: shifting a negative signed value is undefined [-Werror,-Wshift-negative-value]
            FSMC_BTR_DATLAT(SRAM_DATA_LATENCY) |
            ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/github/workspace/sources/nuttx/arch/arm/src/chip/hardware/stm32_fsmc.h:180:42: note: expanded from macro 'FSMC_BTR_DATLAT'
                                         ^
/github/workspace/sources/nuttx/arch/arm/src/common/arm_internal.h:135:54: note: expanded from macro 'putreg32'

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2022-11-20 15:17:28 +08:00 committed by archer
parent 81b9df53fc
commit 30a01ab551
6 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c
View File

@ -295,8 +295,8 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */ /* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(2) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) | putreg32(FSMC_BTR_ADDSET(2) | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) |
FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1); STM32_FSMC_BTR1);

4
boards/arm/stm32/hymini-stm32v/src/stm32_ssd1289.c
View File

@ -374,8 +374,8 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */ /* Bank1 NOR/SRAM timing register configuration */
putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) | putreg32(FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) | FSMC_BTR_DATAST(2) |
FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | FSMC_BTR_BUSTURN(1) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1); STM32_FSMC_BTR1);

6
boards/arm/stm32/olimex-stm32-p407/src/stm32_sram.c
View File

@ -53,11 +53,11 @@
*/ */
#define SRAM_ADDRESS_SETUP_TIME 3 #define SRAM_ADDRESS_SETUP_TIME 3
#define SRAM_ADDRESS_HOLD_TIME 0 #define SRAM_ADDRESS_HOLD_TIME 1
#define SRAM_DATA_SETUP_TIME 6 #define SRAM_DATA_SETUP_TIME 6
#define SRAM_BUS_TURNAROUND_DURATION 1 #define SRAM_BUS_TURNAROUND_DURATION 1
#define SRAM_CLK_DIVISION 0 #define SRAM_CLK_DIVISION 1
#define SRAM_DATA_LATENCY 0 #define SRAM_DATA_LATENCY 2
/**************************************************************************** /****************************************************************************
* Public Data * Public Data

6
boards/arm/stm32/stm3220g-eval/src/stm32_selectsram.c
View File

@ -45,11 +45,11 @@
/* SRAM Timing */ /* SRAM Timing */
#define SRAM_ADDRESS_SETUP_TIME 3 #define SRAM_ADDRESS_SETUP_TIME 3
#define SRAM_ADDRESS_HOLD_TIME 0 #define SRAM_ADDRESS_HOLD_TIME 1
#define SRAM_DATA_SETUP_TIME 6 #define SRAM_DATA_SETUP_TIME 6
#define SRAM_BUS_TURNAROUND_DURATION 1 #define SRAM_BUS_TURNAROUND_DURATION 1
#define SRAM_CLK_DIVISION 0 #define SRAM_CLK_DIVISION 1
#define SRAM_DATA_LATENCY 0 #define SRAM_DATA_LATENCY 2
/* SRAM pin definitions */ /* SRAM pin definitions */

6
boards/arm/stm32/stm3240g-eval/src/stm32_selectsram.c
View File

@ -45,11 +45,11 @@
/* SRAM Timing */ /* SRAM Timing */
#define SRAM_ADDRESS_SETUP_TIME 3 #define SRAM_ADDRESS_SETUP_TIME 3
#define SRAM_ADDRESS_HOLD_TIME 0 #define SRAM_ADDRESS_HOLD_TIME 1
#define SRAM_DATA_SETUP_TIME 6 #define SRAM_DATA_SETUP_TIME 6
#define SRAM_BUS_TURNAROUND_DURATION 1 #define SRAM_BUS_TURNAROUND_DURATION 1
#define SRAM_CLK_DIVISION 0 #define SRAM_CLK_DIVISION 1
#define SRAM_DATA_LATENCY 0 #define SRAM_DATA_LATENCY 2
/* SRAM pin definitions */ /* SRAM pin definitions */

4
boards/arm/stm32/viewtool-stm32f107/src/stm32_ssd1289.c
View File

@ -443,8 +443,8 @@ static void stm32_selectlcd(void)
/* Bank1 NOR/SRAM timing register configuration */ /* Bank1 NOR/SRAM timing register configuration */
putreg32( putreg32(
FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_ADDSET(1) | FSMC_BTR_ADDHLD(1) |
FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(1) |
FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) | FSMC_BTR_CLKDIV(1) | FSMC_BTR_DATLAT(2) |
FSMC_BTR_ACCMODA, FSMC_BTR_ACCMODA,
STM32_FSMC_BTR1); STM32_FSMC_BTR1);