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Fix chip/stm32l562xx_rcc.c:78:20: error: unused function 'rcc_reset'

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao 2022-11-20 12:03:25 +08:00 committed by archer
parent 59a747ee36
commit 30a153d2a0
1 changed files with 0 additions and 44 deletions
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44
arch/arm/src/stm32l5/stm32l562xx_rcc.c
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@ -67,50 +67,6 @@
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: rcc_reset
*
* Description:
* Reset the RCC clock configuration to the default reset state
*
****************************************************************************/
static inline void rcc_reset(void)
{
uint32_t regval;
/* Enable the multispeed internal clock (MSI) @ 4MHz */
regval = getreg32(STM32L5_RCC_CR);
regval &= ~RCC_CR_MSIRANGE_MASK;
regval |= RCC_CR_MSION | RCC_CR_MSIRANGE_4M;
putreg32(regval, STM32L5_RCC_CR);
/* Reset CFGR register */
putreg32(0x00000000, STM32L5_RCC_CFGR);
/* Reset HSION, HSEON, CSSON and PLLON bits */
regval = getreg32(STM32L5_RCC_CR);
regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32L5_RCC_CR);
/* Reset PLLCFGR register to reset default */
putreg32(RCC_PLLCFG_RESET, STM32L5_RCC_PLLCFG);
/* Reset HSEBYP bit */
regval = getreg32(STM32L5_RCC_CR);
regval &= ~RCC_CR_HSEBYP;
putreg32(regval, STM32L5_RCC_CR);
/* Disable all interrupts */
putreg32(0x00000000, STM32L5_RCC_CIER);
}
/****************************************************************************
* Name: rcc_enableahb1
*