Updates to SAM4L clocking. Still not finished
This commit is contained in:
Gregory Nutt
parent
19b38fa95f
commit
30f5d90430
@ -141,6 +141,11 @@ config ARCH_CHIP_SAM4S
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menu "AT91SAM3 Peripheral Support"
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config SAM_PICOCACHE
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bool "PICOCACHE"
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depends on ARCH_CHIP_SAM4L
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default y
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config SAM34_DMA
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bool "DMA"
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default n
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@ -132,13 +132,15 @@
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/* CPU Clock Select Register Bit-field Definitions */
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#define PM_CPUSEL_SHIFT (0) /* Bits 0-2: CPU Clock Select */
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#define PM_CPUSEL_MASK (7 << PM_CPUSEL_CPUSEL_SHIFT)
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#define PM_CPUSEL_CPUDIV (1 << 7) /* Bit 7: CPU Division */
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#define PM_CPUSEL_MASK (7 << PM_CPUSEL_SHIFT)
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# define PM_CPUSEL(n) ((n) << PM_CPUSEL_SHIFT)
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#define PM_CPUSEL_DIV (1 << 7) /* Bit 7: CPU Division */
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/* PBA/PBB/PBC/PBD Clock Select Register Bit-field Definitions */
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#define PM_PBSEL_SHIFT (0) /* Bits 0-2: PBx Clock Select */
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#define PM_PBSEL_MASK (7 << PM_PBASEL_SHIFT)
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#define PM_PBSEL_MASK (7 << PM_PBSEL_SHIFT)
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# define PM_PBSEL(n) ((n) << PM_PBSEL_SHIFT)
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#define PM_PBSEL_DIV (1 << 7) /* Bit 7: PBx Division */
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/* CPU Mask Register Bit-field Definitions */
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@ -228,8 +230,10 @@
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#define PM_UNLOCK_ADDR_SHIFT (0) /* Bits 0-9: Unlock Address */
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#define PM_UNLOCK_ADDR_MASK (0x3ff << PM_UNLOCK_ADDR_SHIFT)
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# define PM_UNLOCK_ADDR(n) ((n) << PM_UNLOCK_ADDR_SHIFT)
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#define PM_UNLOCK_KEY_SHIFT (24) /* Bits 24-31: Unlock Key */
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#define PM_UNLOCK_KEY_MASK (0xff << PM_UNLOCK_KEY_SHIFT)
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# define PM_UNLOCK_KEY(n) ((n) << PM_UNLOCK_KEY_SHIFT)
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/* Interrupt Enable Register Bit-field Definitions */
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/* Interrupt Disable Register Bit-field Definitions */
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@ -41,6 +41,7 @@
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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@ -49,6 +50,8 @@
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#include "chip/sam4l_pm.h"
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#include "chip/sam4l_flashcalw.h"
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#include "sam_clockconfig.h"
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/****************************************************************************
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* Private Definitions
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****************************************************************************/
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@ -86,16 +89,41 @@
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****************************************************************************/
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/****************************************************************************
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* Name: up_enableosc32
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* Name: sam_picocache
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*
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* Description:
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* Initialiaze the 32KHz oscillaor. This oscillaor is used by the RTC
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* Initialiaze the PICOCACHE.
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*
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****************************************************************************/
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#ifdef CONFIG_SAM_PICOCACHE
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static inline void sam_picocache(void)
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{
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/* Enable clocking to the PICOCACHE */
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sam_hsb_enableperipheral(PM_HSBMASK_HRAMC1);
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sam_pbb_enableperipheral(PM_PBBMASK_HRAMC1);
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/* Enable the PICOCACHE and wait for it to become ready */
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putreg32(PICOCACHE_CTRL_CEN, SAM_PICOCACHE_CTRL);
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while ((getreg32(SAM_PICOCACHE_SR) & PICOCACHE_SR_CSTS) == 0);
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}
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#else
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# define sam_picocache()
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#endif
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/****************************************************************************
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* Name: sam_enableosc32
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*
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* Description:
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* Initialiaze the 32KHz oscillator. This oscillator is used by the RTC
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* logic to provide the sysem timer.
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*
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****************************************************************************/
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#ifdef SAM_CLOCK_OSC32
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static inline void up_enableosc32(void)
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static inline void sam_enableosc32(void)
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{
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uint32_t regval;
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@ -116,7 +144,7 @@ static inline void up_enableosc32(void)
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#endif
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/****************************************************************************
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* Name: up_enableosc0
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* Name: sam_enableosc0
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*
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* Description:
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* Initialiaze OSC0 settings per the definitions in the board.h file.
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@ -124,7 +152,7 @@ static inline void up_enableosc32(void)
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****************************************************************************/
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#ifdef NEED_OSC0
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static inline void up_enableosc0(void)
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static inline void sam_enableosc0(void)
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{
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uint32_t regval;
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@ -165,7 +193,7 @@ static inline void up_enableosc0(void)
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#endif
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/****************************************************************************
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* Name: up_enableosc1
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* Name: sam_enableosc1
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*
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* Description:
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* Initialiaze OSC0 settings per the definitions in the board.h file.
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@ -173,7 +201,7 @@ static inline void up_enableosc0(void)
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****************************************************************************/
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#ifdef NEED_OSC1
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static inline void up_enableosc1(void)
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static inline void sam_enableosc1(void)
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{
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uint32_t regval;
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@ -214,7 +242,7 @@ static inline void up_enableosc1(void)
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#endif
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/****************************************************************************
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* Name: up_enablepll0
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* Name: sam_enablepll0
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*
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* Description:
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* Initialiaze PLL0 settings per the definitions in the board.h file.
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@ -222,7 +250,7 @@ static inline void up_enableosc1(void)
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****************************************************************************/
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#ifdef SAM_CLOCK_PLL0
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static inline void up_enablepll0(void)
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static inline void sam_enablepll0(void)
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{
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/* Setup PLL0 */
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@ -264,7 +292,7 @@ static inline void up_enablepll0(void)
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#endif
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/****************************************************************************
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* Name: up_enablepll1
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* Name: sam_enablepll1
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*
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* Description:
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* Initialiaze PLL1 settings per the definitions in the board.h file.
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@ -272,7 +300,7 @@ static inline void up_enablepll0(void)
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****************************************************************************/
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#ifdef SAM_CLOCK_PLL1
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static inline void up_enablepll1(void)
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static inline void sam_enablepll1(void)
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{
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/* Setup PLL1 */
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@ -314,53 +342,84 @@ static inline void up_enablepll1(void)
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#endif
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/****************************************************************************
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* Name: up_clksel
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* Name: sam_setdividers
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*
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* Description:
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* Configure derived clocks.
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*
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****************************************************************************/
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static inline void up_clksel(void)
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static inline void sam_setdividers(uint32_t cpudiv, uint32_t pbadiv,
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uint32_t pbbdiv, uint32_t pbcdiv,
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uint32_t pbddiv)
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{
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uint32_t regval = 0;
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irqstate_t flags;
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uint32_t cpusel = 0;
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uint32_t pbasel = 0;
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uint32_t pbbsel = 0;
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uint32_t pbcsel = 0;
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uint32_t pbdsel = 0;
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#if SAM_CKSEL_CPUDIV != 0
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regval |= PM_CKSEL_CPUDIV;
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regval |= (SAM_CKSEL_CPUDIV << PM_CKSEL_CPUSEL_SHIFT)
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#endif
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/* Get the register setting for each divider value */
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#if SAM_CKSEL_HSBDIV != 0
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regval |= PM_CKSEL_HSBDIV;
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regval |= (SAM_CKSEL_HSBDIV << PM_CKSEL_HSBSEL_SHIFT)
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#endif
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if (cpudiv > 0)
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{
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cpusel = (PM_CPUSEL(cpudiv - 1)) | PM_CPUSEL_DIV;
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}
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#if SAM_CKSEL_PBADIV != 0
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regval |= PM_CKSEL_PBADIV;
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regval |= (SAM_CKSEL_PBADIV << PM_CKSEL_PBASEL_SHIFT)
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#endif
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if (pbadiv > 0)
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{
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pbasel = (PM_PBSEL(pbadiv - 1)) | PM_PBSEL_DIV;
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}
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#if SAM_CKSEL_PBBDIV != 0
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regval |= PM_CKSEL_PBBDIV;
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regval |= (SAM_CKSEL_PBBDIV << PM_CKSEL_PBBSEL_SHIFT)
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#endif
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if (pbbdiv > 0)
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{
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pbbsel = (PM_PBSEL(pbbdiv - 1)) | PM_PBSEL_DIV;
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}
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putreg32(regval, SAM_PM_CKSEL);
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if (pbcdiv > 0)
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{
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pbcsel = (PM_PBSEL(pbcdiv - 1)) | PM_PBSEL_DIV;
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}
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/* Wait for CLKRDY */
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if (pbddiv > 0)
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{
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pbdsel = (PM_PBSEL(pbddiv - 1)) | PM_PBSEL_DIV;
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}
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while ((getreg32(SAM_PM_POSCSR) & PM_POSCSR_CKRDY) == 0);
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/* Then set the divider values. The following operations need to be atomic
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* for the unlock-write sequeuences.
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*/
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flags = irqsave();
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK);
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putreg32(cpusel, SAM_PM_CPUSEL);
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET), SAM_PM_UNLOCK);
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putreg32(pbasel, SAM_PM_PBASEL);
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET), SAM_PM_UNLOCK);
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putreg32(pbbsel, SAM_PM_PBBSEL);
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET), SAM_PM_UNLOCK);
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putreg32(pbcsel, SAM_PM_PBCSEL);
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK);
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putreg32(pbdsel, SAM_PM_PBDSEL);
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irqrestore(flags);
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}
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/****************************************************************************
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* Name: up_fws
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* Name: sam_fws
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*
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* Description:
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* Setup FLASH wait states.
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*
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****************************************************************************/
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static void up_fws(uint32_t cpuclock)
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static void sam_fws(uint32_t cpuclock)
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{
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uint32_t regval;
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@ -373,18 +432,19 @@ static void up_fws(uint32_t cpuclock)
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{
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regval &= ~FLASHCALW_FCR_FWS;
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}
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putreg32(regval, SAM_FLASHCALW_FCR);
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}
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/****************************************************************************
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* Name: up_mainclk
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* Name: sam_mainclk
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*
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* Description:
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* Select the main clock.
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*
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****************************************************************************/
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static inline void up_mainclk(uint32_t mcsel)
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static inline void sam_mainclk(uint32_t mcsel)
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{
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uint32_t regval;
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@ -395,7 +455,7 @@ static inline void up_mainclk(uint32_t mcsel)
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}
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/****************************************************************************
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* Name: up_usbclock
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* Name: sam_usbclock
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*
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* Description:
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* Setup the USBB GCLK.
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@ -403,7 +463,7 @@ static inline void up_mainclk(uint32_t mcsel)
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****************************************************************************/
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#ifdef CONFIG_USBDEV
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static inline void up_usbclock(void)
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static inline void sam_usbclock(void)
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{
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uint32_t regval = 0;
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@ -445,62 +505,216 @@ static inline void up_usbclock(void)
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void sam_clockconfig(void)
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{
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/* Enable clocking to the PICOCACHE */
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sam_picocache();
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/* Configure dividers derived clocks. These divider definitions must be
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* provided in the board.h header file.
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*/
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sam_setdividers(BOARD_SYSCLK_CPU_DIV, BOARD_SYSCLK_PBA_DIV,
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BOARD_SYSCLK_PBB_DIV, BOARD_SYSCLK_PBC_DIV,
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BOARD_SYSCLK_PBD_DIV);
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#ifdef SAM_CLOCK_OSC32
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/* Enable the 32KHz oscillator (need by the RTC module) */
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up_enableosc32();
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sam_enableosc32();
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#endif
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#ifdef NEED_OSC0
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/* Enable OSC0 using the settings in board.h */
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up_enableosc0();
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sam_enableosc0();
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/* Set up FLASH wait states */
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up_fws(SAM_FOSC0);
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sam_fws(SAM_FOSC0);
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/* Then switch the main clock to OSC0 */
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up_mainclk(PM_MCCTRL_MCSEL_OSC0);
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sam_mainclk(PM_MCCTRL_MCSEL_OSC0);
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#endif
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#ifdef NEED_OSC1
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/* Enable OSC1 using the settings in board.h */
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up_enableosc1();
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sam_enableosc1();
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#endif
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#ifdef SAM_CLOCK_PLL0
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/* Enable PLL0 using the settings in board.h */
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up_enablepll0();
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sam_enablepll0();
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/* Set up FLASH wait states */
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up_fws(SAM_CPU_CLOCK);
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sam_fws(SAM_CPU_CLOCK);
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/* Then switch the main clock to PLL0 */
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up_mainclk(PM_MCCTRL_MCSEL_PLL0);
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sam_mainclk(PM_MCCTRL_MCSEL_PLL0);
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#endif
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#ifdef SAM_CLOCK_PLL1
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/* Enable PLL1 using the settings in board.h */
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up_enablepll1();
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sam_enablepll1();
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#endif
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/* Configure derived clocks */
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up_clksel();
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/* Set up the USBB GCLK */
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#ifdef CONFIG_USBDEV
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void up_usbclock();
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void sam_usbclock();
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#endif
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}
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/****************************************************************************
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* Name: sam_modifyperipheral
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*
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* Description:
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* This is a convenience function that is intended to be used to enable
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* or disable peripheral module clocking.
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*
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****************************************************************************/
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void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits)
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{
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irqstate_t flags;
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uint32_t regval;
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/* Make sure that the following operations are atomic */
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flags = irqsave();
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/* Enable/disabling clocking */
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regval = getreg32(regaddr);
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regval &= ~clrbits;
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regval |= setbits;
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putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(regaddr - SAM_PM_BASE), SAM_PM_UNLOCK);
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putreg32(regval, regaddr);
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irqrestore(flags);
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}
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/****************************************************************************
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* Name: sam_pba_enableperipheral
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*
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* Description:
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* This is a convenience function to enable a peripheral on the APBA
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* bridge.
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*
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****************************************************************************/
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void sam_pba_enableperipheral(uint32_t bitset)
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{
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irqstate_t flags;
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/* The following operations must be atomic */
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flags = irqsave();
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/* Enable the APBA bridge if necessary */
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if (getreg32(SAM_PM_PBAMASK) == 0)
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{
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sam_hsb_enableperipheral(PM_HSBMASK_APBA);
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}
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irqrestore(flags);
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/* Enable the module */
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sam_enableperipheral(SAM_PM_PBAMASK, bitset);
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}
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/****************************************************************************
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* Name: sam_pba_disableperipheral
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*
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* Description:
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* This is a convenience function to disable a peripheral on the APBA
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* bridge.
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*
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****************************************************************************/
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void sam_pba_disableperipheral(uint32_t bitset)
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{
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irqstate_t flags;
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/* Disable clocking to the module */
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sam_disableperipheral(SAM_PM_PBAMASK, bitset);
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/* Disable the APBA bridge if possible */
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flags = irqsave();
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if (getreg32(SAM_PM_PBAMASK) == 0)
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{
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sam_hsb_disableperipheral(PM_HSBMASK_APBA);
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}
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irqrestore(flags);
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}
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/****************************************************************************
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* Name: sam_pbb_enableperipheral
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*
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* Description:
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* This is a convenience function to enable a peripheral on the APBB
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* bridge.
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*
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****************************************************************************/
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void sam_pbb_enableperipheral(uint32_t bitset)
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{
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irqstate_t flags;
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/* The following operations must be atomic */
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|
||||
flags = irqsave();
|
||||
|
||||
/* Enable the APBB bridge if necessary */
|
||||
|
||||
if (getreg32(SAM_PM_PBBMASK) == 0)
|
||||
{
|
||||
sam_hsb_enableperipheral(PM_HSBMASK_APBB);
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
|
||||
/* Enable the module */
|
||||
|
||||
sam_enableperipheral(SAM_PM_PBBMASK, bitset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_pbb_disableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to disable a peripheral on the APBA
|
||||
* bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_pbb_disableperipheral(uint32_t bitset)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Disable clocking to the peripheral module */
|
||||
|
||||
sam_disableperipheral(SAM_PM_PBBMASK, bitset);
|
||||
|
||||
/* Disable the APBB bridge if possible */
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
if (getreg32(SAM_PM_PBBMASK) == 0)
|
||||
{
|
||||
sam_hsb_disableperipheral(PM_HSBMASK_APBB);
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
@ -43,9 +43,26 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* SAM4L helper functions */
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
# define sam_enableperipheral(a,s) sam_modifyperipheral(a,0,s)
|
||||
# define sam_disableperipheral(a,s) sam_modifyperipheral(a,s,0)
|
||||
|
||||
# define sam_cpu_enableperipheral(s) sam_enableperipheral(SAM_PM_CPUMASK,s)
|
||||
# define sam_hsb_enableperipheral(s) sam_enableperipheral(SAM_PM_HSBMASK,s)
|
||||
# define sam_pbc_enableperipheral(s) sam_enableperipheral(SAM_PM_PBCMASK,s)
|
||||
# define sam_pbd_enableperipheral(s) sam_enableperipheral(SAM_PM_PBDMASK,s)
|
||||
|
||||
# define sam_cpu_disableperipheral(s) sam_disableperipheral(SAM_PM_CPUMASK,s)
|
||||
# define sam_hsb_disableperipheral(s) sam_disableperipheral(SAM_PM_HSBMASK,s)
|
||||
# define sam_pbc_enableperipheral(s) sam_enableperipheral(SAM_PM_PBCMASK,s)
|
||||
# define sam_pbd_enableperipheral(s) sam_enableperipheral(SAM_PM_PBDMASK,s)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
@ -85,6 +102,71 @@ extern "C"
|
||||
|
||||
void sam_clockconfig(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_modifyperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function that is intended to be used to enable
|
||||
* or disable module clocking.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_pba_enableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to enable a peripheral on the APBA
|
||||
* bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pba_enableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_pba_disableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to disable a peripheral on the APBA
|
||||
* bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pba_disableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_pbb_enableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to enable a peripheral on the APBB
|
||||
* bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pbb_enableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_pbb_disableperipheral
|
||||
*
|
||||
* Description:
|
||||
* This is a convenience function to disable a peripheral on the APBA
|
||||
* bridge.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
void sam_pbb_disableperipheral(uint32_t bitset);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user