Add WDT header file
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2694 42af7a65-404d-4744-a932-0658087f49c3
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@ -80,48 +80,48 @@
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/* Register addresses ***************************************************************/
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/* GPIO block register addresses ****************************************************/
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#define LPC17X_FIO_BASE(n) (LPC17X_GPIO_BASE+LPC17_GPIOINT(n))
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#define LPC17X_FIO0_BASE (LPC17X_GPIO_BASE+LPC17_FIO0_OFFSET)
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#define LPC17X_FIO1_BASE (LPC17X_GPIO_BASE+LPC17_FIO1_OFFSET)
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#define LPC17X_FIO2_BASE (LPC17X_GPIO_BASE+LPC17_FIO2_OFFSET)
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#define LPC17X_FIO3_BASE (LPC17X_GPIO_BASE+LPC17_FIO3_OFFSET)
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#define LPC17X_FIO4_BASE (LPC17X_GPIO_BASE+LPC17_FIO4_OFFSET)
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#define LPC17_FIO_BASE(n) (LPC17_GPIO_BASE+LPC17_GPIOINT(n))
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#define LPC17_FIO0_BASE (LPC17_GPIO_BASE+LPC17_FIO0_OFFSET)
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#define LPC17_FIO1_BASE (LPC17_GPIO_BASE+LPC17_FIO1_OFFSET)
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#define LPC17_FIO2_BASE (LPC17_GPIO_BASE+LPC17_FIO2_OFFSET)
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#define LPC17_FIO3_BASE (LPC17_GPIO_BASE+LPC17_FIO3_OFFSET)
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#define LPC17_FIO4_BASE (LPC17_GPIO_BASE+LPC17_FIO4_OFFSET)
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#define LPC17_FIO_DIR(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO_MASK(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO_PIN(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO_SET(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO_CLR(n) (LPC17X_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO_DIR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO_MASK(n) (LPC17_FIO_BASE(n)+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO_PIN(n) (LPC17_FIO_BASE(n)+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO_SET(n) (LPC17_FIO_BASE(n)+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO_CLR(n) (LPC17_FIO_BASE(n)+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO0_DIR (LPC17X_FIO0_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO0_MASK (LPC17X_FIO0_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO0_PIN (LPC17X_FIO0_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO0_SET (LPC17X_FIO0_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO0_CLR (LPC17X_FIO0_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO0_DIR (LPC17_FIO0_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO0_MASK (LPC17_FIO0_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO0_PIN (LPC17_FIO0_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO0_SET (LPC17_FIO0_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO0_CLR (LPC17_FIO0_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO1_DIR (LPC17X_FIO1_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO1_MASK (LPC17X_FIO1_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO1_PIN (LPC17X_FIO1_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO1_SET (LPC17X_FIO1_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO1_CLR (LPC17X_FIO1_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO1_DIR (LPC17_FIO1_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO1_MASK (LPC17_FIO1_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO1_PIN (LPC17_FIO1_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO1_SET (LPC17_FIO1_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO1_CLR (LPC17_FIO1_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO2_DIR (LPC17X_FIO2_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO2_MASK (LPC17X_FIO2_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO2_PIN (LPC17X_FIO2_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO2_SET (LPC17X_FIO2_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO2_CLR (LPC17X_FIO2_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO2_DIR (LPC17_FIO2_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO2_MASK (LPC17_FIO2_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO2_PIN (LPC17_FIO2_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO2_SET (LPC17_FIO2_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO2_CLR (LPC17_FIO2_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO3_DIR (LPC17X_FIO3_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO3_MASK (LPC17X_FIO3_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO3_PIN (LPC17X_FIO3_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO3_SET (LPC17X_FIO3_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO3_CLR (LPC17X_FIO3_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO3_DIR (LPC17_FIO3_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO3_MASK (LPC17_FIO3_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO3_PIN (LPC17_FIO3_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO3_SET (LPC17_FIO3_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO3_CLR (LPC17_FIO3_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO4_DIR (LPC17X_FIO4_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO4_MASK (LPC17X_FIO4_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO4_PIN (LPC17X_FIO4_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO4_SET (LPC17X_FIO4_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO4_CLR (LPC17X_FIO4_BASE+LPC17_FIO_CLR_OFFSET)
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#define LPC17_FIO4_DIR (LPC17_FIO4_BASE+LPC17_FIO_DIR_OFFSET)
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#define LPC17_FIO4_MASK (LPC17_FIO4_BASE+LPC17_FIO_MASK_OFFSET)
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#define LPC17_FIO4_PIN (LPC17_FIO4_BASE+LPC17_FIO_PIN_OFFSET)
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#define LPC17_FIO4_SET (LPC17_FIO4_BASE+LPC17_FIO_SET_OFFSET)
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#define LPC17_FIO4_CLR (LPC17_FIO4_BASE+LPC17_FIO_CLR_OFFSET)
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/* GPIO interrupt block register addresses ******************************************/
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@ -50,17 +50,17 @@
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/* Memory Map ***********************************************************************/
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#define LPC17X_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatilenmemory */
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#define LPC17X_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
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#define LPC17X_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
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#define LPC17X_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
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# define LPC17X_SRAM_BANK0 0x20070000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
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# define LPC17X_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank0 (devices 64Kb) */
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#define LPC17X_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
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#define LPC17X_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
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# define LPC17X_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
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# define LPC17X_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
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# define LPC17X_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
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#define LPC17_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatilenmemory */
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#define LPC17_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=32Kb) */
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#define LPC17_ROM_BASE 0x1fff0000 /* -0x1fffffff: 8Kb Boot ROM with flash services */
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#define LPC17_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
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# define LPC17_SRAM_BANK0 0x20070000 /* -0x2007ffff: On-chip AHB SRAM Bank0 (devices >=32Kb) */
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# define LPC17_SRAM_BANK1 0x20080000 /* -0x2008ffff: On-chip AHB SRAM Bank0 (devices 64Kb) */
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#define LPC17_GPIO_BASE 0x2009c000 /* -0x2009ffff: GPIO */
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#define LPC17_APB_BASE 0x40000000 /* -0x5fffffff: APB Peripherals */
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# define LPC17_APB0_BASE 0x40000000 /* -0x4007ffff: APB0 Peripherals */
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# define LPC17_APB1_BASE 0x40080000 /* -0x400fffff: APB1 Peripherals */
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# define LPC17_AHB_BASE 0x50000000 /* -0x501fffff: DMA Controller, Ethernet, and USB */
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#define LPC17_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see cortexm3/nvic.h) */
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#define LPC17_SCS_BASE 0xe000e000
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#define LPC17_DEBUGMCU_BASE 0xe0042000
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108
arch/arm/src/lpc17xx/lpc17_wdt.h
Executable file
108
arch/arm/src/lpc17xx/lpc17_wdt.h
Executable file
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/************************************************************************************
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* arch/arm/src/lpc17xx/lpc17_wdt.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
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#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "lp17_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register offsets *****************************************************************/
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#define LPC17_WDT_WDMOD_OFFSET 0x0000 /* Watchdog mode register */
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#define LPC17_WDT_WDTC_OFFSET 0x0004 /* Watchdog timer constant register */
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#define LPC17_WDT_WDFEED_OFFSET 0x0008 /* Watchdog feed sequence register */
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#define LPC17_WDT_WDTV_OFFSET 0x000c /* Watchdog timer value register */
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#define LPC17_WDT_WDCLKSEL_OFFSET 0x0010 /* Watchdog clock source selection register */
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/* Register addresses ***************************************************************/
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#define LPC17_WDT_WDMOD (LPC17_WDT_BASE+LPC17_WDT_WDMOD_OFFSET)
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#define LPC17_WDT_WDTC (LPC17_WDT_BASE+LPC17_WDT_WDTC_OFFSET)
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#define LPC17_WDT_WDFEED (LPC17_WDT_BASE+LPC17_WDT_WDFEED_OFFSET)
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#define LPC17_WDT_WDTV (LPC17_WDT_BASE+LPC17_WDT_WDTV_OFFSET)
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#define LPC17_WDT_WDCLKSEL (LPC17_WDT_BASE+LPC17_WDT_WDCLKSEL_OFFSET)
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/* Register bit definitions *********************************************************/
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/* Watchdog mode register */
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#define WDT_WDMOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
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#define WDT_WDMOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
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#define WDT_WDMOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
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#define WDT_WDMOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
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/* Bits 14-31: Reserved */
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/* Watchdog timer constant register (Bits 0-31: Watchdog time-out interval) */
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/* Watchdog feed sequence register */
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#define WDT_WDFEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa followed by 0x55 */
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/* Bits 14-31: Reserved */
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/* Watchdog timer value register (Bits 0-31: Counter timer value) */
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/* Watchdog clock source selection register */
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#define WDT_WDCLKSEL_WDSEL_SHIFT (0) /* Bits 0-1: Clock source for the Watchdog timer */
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#define WDT_WDCLKSEL_WDSEL_MASK (3 << WDT_WDCLKSEL_WDSEL_SHIFT)
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# define WDT_WDCLKSEL_WDSEL_INTRC (0 << WDT_WDCLKSEL_WDSEL_SHIFT) /* Internal RC osc */
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# define WDT_WDCLKSEL_WDSEL_APB (1 << WDT_WDCLKSEL_WDSEL_SHIFT) /* APB peripheral clock (watchdog pclk) */
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# define WDT_WDCLKSEL_WDSEL_RTC (2 << WDT_WDCLKSEL_WDSEL_SHIFT) /* RTC oscillator (rtc_clk) */
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/* Bits 2-30: Reserved */
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#define WDT_WDCLKSEL_WDLOCK (1 << 31) /* Bit 31: Lock WDT register bits if set */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */
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