esp32s3/rtc: Initialize RTC subsystem
RTC subsystem controls not only the RTC itself but functions that use RTC-enabled features like Bluetooth and Wi-Fi. Initialization must be performed during the system start-up.
This commit is contained in:
Tiago Medicci Serrano
Alan Carvalho de Assis
parent
7dafbb05a1
commit
31476bcb34
@ -34,6 +34,9 @@
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#include "esp32s3_clockconfig.h"
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#include "esp32s3_rt_timer.h"
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#include "hardware/esp32s3_bb.h"
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#include "hardware/esp32s3_nrx.h"
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#include "hardware/esp32s3_fe.h"
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#include "hardware/esp32s3_rtccntl.h"
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#include "hardware/esp32s3_rtc_io.h"
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#include "hardware/esp32s3_system.h"
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@ -111,10 +114,6 @@
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#define RCT_FAST_D256_FREQ_APPROX (RTC_FAST_CLK_FREQ_APPROX / 256)
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#define RTC_SLOW_CLK_FREQ_APPROX 32768
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/* Number of fractional bits in values returned by rtc_clk_cal */
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#define RTC_CLK_CAL_FRACT 19
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/* Disable logging from the ROM code. */
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#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
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@ -421,10 +420,30 @@ extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
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static void IRAM_ATTR
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esp32s3_rtc_sleep_pu(struct esp32s3_rtc_sleep_pu_config_s cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG,
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RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG,
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RTC_CNTL_RTC_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG,
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RTC_CNTL_RTC_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
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SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
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SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG,
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SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
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if (cfg.sram_fpu)
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{
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP,
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SYSCON_SRAM_POWER_UP);
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG,
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SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
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}
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else
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{
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@ -1496,6 +1515,14 @@ void IRAM_ATTR esp32s3_rtc_init(void)
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/* set wifi timer */
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REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, 1);
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REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, 1);
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/* set bt timer */
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REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, 1);
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REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, 1);
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/* Reset RTC bias to default value (needed if waking up from deep sleep) */
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REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP,
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@ -2507,13 +2534,6 @@ int up_rtc_settime(const struct timespec *ts)
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int up_rtc_initialize(void)
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{
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#ifndef CONFIG_PM
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/* Initialize RTC controller parameters */
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esp32s3_rtc_init();
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esp32s3_rtc_clk_set();
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#endif
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g_rtc_save = &rtc_saved_data;
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/* If saved data is invalid, clear offset information */
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@ -64,6 +64,10 @@ extern "C"
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#define EXT_OSC_FLAG BIT(3)
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/* Number of fractional bits in values returned by rtc_clk_cal */
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#define RTC_CLK_CAL_FRACT 19
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -298,24 +302,6 @@ void esp32s3_rtc_update_to_xtal(int freq, int div);
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void esp32s3_rtc_bbpll_enable(void);
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/****************************************************************************
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* Name: esp32s3_rtc_bbpll_configure
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*
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* Description:
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* Configure main XTAL frequency values according to pll_freq.
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*
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* Input Parameters:
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* xtal_freq - XTAL frequency values
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* pll_freq - PLL frequency values
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void IRAM_ATTR esp32s3_rtc_bbpll_configure(
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enum esp32s3_rtc_xtal_freq_e xtal_freq, int pll_freq);
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/****************************************************************************
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* Name: esp32s3_rtc_clk_set
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*
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@ -38,6 +38,7 @@
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#include "esp32s3_clockconfig.h"
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#include "esp32s3_region.h"
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#include "esp32s3_periph.h"
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#include "esp32s3_rtc.h"
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#include "esp32s3_spiram.h"
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#include "esp32s3_wdt.h"
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#ifdef CONFIG_BUILD_PROTECTED
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@ -322,6 +323,11 @@ void noreturn_function IRAM_ATTR __esp32s3_start(void)
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esp32s3_wdt_early_deinit();
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/* Initialize RTC controller parameters */
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esp32s3_rtc_init();
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esp32s3_rtc_clk_set();
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/* Set CPU frequency configured in board.h */
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esp32s3_clockconfig();
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60
arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
Normal file
60
arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
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@ -0,0 +1,60 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/hardware/esp32s3_bb.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H
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#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "esp32s3_soc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Some of the baseband control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
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#define BB_FFT_FORCE_PU (BIT(3))
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#define BB_FFT_FORCE_PU_M (BIT(3))
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#define BB_FFT_FORCE_PU_V 1
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#define BB_FFT_FORCE_PU_S 3
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#define BB_FFT_FORCE_PD (BIT(2))
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#define BB_FFT_FORCE_PD_M (BIT(2))
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#define BB_FFT_FORCE_PD_V 1
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#define BB_FFT_FORCE_PD_S 2
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#define BB_DC_EST_FORCE_PU (BIT(1))
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#define BB_DC_EST_FORCE_PU_M (BIT(1))
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#define BB_DC_EST_FORCE_PU_V 1
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#define BB_DC_EST_FORCE_PU_S 1
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#define BB_DC_EST_FORCE_PD (BIT(0))
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#define BB_DC_EST_FORCE_PD_M (BIT(0))
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#define BB_DC_EST_FORCE_PD_V 1
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#define BB_DC_EST_FORCE_PD_S 0
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_BB_H */
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62
arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
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62
arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
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@ -0,0 +1,62 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/hardware/esp32s3_fe.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H
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#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "esp32s3_soc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Some of the RF frontend control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
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#define FE_IQ_EST_FORCE_PU (BIT(5))
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#define FE_IQ_EST_FORCE_PU_M (BIT(5))
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#define FE_IQ_EST_FORCE_PU_V 1
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#define FE_IQ_EST_FORCE_PU_S 5
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#define FE_IQ_EST_FORCE_PD (BIT(4))
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#define FE_IQ_EST_FORCE_PD_M (BIT(4))
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#define FE_IQ_EST_FORCE_PD_V 1
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#define FE_IQ_EST_FORCE_PD_S 4
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#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
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#define FE2_TX_INF_FORCE_PU (BIT(10))
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#define FE2_TX_INF_FORCE_PU_M (BIT(10))
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#define FE2_TX_INF_FORCE_PU_V 1
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#define FE2_TX_INF_FORCE_PU_S 10
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#define FE2_TX_INF_FORCE_PD (BIT(9))
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#define FE2_TX_INF_FORCE_PD_M (BIT(9))
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#define FE2_TX_INF_FORCE_PD_V 1
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#define FE2_TX_INF_FORCE_PD_S 9
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_FE_H */
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80
arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
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80
arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
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@ -0,0 +1,80 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/hardware/esp32s3_nrx.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H
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#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "esp32s3_soc.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Some of the WiFi RX control registers.
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* PU/PD fields defined here are used in sleep related functions.
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*/
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#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
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#define NRX_CHAN_EST_FORCE_PU (BIT(7))
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#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
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#define NRX_CHAN_EST_FORCE_PU_V 1
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#define NRX_CHAN_EST_FORCE_PU_S 7
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#define NRX_CHAN_EST_FORCE_PD (BIT(6))
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#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
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#define NRX_CHAN_EST_FORCE_PD_V 1
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#define NRX_CHAN_EST_FORCE_PD_S 6
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#define NRX_RX_ROT_FORCE_PU (BIT(5))
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#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
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#define NRX_RX_ROT_FORCE_PU_V 1
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#define NRX_RX_ROT_FORCE_PU_S 5
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#define NRX_RX_ROT_FORCE_PD (BIT(4))
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#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
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#define NRX_RX_ROT_FORCE_PD_V 1
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#define NRX_RX_ROT_FORCE_PD_S 4
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#define NRX_VIT_FORCE_PU (BIT(3))
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#define NRX_VIT_FORCE_PU_M (BIT(3))
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#define NRX_VIT_FORCE_PU_V 1
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#define NRX_VIT_FORCE_PU_S 3
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#define NRX_VIT_FORCE_PD (BIT(2))
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#define NRX_VIT_FORCE_PD_M (BIT(2))
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#define NRX_VIT_FORCE_PD_V 1
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#define NRX_VIT_FORCE_PD_S 2
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#define NRX_DEMAP_FORCE_PU (BIT(1))
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#define NRX_DEMAP_FORCE_PU_M (BIT(1))
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#define NRX_DEMAP_FORCE_PU_V 1
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#define NRX_DEMAP_FORCE_PU_S 1
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#define NRX_DEMAP_FORCE_PD (BIT(0))
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#define NRX_DEMAP_FORCE_PD_M (BIT(0))
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#define NRX_DEMAP_FORCE_PD_V 1
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#define NRX_DEMAP_FORCE_PD_S 0
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_NRX_H */
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