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arch/arm/src/sama5/sam_emacb.c: Fix syslog formats

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YAMAMOTO Takashi 2020-12-05 22:06:56 +09:00 committed by Xiang Xiao
parent c3bcf80a18
commit 3152ee6c62
1 changed files with 13 additions and 10 deletions
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23
arch/arm/src/sama5/sam_emacb.c
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@ -65,6 +65,7 @@
# define CONFIG_DEBUG_NET 1 # define CONFIG_DEBUG_NET 1
#endif #endif
#include <inttypes.h>
#include <stdint.h> #include <stdint.h>
#include <stdbool.h> #include <stdbool.h>
#include <time.h> #include <time.h>
@ -1367,7 +1368,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
up_invalidate_dcache((uintptr_t)rxdesc, up_invalidate_dcache((uintptr_t)rxdesc,
(uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s)); (uintptr_t)rxdesc + sizeof(struct emac_rxdesc_s));
ninfo("rxndx: %d\n", rxndx); ninfo("rxndx: %" PRId32 "\n", rxndx);
while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0) while ((rxdesc->addr & EMACRXD_ADDR_OWNER) != 0)
{ {
@ -1478,7 +1479,8 @@ static int sam_recvframe(struct sam_emac_s *priv)
/* Frame size from the EMAC */ /* Frame size from the EMAC */
dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK); dev->d_len = (rxdesc->status & EMACRXD_STA_FRLEN_MASK);
ninfo("packet %d-%d (%d)\n", priv->rxndx, rxndx, dev->d_len); ninfo("packet %d-%" PRId32 " (%d)\n",
priv->rxndx, rxndx, dev->d_len);
/* All data have been copied in the application frame buffer, /* All data have been copied in the application frame buffer,
* release the RX descriptor * release the RX descriptor
@ -1512,7 +1514,7 @@ static int sam_recvframe(struct sam_emac_s *priv)
ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len); ninfo("rxndx: %d d_len: %d\n", priv->rxndx, dev->d_len);
if (pktlen < dev->d_len) if (pktlen < dev->d_len)
{ {
nerr("ERROR: Buffer size %d; frame size %d\n", nerr("ERROR: Buffer size %d; frame size %" PRId32 "\n",
dev->d_len, pktlen); dev->d_len, pktlen);
return -E2BIG; return -E2BIG;
} }
@ -1872,7 +1874,7 @@ static void sam_interrupt_work(FAR void *arg)
imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET); imr = sam_getreg(priv, SAM_EMAC_IMR_OFFSET);
pending = isr & ~(imr | EMAC_INT_UNUSED); pending = isr & ~(imr | EMAC_INT_UNUSED);
ninfo("isr: %08x pending: %08x\n", isr, pending); ninfo("isr: %08" PRIx32 " pending: %08" PRIx32 "\n", isr, pending);
/* Check for the completion of a transmission. This should be done before /* Check for the completion of a transmission. This should be done before
* checking for received data (because receiving can cause another * checking for received data (because receiving can cause another
@ -1898,7 +1900,7 @@ static void sam_interrupt_work(FAR void *arg)
clrbits = EMAC_TSR_RLE | sam_txinuse(priv); clrbits = EMAC_TSR_RLE | sam_txinuse(priv);
sam_txreset(priv); sam_txreset(priv);
nerr("ERROR: Retry Limit Exceeded TSR: %08x\n", tsr); nerr("ERROR: Retry Limit Exceeded TSR: %08" PRIx32 "\n", tsr);
regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET); regval = sam_getreg(priv, SAM_EMAC_NCR_OFFSET);
regval |= EMAC_NCR_TXEN; regval |= EMAC_NCR_TXEN;
@ -1909,7 +1911,7 @@ static void sam_interrupt_work(FAR void *arg)
if ((tsr & EMAC_TSR_COL) != 0) if ((tsr & EMAC_TSR_COL) != 0)
{ {
nerr("ERROR: Collision occurred TSR: %08x\n", tsr); nerr("ERROR: Collision occurred TSR: %08" PRIx32 "\n", tsr);
clrbits |= EMAC_TSR_COL; clrbits |= EMAC_TSR_COL;
} }
@ -1917,7 +1919,8 @@ static void sam_interrupt_work(FAR void *arg)
if ((tsr & EMAC_TSR_TFC) != 0) if ((tsr & EMAC_TSR_TFC) != 0)
{ {
nerr("ERROR: Transmit Frame Corruption due to AHB error: %08x\n", nerr("ERROR: Transmit Frame Corruption "
"due to AHB error: %08" PRIx32 "\n",
tsr); tsr);
clrbits |= EMAC_TSR_TFC; clrbits |= EMAC_TSR_TFC;
} }
@ -1933,7 +1936,7 @@ static void sam_interrupt_work(FAR void *arg)
if ((tsr & EMAC_TSR_UND) != 0) if ((tsr & EMAC_TSR_UND) != 0)
{ {
nerr("ERROR: Transmit Underrun TSR: %08x\n", tsr); nerr("ERROR: Transmit Underrun TSR: %08" PRIx32 "\n", tsr);
clrbits |= EMAC_TSR_UND; clrbits |= EMAC_TSR_UND;
} }
@ -1970,7 +1973,7 @@ static void sam_interrupt_work(FAR void *arg)
if ((rsr & EMAC_RSR_RXOVR) != 0) if ((rsr & EMAC_RSR_RXOVR) != 0)
{ {
nerr("ERROR: Receiver overrun RSR: %08x\n", rsr); nerr("ERROR: Receiver overrun RSR: %08" PRIx32 "\n", rsr);
clrbits |= EMAC_RSR_RXOVR; clrbits |= EMAC_RSR_RXOVR;
} }
@ -1987,7 +1990,7 @@ static void sam_interrupt_work(FAR void *arg)
if ((rsr & EMAC_RSR_BNA) != 0) if ((rsr & EMAC_RSR_BNA) != 0)
{ {
nerr("ERROR: Buffer not available RSR: %08x\n", rsr); nerr("ERROR: Buffer not available RSR: %08" PRIx32 "\n", rsr);
clrbits |= EMAC_RSR_BNA; clrbits |= EMAC_RSR_BNA;
} }