Merge branch 'master' of github.com:apache/incubator-nuttx
This commit is contained in:
Gregory Nutt
commit
316675f4db
@ -166,13 +166,14 @@
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# define STM32H7_NETHERNET 0 /* No 100/100 Ethernet MAC */
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#endif
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|
||||
#if defined(CONFIG_STM32F7_HAVE_FMC)
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# define STM32F7_NFMC 1 /* Have FMC memory controller */
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#if defined(CONFIG_STM32H7_HAVE_FMC)
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# define STM32H7_NFMC 1 /* Have FMC memory controller */
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#else
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# define STM32F7_NFMC 0 /* No FMC memory controller */
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# define STM32H7_NFMC 0 /* No FMC memory controller */
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#endif
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/* NVIC priority levels **************************************************************/
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/* 16 Programmable interrupt levels */
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
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@ -1,7 +1,7 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/stm32/stm32_fmc.c
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*
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* Copyright (C) 20019 Gregory Nutt. All rights reserved.
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Jason T. Harris <sirmanlypowers@gmail.com>
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*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -31,11 +31,11 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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||||
************************************************************************************/
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****************************************************************************/
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||||
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/************************************************************************************
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||||
/****************************************************************************
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||||
* Included Files
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||||
************************************************************************************/
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||||
****************************************************************************/
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#include <nuttx/config.h>
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@ -43,9 +43,9 @@
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#if defined(CONFIG_STM32_FMC)
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/************************************************************************************
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/****************************************************************************
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* Public Functions
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************************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Name: stm32_fmc_sdram_wait
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@ -64,6 +64,7 @@ void stm32_fmc_sdram_wait(void)
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{
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break;
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}
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timeout--;
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}
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@ -106,7 +107,8 @@ void stm32_fmc_disable(void)
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void stm32_fmc_sdram_write_protect(int bank, bool state)
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{
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uint32_t val, sdcr;
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uint32_t val;
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uint32_t sdcr;
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DEBUGASSERT(bank == 1 || bank == 2);
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sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
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@ -158,7 +160,8 @@ void stm32_fmc_sdram_set_refresh_rate(int count)
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void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
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{
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uint32_t val, sdtr;
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uint32_t val
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uint32_t sdtr;
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DEBUGASSERT((bank == 1) || (bank == 2));
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DEBUGASSERT((timing & FMC_SDTR_RESERVED) == 0);
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@ -180,7 +183,8 @@ void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
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void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
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{
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uint32_t val, sdcr;
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uint32_t val
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uint32_t sdcr;
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DEBUGASSERT((bank == 1) || (bank == 2));
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DEBUGASSERT((ctrl & FMC_SDCR_RESERVED) == 0);
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@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/src/stm32/stm32_fmc.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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@ -31,23 +31,23 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32_STM32_FMC_H
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#define __ARCH_ARM_STC_STM32_STM32_FMC_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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||||
************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "hardware/stm32_fmc.h"
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/************************************************************************************
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/****************************************************************************
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* Public Functions
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************************************************************************************/
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****************************************************************************/
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#ifndef __ASSEMBLY__
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@ -41,6 +41,7 @@ config STM32H7_STM32H7X3XX
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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select STM32H7_HAVE_ETHERNET
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select STM32H7_HAVE_FMC
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select STM32H7_HAVE_SPI4
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select STM32H7_HAVE_SPI5
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select STM32H7_HAVE_SPI6
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@ -58,6 +59,7 @@ config STM32H7_STM32H7X7XX
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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select STM32H7_HAVE_ETHERNET
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select STM32H7_HAVE_FMC
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select STM32H7_HAVE_SPI4
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select STM32H7_HAVE_SPI5
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select STM32H7_HAVE_SPI6
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@ -148,6 +150,10 @@ config STM32H7_HAVE_ETHERNET
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bool
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default n
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config STM32H7_HAVE_FMC
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bool
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default n
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config STM32H7_HAVE_SPI4
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bool
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default n
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@ -274,6 +280,11 @@ config STM32H7_ETHMAC
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select NETDEVICES
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select ARCH_HAVE_PHY
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config STM32H7_FMC
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bool "FMC"
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default n
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depends on STM32H7_HAVE_FMC
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config STM32H7_OTGFS
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bool "OTG FS"
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default n
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@ -1143,6 +1154,14 @@ config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
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endif # STM32H7_RTC_LSECLOCK
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config STM32H7_EXTERNAL_RAM
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bool "External RAM on FMC"
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default n
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depends on STM32H7_FMC
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select ARCH_HAVE_HEAP2
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---help---
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In addition to internal SDRAM, external RAM may be available through the FMC.
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endmenu # RTC Configuration
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config STM32H7_CUSTOM_CLOCKCONFIG
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@ -141,6 +141,10 @@ ifeq ($(CONFIG_STM32H7_DMA),y)
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CHIP_CSRCS += stm32_dma.c
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endif
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ifeq ($(CONFIG_STM32H7_FMC),y)
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CHIP_CSRCS += stm32_fmc.c
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endif
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ifeq ($(filter y,$(CONFIG_STM32H7_IWDG) $(CONFIG_STM32H7_RTC_LSICLOCK)),y)
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CHIP_CSRCS += stm32_lsi.c
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endif
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390
arch/arm/src/stm32h7/hardware/stm32_fmc.h
Normal file
390
arch/arm/src/stm32h7/hardware/stm32_fmc.h
Normal file
@ -0,0 +1,390 @@
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/************************************************************************************
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* arch/arm/src/stm32h7/hardware/stm32_fmc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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||||
************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H
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#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H
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/************************************************************************************
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* Included Files
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||||
************************************************************************************/
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||||
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_FMC_BCR_OFFSET(n) (8*((n)-1))
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#define STM32_FMC_BCR1_OFFSET 0x0000 /* SRAM/NOR-Flash chip-select control registers 1 */
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#define STM32_FMC_BCR2_OFFSET 0x0008 /* SRAM/NOR-Flash chip-select control registers 2 */
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#define STM32_FMC_BCR3_OFFSET 0x0010 /* SRAM/NOR-Flash chip-select control registers 3 */
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#define STM32_FMC_BCR4_OFFSET 0x0018 /* SRAM/NOR-Flash chip-select control registers 4 */
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#define STM32_FMC_BTR_OFFSET(n) (8*((n)-1)+0x0004)
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#define STM32_FMC_BTR1_OFFSET 0x0004 /* SRAM/NOR-Flash chip-select timing registers 1 */
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#define STM32_FMC_BTR2_OFFSET 0x000c /* SRAM/NOR-Flash chip-select timing registers 2 */
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#define STM32_FMC_BTR3_OFFSET 0x0014 /* SRAM/NOR-Flash chip-select timing registers 3 */
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#define STM32_FMC_BTR4_OFFSET 0x001c /* SRAM/NOR-Flash chip-select timing registers 4 */
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#define STM32_FMC_BWTR_OFFSET(n) (8*((n)-1)+0x0104)
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#define STM32_FMC_BWTR1_OFFSET 0x0104 /* SRAM/NOR-Flash write timing registers 1 */
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#define STM32_FMC_BWTR2_OFFSET 0x010c /* SRAM/NOR-Flash write timing registers 2 */
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#define STM32_FMC_BWTR3_OFFSET 0x0114 /* SRAM/NOR-Flash write timing registers 3 */
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#define STM32_FMC_BWTR4_OFFSET 0x011c /* SRAM/NOR-Flash write timing registers 4 */
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#define STM32_FMC_PCR_OFFSET(n) (0x0020*((n)-1)+0x0040)
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#define STM32_FMC_PCR2_OFFSET 0x0060 /* NAND Flash/PC Card controller register 2 */
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#define STM32_FMC_PCR3_OFFSET 0x0080 /* NAND Flash/PC Card controller register 3 */
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#define STM32_FMC_PCR4_OFFSET 0x00a0 /* NAND Flash/PC Card controller register 4 */
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#define STM32_FMC_SR_OFFSET(n) (0x0020*((n)-1)+0x0044)
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#define STM32_FMC_SR2_OFFSET 0x0064 /* NAND Flash/PC Card controller register 2 */
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#define STM32_FMC_SR3_OFFSET 0x0084 /* NAND Flash/PC Card controller register 3 */
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#define STM32_FMC_SR4_OFFSET 0x00a4 /* NAND Flash/PC Card controller register 4 */
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#define STM32_FMC_PMEM_OFFSET(n) (0x0020*((n)-1)+0x0048)
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#define STM32_FMC_PMEM2_OFFSET 0x0068 /* Common memory space timing register 2 */
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#define STM32_FMC_PMEM3_OFFSET 0x0088 /* Common memory space timing register 3 */
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#define STM32_FMC_PMEM4_OFFSET 0x00a8 /* Common memory space timing register 4 */
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#define STM32_FMC_PATT_OFFSET(n) (0x0020*((n)-1)+0x004c)
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#define STM32_FMC_PATT2_OFFSET 0x006c /* Attribute memory space timing register 2 */
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#define STM32_FMC_PATT3_OFFSET 0x008c /* Attribute memory space timing register 3 */
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#define STM32_FMC_PATT4_OFFSET 0x00ac /* Attribute memory space timing register 4 */
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#define STM32_PIO4_OFFSET 0x00b0 /* I/O space timing register 4 */
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#define STM32_FMC_ECCR_OFFSET(n) (0x0020*((n)-1)+0x003c)
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#define STM32_FMC_ECCR2_OFFSET 0x0054 /* ECC result register 2 */
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#define STM32_FMC_ECCR3_OFFSET 0x0074 /* ECC result register 3 */
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#define STM32_FMC_SDCR1_OFFSET 0x0140 /* SDRAM Control Register, Bank 0 */
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#define STM32_FMC_SDCR2_OFFSET 0x0144 /* SDRAM Control Register, Bank 1 */
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#define STM32_FMC_SDTR1_OFFSET 0x0148 /* SDRAM Timing Register, Bank 0 */
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#define STM32_FMC_SDTR2_OFFSET 0x014c /* SDRAM Timing Register, Bank 1 */
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#define STM32_FMC_SDCMR_OFFSET 0x0150 /* SDRAM Config Memory register */
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#define STM32_FMC_SDRTR_OFFSET 0x0154 /* SDRAM Refresh Timing Register maybe */
|
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#define STM32_FMC_SDSR_OFFSET 0x0158 /* SDRAM Status Register */
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||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_FMC_BCR(n) (STM32_FMC_BASE+STM32_FMC_BCR_OFFSET(n))
|
||||
#define STM32_FMC_BCR1 (STM32_FMC_BASE+STM32_FMC_BCR1_OFFSET )
|
||||
#define STM32_FMC_BCR2 (STM32_FMC_BASE+STM32_FMC_BCR2_OFFSET )
|
||||
#define STM32_FMC_BCR3 (STM32_FMC_BASE+STM32_FMC_BCR3_OFFSET )
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#define STM32_FMC_BCR4 (STM32_FMC_BASE+STM32_FMC_BCR4_OFFSET )
|
||||
|
||||
#define STM32_FMC_BTR(n) (STM32_FMC_BASE+STM32_FMC_BTR_OFFSET(n))
|
||||
#define STM32_FMC_BTR1 (STM32_FMC_BASE+STM32_FMC_BTR1_OFFSET )
|
||||
#define STM32_FMC_BTR2 (STM32_FMC_BASE+STM32_FMC_BTR2_OFFSET )
|
||||
#define STM32_FMC_BTR3 (STM32_FMC_BASE+STM32_FMC_BTR3_OFFSET )
|
||||
#define STM32_FMC_BTR4 (STM32_FMC_BASE+STM32_FMC_BTR4_OFFSET )
|
||||
|
||||
#define STM32_FMC_BWTR(n) (STM32_FMC_BASE+STM32_FMC_BWTR_OFFSET(n))
|
||||
#define STM32_FMC_BWTR1 (STM32_FMC_BASE+STM32_FMC_BWTR1_OFFSET )
|
||||
#define STM32_FMC_BWTR2 (STM32_FMC_BASE+STM32_FMC_BWTR2_OFFSET )
|
||||
#define STM32_FMC_BWTR3 (STM32_FMC_BASE+STM32_FMC_BWTR3_OFFSET )
|
||||
#define STM32_FMC_BWTR4 (STM32_FMC_BASE+STM32_FMC_BWTR4_OFFSET )
|
||||
|
||||
#define STM32_FMC_PCR(n) (STM32_FMC_BASE+STM32_FMC_PCR_OFFSET(n))
|
||||
#define STM32_FMC_PCR2 (STM32_FMC_BASE+STM32_FMC_PCR2_OFFSET )
|
||||
#define STM32_FMC_PCR3 (STM32_FMC_BASE+STM32_FMC_PCR3_OFFSET )
|
||||
#define STM32_FMC_PCR4 (STM32_FMC_BASE+STM32_FMC_PCR4_OFFSET )
|
||||
|
||||
#define STM32_FMC_SR(n) (STM32_FMC_BASE+STM32_FMC_SR_OFFSET(n))
|
||||
#define STM32_FMC_SR2 (STM32_FMC_BASE+STM32_FMC_SR2_OFFSET )
|
||||
#define STM32_FMC_SR3 (STM32_FMC_BASE+STM32_FMC_SR3_OFFSET )
|
||||
#define STM32_FMC_SR4 (STM32_FMC_BASE+STM32_FMC_SR4_OFFSET )
|
||||
|
||||
#define STM32_FMC_PMEM(n) (STM32_FMC_BASE+STM32_FMC_PMEM_OFFSET(n))
|
||||
#define STM32_FMC_PMEM2 (STM32_FMC_BASE+STM32_FMC_PMEM2_OFFSET )
|
||||
#define STM32_FMC_PMEM3 (STM32_FMC_BASE+STM32_FMC_PMEM3_OFFSET )
|
||||
#define STM32_FMC_PMEM4 (STM32_FMC_BASE+STM32_FMC_PMEM4_OFFSET )
|
||||
|
||||
#define STM32_FMC_PATT(n) (STM32_FMC_BASE+STM32_FMC_PATT_OFFSET(n))
|
||||
#define STM32_FMC_PATT2 (STM32_FMC_BASE+STM32_FMC_PATT2_OFFSET )
|
||||
#define STM32_FMC_PATT3 (STM32_FMC_BASE+STM32_FMC_PATT3_OFFSET )
|
||||
#define STM32_FMC_PATT4 (STM32_FMC_BASE+STM32_FMC_PATT4_OFFSET )
|
||||
|
||||
#define STM32_PIO4 (STM32_FMC_BASE+STM32_FMC_PIO4_OFFSET )
|
||||
|
||||
#define STM32_FMC_ECCR(n) (STM32_FMC_BASE+STM32_FMC_ECCR_OFFSET(n))
|
||||
#define STM32_FMC_ECCR2 (STM32_FMC_BASE+STM32_FMC_ECCR2_OFFSET )
|
||||
#define STM32_FMC_ECCR3 (STM32_FMC_BASE+STM32_FMC_ECCR3_OFFSET )
|
||||
|
||||
#define STM32_FMC_SDCR1 (STM32_FMC_BASE+STM32_FMC_SDCR1_OFFSET)
|
||||
#define STM32_FMC_SDCR2 (STM32_FMC_BASE+STM32_FMC_SDCR2_OFFSET)
|
||||
|
||||
#define STM32_FMC_SDTR1 (STM32_FMC_BASE+STM32_FMC_SDTR1_OFFSET)
|
||||
#define STM32_FMC_SDTR2 (STM32_FMC_BASE+STM32_FMC_SDTR2_OFFSET)
|
||||
|
||||
#define STM32_FMC_SDCMR (STM32_FMC_BASE+STM32_FMC_SDCMR_OFFSET)
|
||||
#define STM32_FMC_SDRTR (STM32_FMC_BASE+STM32_FMC_SDRTR_OFFSET)
|
||||
#define STM32_FMC_SDSR (STM32_FMC_BASE+STM32_FMC_SDSR_OFFSET)
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
|
||||
#define FMC_BCR_MBKEN (1 << 0) /* Memory bank enable bit */
|
||||
#define FMC_BCR_MUXEN (1 << 1) /* Address/data multiplexing enable bit */
|
||||
#define FMC_BCR_MTYP_SHIFT (2) /* Memory type */
|
||||
#define FMC_BCR_MTYP_MASK (3 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_SRAM (0 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_ROM (0 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_PSRAM (1 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_CRAM (1 << FMC_BCR_MTYP_SHIFT)
|
||||
# define FMC_BCR_NOR (2 << FMC_BCR_MTYP_SHIFT)
|
||||
#define FMC_BCR_MWID_SHIFT (4) /* Memory data bus width */
|
||||
#define FMC_BCR_MWID_MASK (3 << FMC_BCR_MWID_SHIFT)
|
||||
# define FMC_BCR_MWID8 (0 << FMC_BCR_MWID_SHIFT)
|
||||
# define FMC_BCR_MWID16 (1 << FMC_BCR_MWID_SHIFT)
|
||||
#define FMC_BCR_FACCEN (1 << 6) /* Flash access enable */
|
||||
#define FMC_BCR_BURSTEN (1 << 8) /* Burst enable bit */
|
||||
#define FMC_BCR_WAITPOL (1 << 9) /* Wait signal polarity bit */
|
||||
#define FMC_BCR_WRAPMOD (1 << 10) /* Wrapped burst mode support */
|
||||
#define FMC_BCR_WAITCFG (1 << 11) /* Wait timing configuration */
|
||||
#define FMC_BCR_WREN (1 << 12) /* Write enable bit */
|
||||
#define FMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
|
||||
#define FMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
|
||||
#define FMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
|
||||
#define FMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
|
||||
#define FMC_BCR_BMAP_SHIFT (24)
|
||||
# define FMC_BCR_BMAP_0 (0 << FMC_BCR_BMAP_SHIFT)
|
||||
# define FMC_BCR_BMAP_1 (1 << FMC_BCR_BMAP_SHIFT)
|
||||
# define FMC_BCR_BMAP_2 (2 << FMC_BCR_BMAP_SHIFT)
|
||||
|
||||
#define FMC_BCR_FMCEN (1 << 31) /* Write burst enable */
|
||||
|
||||
#define FMC_BCR_RSTVALUE 0x000003d2
|
||||
|
||||
#define FMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
#define FMC_BTR_ADDSET_MASK (15 << FMC_BTR_ADDSET_SHIFT)
|
||||
# define FMC_BTR_ADDSET(n) ((n-1) << FMC_BTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
|
||||
#define FMC_BTR_ADDHLD_MASK (15 << FMC_BTR_ADDHLD_SHIFT)
|
||||
# define FMC_BTR_ADDHLD(n) ((n-1) << FMC_BTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
|
||||
#define FMC_BTR_DATAST_SHIFT (8) /* Data-phase duration */
|
||||
#define FMC_BTR_DATAST_MASK (255 << FMC_BTR_DATAST_SHIFT)
|
||||
# define FMC_BTR_DATAST(n) ((n-1) << FMC_BTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_BTR_BUSTURN_SHIFT (16) /* Bus turnaround phase duration */
|
||||
#define FMC_BTR_BUSTURN_MASK (15 << FMC_BTR1_BUSTURN_SHIFT)
|
||||
# define FMC_BTR_BUSTURN(n) ((n-1) << FMC_BTR_BUSTURN_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
|
||||
#define FMC_BTR_CLKDIV_MASK (15 << FMC_BTR_CLKDIV_SHIFT)
|
||||
# define FMC_BTR_CLKDIV(n) ((n-1) << FMC_BTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
|
||||
#define FMC_BTR_DATLAT_SHIFT (24) /* Data latency */
|
||||
#define FMC_BTR_DATLAT_MASK (15 << FMC_BTR_DATLAT_SHIFT)
|
||||
# define FMC_BTR_DATLAT(n) ((n-2) << FMC_BTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
|
||||
#define FMC_BTR_ACCMOD_SHIFT (28) /* Access mode */
|
||||
#define FMC_BTR_ACCMOD_MASK (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODA (0 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODB (1 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODC (2 << FMC_BTR_ACCMOD_SHIFT)
|
||||
# define FMC_BTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
|
||||
#define FMC_BTR_RSTVALUE 0xffffffff
|
||||
|
||||
#define FMC_BWTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
#define FMC_BWTR_ADDSET_MASK (15 << FMC_BWTR_ADDSET_SHIFT)
|
||||
# define FMC_BWTR_ADDSET(n) ((n-1) << FMC_BWTR_ADDSET_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_BWTR_ADDHLD_SHIFT (4) /* Address-hold phase duration */
|
||||
#define FMC_BWTR_ADDHLD_MASK (15 << FMC_BWTR_ADDHLD_SHIFT)
|
||||
# define FMC_BWTR_ADDHLD(n) ((n-1) << FMC_BWTR_ADDHLD_SHIFT) /* (n)xHCLK n=2..16*/
|
||||
#define FMC_BWTR_DATAST_SHIFT (8) /* Data-phase duration */
|
||||
#define FMC_BWTR_DATAST_MASK (255 << FMC_BWTR_DATAST_SHIFT)
|
||||
# define FMC_BWTR_DATAST(n) ((n-1) << FMC_BWTR_DATAST_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_BWTR_CLKDIV_SHIFT (20) /* Clock divide ratio */
|
||||
#define FMC_BWTR_CLKDIV_MASK (15 << FMC_BWTR_CLKDIV_SHIFT)
|
||||
# define FMC_BWTR_CLKDIV(n) ((n-1) << FMC_BWTR_CLKDIV_SHIFT) /* (n)xHCLK n=2..16 */
|
||||
#define FMC_BWTR_DATLAT_SHIFT (24) /* Data latency */
|
||||
#define FMC_BWTR_DATLAT_MASK (15 << FMC_BWTR_DATLAT_SHIFT)
|
||||
# define FMC_BWTR_DATLAT(n) ((n-2) << FMC_BWTR_DATLAT_SHIFT) /* (n)xHCLK n=2..17 */
|
||||
#define FMC_BWTR_ACCMOD_SHIFT (28) /* Access mode */
|
||||
#define FMC_BWTR_ACCMOD_MASK (3 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODA (0 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODB (1 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODC (2 << FMC_BWTR_ACCMOD_SHIFT)
|
||||
# define FMC_BWTR_ACCMODD (3 << FMC_BTR_ACCMOD_SHIFT)
|
||||
|
||||
#define FMC_PCR_PWAITEN (1 << 1) /* Wait feature enable bit */
|
||||
#define FMC_PCR_PBKEN (1 << 2) /* PC Card/NAND Flash memory bank enable bit */
|
||||
#define FMC_PCR_PTYP (1 << 3) /* Memory type */
|
||||
#define FMC_PCR_PWID_SHIFT (4) /* NAND Flash databus width */
|
||||
#define FMC_PCR_PWID_MASK (3 << FMC_PCR_PWID_SHIFT)
|
||||
# define FMC_PCR_PWID8 (0 << FMC_PCR_PWID_SHIFT)
|
||||
# define FMC_PCR_PWID16 (1 << FMC_PCR_PWID_SHIFT)
|
||||
#define FMC_PCR_ECCEN (1 << 6) /* ECC computation logic enable bit */
|
||||
#define FMC_PCR_TCLR_SHIFT (9) /* CLE to RE delay */
|
||||
#define FMC_PCR_TCLR_MASK (15 << FMC_PCR_TCLR_SHIFT)
|
||||
# define FMC_PCR_TCLR(n) ((n-1) << FMC_PCR_TCLR_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_PCR_TAR_SHIFT (13) /* ALE to RE delay */
|
||||
#define FMC_PCR_TAR_MASK (15 << FMC_PCR_TAR_MASK)
|
||||
# define FMC_PCR_TAR(n) ((n-1) << FMC_PCR_TAR_SHIFT) /* (n)xHCLK n=1..16 */
|
||||
#define FMC_PCR_ECCPS_SHIFT (17) /* ECC page size */
|
||||
#define FMC_PCR_ECCPS_MASK (7 << FMC_PCR_ECCPS_SHIFT)
|
||||
# define FMC_PCR_ECCPS256 (0 << FMC_PCR_ECCPS_SHIFT) /* 256 bytes */
|
||||
# define FMC_PCR_ECCPS512 (1 << FMC_PCR_ECCPS_SHIFT) /* 512 bytes */
|
||||
# define FMC_PCR_ECCPS1024 (2 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
|
||||
# define FMC_PCR_ECCPS2048 (3 << FMC_PCR_ECCPS_SHIFT) /* 2048 bytes */
|
||||
# define FMC_PCR_ECCPS4096 (4 << FMC_PCR_ECCPS_SHIFT) /* 8192 bytes */
|
||||
# define FMC_PCR_ECCPS8192 (5 << FMC_PCR_ECCPS_SHIFT) /* 1024 bytes */
|
||||
|
||||
#define FMC_SR_IRS (1 << 0) /* Interrupt Rising Edge status */
|
||||
#define FMC_SR_ILS (1 << 1) /* Interrupt Level status */
|
||||
#define FMC_SR_IFS (1 << 2) /* Interrupt Falling Edge status */
|
||||
#define FMC_SR_IREN (1 << 3) /* Interrupt Rising Edge detection Enable bit */
|
||||
#define FMC_SR_ILEN (1 << 4) /* Interrupt Level detection Enable bit */
|
||||
#define FMC_SR_IFEN (1 << 5) /* Interrupt Falling Edge detection Enable bit */
|
||||
#define FMC_SR_FEMPT (1 << 6) /* FIFO empty */
|
||||
|
||||
#define FMC_PMEM_MEMSET_SHIFT (0) /* Common memory setup time */
|
||||
#define FMC_PMEM_MEMSET_MASK (255 << FMC_PMEM_MEMSET_SHIFT)
|
||||
# define FMC_PMEM_MEMSET(n) ((n-1) << FMC_PMEM_MEMSET_SHIFT) /* (n)xHCLK n=1..256 */
|
||||
#define FMC_PMEM_MEMWAIT_SHIFT (8) /* Common memory wait time */
|
||||
#define FMC_PMEM_MEMWAIT_MASK (255 << FMC_PMEM_MEMWAIT_SHIFT)
|
||||
# define FMC_PMEM_MEMWAIT(n) ((n-1) << FMC_PMEM_MEMWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PMEM_MEMHOLD_SHIFT (16) /* Common memoryhold time */
|
||||
#define FMC_PMEM_MEMHOLD_MASK (255 << FMC_PMEM_MEMHOLD_SHIFT)
|
||||
# define FMC_PMEM_MEMHOLD(n) ((n) << FMC_PMEM_MEMHOLD_SHIFT) /* (n)xHCLK n=1..255 */
|
||||
#define FMC_PMEM_MEMHIZ_SHIFT (24) /* Common memory databus HiZ time */
|
||||
#define FMC_PMEM_MEMHIZ_MASK (255 << FMC_PMEM_MEMHIZ_SHIFT)
|
||||
# define FMC_PMEM_MEMHIZ(n) ((n) << FMC_PMEM_MEMHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
|
||||
#define FMC_PATT_ATTSET_SHIFT (0) /* Attribute memory setup time */
|
||||
#define FMC_PATT_ATTSET_MASK (255 << FMC_PATT_ATTSET_SHIFT)
|
||||
# define FMC_PATT_ATTSET(n) ((n-1) << FMC_PATT_ATTSET_SHIFT) /* (n)xHCLK n=1..256 */
|
||||
#define FMC_PATT_ATTWAIT_SHIFT (8) /* Attribute memory wait time */
|
||||
#define FMC_PATT_ATTWAIT_MASK (255 << FMC_PATT_ATTWAIT_SHIFT)
|
||||
# define FMC_PATT_ATTWAIT(n) ((n-1) << FMC_PATT_ATTWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PATT_ATTHOLD_SHIFT (16) /* Attribute memory hold time */
|
||||
#define FMC_PATT_ATTHOLD_MASK (255 << FMC_PATT_ATTHOLD_SHIFT)
|
||||
# define FMC_PATT_ATTHOLD(n) ((n) << FMC_PATT_ATTHOLD_SHIFT) /* (n)xHCLK n=1..255 */
|
||||
#define FMC_PATT_ATTHIZ_SHIFT (24) /* Attribute memory databus HiZ time */
|
||||
#define FMC_PATT_ATTHIZ_MASK (255 << FMC_PATT_ATTHIZ_SHIFT)
|
||||
# define FMC_PATT_ATTHIZ(n) ((n) << FMC_PATT_ATTHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
|
||||
#define FMC_PIO4_IOSET_SHIFT (0) /* IOribute memory setup time */
|
||||
#define FMC_PIO4_IOSET_MASK (255 << FMC_PIO4_IOSET_SHIFT)
|
||||
# define FMC_PIO4_IOSET(n) ((n-1) << FMC_PIO4_IOSET_SHIFT) /* (n)xHCLK n=1..256 */
|
||||
#define FMC_PIO4_IOWAIT_SHIFT (8) /* IOribute memory wait time */
|
||||
#define FMC_PIO4_IOWAIT_MASK (255 << FMC_PIO4_IOWAIT_SHIFT)
|
||||
# define FMC_PIO4_IOWAIT(n) ((n-1) << FMC_PIO4_IOWAIT_SHIFT) /* (n)xHCLK n=2..256 */
|
||||
#define FMC_PIO4_IOHOLD_SHIFT (16) /* IOribute memory hold time */
|
||||
#define FMC_PIO4_IOHOLD_MASK (255 << FMC_PIO4_IOHOLD_SHIFT)
|
||||
# define FMC_PIO4_IOHOLD(n) ((n) << FMC_PIO4_IOHOLD_SHIFT) /* (n)xHCLK n=1..255 */
|
||||
#define FMC_PIO4_IOHIZ_SHIFT (24) /* IOribute memory databus HiZ time */
|
||||
#define FMC_PIO4_IOHIZ_MASK (255 << FMC_PIO4_IOHIZ_SHIFT)
|
||||
# define FMC_PIO4_IOHIZ(n) ((n) << FMC_PIO4_IOHIZ_SHIFT) /* (n)xHCLK n=0..255 */
|
||||
|
||||
#define FMC_SDCMR_RESERVED (0x3ff << 22) /* reserved bits */
|
||||
#define FMC_SDCMR_CMD_LOAD_MODE (4 << 0)
|
||||
|
||||
# define FMC_SDRAM_CR_COLBITS_8 0x00000000
|
||||
# define FMC_SDRAM_CR_COLBITS_9 0x00000001
|
||||
# define FMC_SDRAM_CR_COLBITS_10 0x00000002
|
||||
# define FMC_SDRAM_CR_COLBITS_11 0x00000003
|
||||
|
||||
# define FMC_SDRAM_CR_ROWBITS_11 0x00000000
|
||||
# define FMC_SDRAM_CR_ROWBITS_12 0x00000004
|
||||
# define FMC_SDRAM_CR_ROWBITS_13 0x00000008
|
||||
|
||||
# define FMC_SDRAM_CR_WIDTH_8 0x00000000
|
||||
# define FMC_SDRAM_CR_WIDTH_16 0x00000010
|
||||
# define FMC_SDRAM_CR_WIDTH_32 0x00000020
|
||||
|
||||
# define FMC_SDRAM_CR_BANKS_2 0x00000000
|
||||
# define FMC_SDRAM_CR_BANKS_4 0x00000040
|
||||
|
||||
# define FMC_SDRAM_CR_CASLAT_1 0x00000080
|
||||
# define FMC_SDRAM_CR_CASLAT_2 0x00000100
|
||||
# define FMC_SDRAM_CR_CASLAT_3 0x00000180
|
||||
|
||||
# define FMC_SDRAM_CR_WRITE_PROTECT 0x00000200
|
||||
|
||||
# define FMC_SDRAM_CR_SDCLK_DISABLE 0x00000000
|
||||
# define FMC_SDRAM_CR_SDCLK_2X 0x00000800
|
||||
# define FMC_SDRAM_CR_SDCLK_3X 0x00000C00
|
||||
|
||||
# define FMC_SDRAM_CR_BURST_READ 0x00001000
|
||||
|
||||
# define FMC_SDRAM_CR_RPIPE_0 0x00000000
|
||||
# define FMC_SDRAM_CR_RPIPE_1 0x00002000
|
||||
# define FMC_SDRAM_CR_RPIPE_2 0x00004000
|
||||
|
||||
# define FMC_SDRAM_CR_RESERVED (0x1FFFF << 15) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_TR_TMRD_SHIFT 0
|
||||
# define FMC_SDRAM_TR_TXSR_SHIFT 4
|
||||
# define FMC_SDRAM_TR_TRAS_SHIFT 8
|
||||
# define FMC_SDRAM_TR_TRC_SHIFT 12
|
||||
# define FMC_SDRAM_TR_TWR_SHIFT 16
|
||||
# define FMC_SDRAM_TR_TRP_SHIFT 20
|
||||
# define FMC_SDRAM_TR_TRCD_SHIFT 24
|
||||
|
||||
# define FMC_SDRAM_TR_RESERVED (0xF << 28) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_MODE_CMD_NORMAL 0
|
||||
# define FMC_SDRAM_MODE_CMD_CLK_ENABLE 1
|
||||
# define FMC_SDRAM_MODE_CMD_PALL 2
|
||||
# define FMC_SDRAM_MODE_CMD_AUTO_REFRESH 3
|
||||
# define FMC_SDRAM_MODE_CMD_LOAD_MODE 4
|
||||
# define FMC_SDRAM_MODE_CMD_SELF_REFRESH 5
|
||||
# define FMC_SDRAM_MODE_CMD_POWER_DOWN 6
|
||||
|
||||
# define FMC_SDRAM_CMD_BANK_1 0x00000010
|
||||
# define FMC_SDRAM_CMD_BANK_2 0x00000008
|
||||
# define FMC_SDRAM_CMD_RESERVED (0x200 << 23) /* reserved bits */
|
||||
|
||||
# define FMC_SDRAM_AUTO_REFRESH_SHIFT 5
|
||||
# define FMC_SDRAM_MODEREG_SHIFT 9
|
||||
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_1 (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_2 (0x0001 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_4 (0x0002 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_LENGTH_8 (0x0004 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_CAS_LATENCY_2 (0x0020 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_CAS_LATENCY_3 (0x0030 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
# define FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200 << FMC_SDRAM_MODEREG_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_FMC_H */
|
||||
@ -319,118 +319,118 @@
|
||||
|
||||
/* Flexible memory controller (FMC) */
|
||||
|
||||
#define GPIO_FMC_A0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_FMC_A1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_FMC_A2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_FMC_A3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_FMC_A4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_FMC_A5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_FMC_A6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_FMC_A7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_FMC_A8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_FMC_A9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_FMC_A10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_FMC_A11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
|
||||
#define GPIO_FMC_A12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_FMC_A13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_FMC_A14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FMC_A15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FMC_A16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_FMC_A17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_FMC_A18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_FMC_A19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_FMC_A20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_FMC_A21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_FMC_A22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_FMC_A23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_FMC_A24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_FMC_A25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_FMC_BA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FMC_BA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FMC_CLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_FMC_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FMC_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FMC_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FMC_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FMC_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FMC_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FMC_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FMC_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FMC_D8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FMC_D9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FMC_D10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FMC_D11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FMC_D12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FMC_D13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FMC_D14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FMC_D15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FMC_D16 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_FMC_D17 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_FMC_D18 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_FMC_D19 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_FMC_D20 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_FMC_D21 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
|
||||
#define GPIO_FMC_D22 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_FMC_D23 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_FMC_D24 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_FMC_D25 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_FMC_D26 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_FMC_D27 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_FMC_D28 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_FMC_D29 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_FMC_D30 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
|
||||
#define GPIO_FMC_D31 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
|
||||
#define GPIO_FMC_DA0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FMC_DA1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FMC_DA2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FMC_DA3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FMC_DA4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FMC_DA5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FMC_DA6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FMC_DA7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FMC_DA8 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FMC_DA9 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FMC_DA10 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FMC_DA11 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FMC_DA12 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FMC_DA13 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FMC_DA14 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FMC_DA15 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FMC_INT (GPIO_ALT|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_FMC_NBL2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_FMC_NBL3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_FMC_NCE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FMC_NCE_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_FMC_NE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FMC_NE1_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_FMC_NE2_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FMC_NE2_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_FMC_NE3_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FMC_NE3_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_FMC_NL (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_FMC_NOE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_FMC_NWAIT_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_FMC_NWAIT_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_FMC_NWE (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_FMC_SDCKE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_FMC_SDCKE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_FMC_SDCKE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_FMC_SDNE0_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_FMC_SDNE1_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_FMC_SDNE1_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_FMC_SDNWE_3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
#define GPIO_FMC_A0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN0)
|
||||
#define GPIO_FMC_A1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN1)
|
||||
#define GPIO_FMC_A2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN2)
|
||||
#define GPIO_FMC_A3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN3)
|
||||
#define GPIO_FMC_A4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN4)
|
||||
#define GPIO_FMC_A5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN5)
|
||||
#define GPIO_FMC_A6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN12)
|
||||
#define GPIO_FMC_A7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN13)
|
||||
#define GPIO_FMC_A8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN14)
|
||||
#define GPIO_FMC_A9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN15)
|
||||
#define GPIO_FMC_A10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_FMC_A11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN1)
|
||||
#define GPIO_FMC_A12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN2)
|
||||
#define GPIO_FMC_A13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN3)
|
||||
#define GPIO_FMC_A14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FMC_A15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FMC_A16 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN11)
|
||||
#define GPIO_FMC_A17 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN12)
|
||||
#define GPIO_FMC_A18 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN13)
|
||||
#define GPIO_FMC_A19 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN3)
|
||||
#define GPIO_FMC_A20 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN4)
|
||||
#define GPIO_FMC_A21 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN5)
|
||||
#define GPIO_FMC_A22 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN6)
|
||||
#define GPIO_FMC_A23 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN2)
|
||||
#define GPIO_FMC_A24 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN13)
|
||||
#define GPIO_FMC_A25 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN14)
|
||||
#define GPIO_FMC_BA0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN4)
|
||||
#define GPIO_FMC_BA1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_FMC_CLK (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN3)
|
||||
#define GPIO_FMC_D0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FMC_D1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FMC_D2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FMC_D3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FMC_D4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FMC_D5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FMC_D6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FMC_D7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FMC_D8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FMC_D9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FMC_D10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FMC_D11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FMC_D12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FMC_D13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FMC_D14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FMC_D15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FMC_D16 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN8)
|
||||
#define GPIO_FMC_D17 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN9)
|
||||
#define GPIO_FMC_D18 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN10)
|
||||
#define GPIO_FMC_D19 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN11)
|
||||
#define GPIO_FMC_D20 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN12)
|
||||
#define GPIO_FMC_D21 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN13)
|
||||
#define GPIO_FMC_D22 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_FMC_D23 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN15)
|
||||
#define GPIO_FMC_D24 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN0)
|
||||
#define GPIO_FMC_D25 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN1)
|
||||
#define GPIO_FMC_D26 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN2)
|
||||
#define GPIO_FMC_D27 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN3)
|
||||
#define GPIO_FMC_D28 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN6)
|
||||
#define GPIO_FMC_D29 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN7)
|
||||
#define GPIO_FMC_D30 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN9)
|
||||
#define GPIO_FMC_D31 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN10)
|
||||
#define GPIO_FMC_DA0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN14)
|
||||
#define GPIO_FMC_DA1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN15)
|
||||
#define GPIO_FMC_DA2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN0)
|
||||
#define GPIO_FMC_DA3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN1)
|
||||
#define GPIO_FMC_DA4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN7)
|
||||
#define GPIO_FMC_DA5 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN8)
|
||||
#define GPIO_FMC_DA6 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN9)
|
||||
#define GPIO_FMC_DA7 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN10)
|
||||
#define GPIO_FMC_DA8 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN11)
|
||||
#define GPIO_FMC_DA9 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN12)
|
||||
#define GPIO_FMC_DA10 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN13)
|
||||
#define GPIO_FMC_DA11 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN14)
|
||||
#define GPIO_FMC_DA12 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN15)
|
||||
#define GPIO_FMC_DA13 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN8)
|
||||
#define GPIO_FMC_DA14 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN9)
|
||||
#define GPIO_FMC_DA15 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN10)
|
||||
#define GPIO_FMC_INT (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_PORTG|GPIO_PIN7)
|
||||
#define GPIO_FMC_NBL0 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN0)
|
||||
#define GPIO_FMC_NBL1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTE|GPIO_PIN1)
|
||||
#define GPIO_FMC_NBL2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN4)
|
||||
#define GPIO_FMC_NBL3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTI|GPIO_PIN5)
|
||||
#define GPIO_FMC_NCE_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FMC_NCE_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_FMC_NE1_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_FMC_NE1_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_FMC_NE2_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN9)
|
||||
#define GPIO_FMC_NE2_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_FMC_NE3_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN10)
|
||||
#define GPIO_FMC_NE3_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN6)
|
||||
#define GPIO_FMC_NE4 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN12)
|
||||
#define GPIO_FMC_NL (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_FMC_NOE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN4)
|
||||
#define GPIO_FMC_NWAIT_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_FMC_NWAIT_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF9|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_FMC_NWE (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTD|GPIO_PIN5)
|
||||
#define GPIO_FMC_SDCKE0_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_FMC_SDCKE0_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN5)
|
||||
#define GPIO_FMC_SDCKE0_3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN2)
|
||||
#define GPIO_FMC_SDCKE1_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_FMC_SDCKE1_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN7)
|
||||
#define GPIO_FMC_SDCLK (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN8)
|
||||
#define GPIO_FMC_SDNCAS (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTG|GPIO_PIN15)
|
||||
#define GPIO_FMC_SDNE0_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_FMC_SDNE0_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN4)
|
||||
#define GPIO_FMC_SDNE0_3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN3)
|
||||
#define GPIO_FMC_SDNE1_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_FMC_SDNE1_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN6)
|
||||
#define GPIO_FMC_SDNRAS (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTF|GPIO_PIN11)
|
||||
#define GPIO_FMC_SDNWE_1 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_FMC_SDNWE_2 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_FMC_SDNWE_3 (GPIO_ALT|GPIO_PULLUP|GPIO_AF12|GPIO_SPEED_100MHz|GPIO_PORTH|GPIO_PIN5)
|
||||
|
||||
/* HDMI-CEC Controller */
|
||||
|
||||
|
||||
@ -55,6 +55,7 @@
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_fmc.h"
|
||||
#include "stm32_i2c.h"
|
||||
#include "stm32_spi.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
196
arch/arm/src/stm32h7/stm32_fmc.c
Normal file
196
arch/arm/src/stm32h7/stm32_fmc.c
Normal file
@ -0,0 +1,196 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32_fmc.c
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Jason T. Harris <sirmanlypowers@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "stm32.h"
|
||||
|
||||
#if defined(CONFIG_STM32H7_FMC)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking to the FMC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_enable_clk(void)
|
||||
{
|
||||
modifyreg32(STM32_RCC_AHB3ENR, 0, RCC_AHB3ENR_FMCEN);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable clocking to the FMC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_disable(void)
|
||||
{
|
||||
modifyreg32(STM32_RCC_AHB3ENR, RCC_AHB3ENR_FMCEN, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_write_protect
|
||||
*
|
||||
* Description:
|
||||
* Enable/Disable writes to an SDRAM.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_write_protect(int bank, bool state)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t sdcr;
|
||||
|
||||
DEBUGASSERT(bank == 1 || bank == 2);
|
||||
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
|
||||
|
||||
val = getreg32(sdcr);
|
||||
if (state)
|
||||
{
|
||||
val |= FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 1 */
|
||||
}
|
||||
else
|
||||
{
|
||||
val &= ~FMC_SDRAM_CR_WRITE_PROTECT; /* wp == 0 */
|
||||
}
|
||||
|
||||
putreg32(val, sdcr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_set_refresh_rate
|
||||
*
|
||||
* Description:
|
||||
* Set the SDRAM refresh rate.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_set_refresh_rate(int count)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
DEBUGASSERT(count <= 0x1fff && count >= 0x29);
|
||||
putreg32(count << 1, STM32_FMC_SDRTR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_set_timing
|
||||
*
|
||||
* Description:
|
||||
* Set the SDRAM timing parameters.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t sdtr;
|
||||
|
||||
DEBUGASSERT((bank == 1) || (bank == 2));
|
||||
DEBUGASSERT((timing & FMC_SDRAM_TR_RESERVED) == 0);
|
||||
|
||||
sdtr = (bank == 1) ? STM32_FMC_SDTR1 : STM32_FMC_SDTR2;
|
||||
val = getreg32(sdtr);
|
||||
val &= FMC_SDRAM_TR_RESERVED; /* preserve reserved bits */
|
||||
val |= timing;
|
||||
putreg32(val, sdtr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable FMC SDRAM. Do this after issue refresh rate.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_enable(void)
|
||||
{
|
||||
uint32_t val;
|
||||
val = FMC_BCR_FMCEN | getreg32(STM32_FMC_BCR1);
|
||||
putreg32(val, STM32_FMC_BCR1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_set_control
|
||||
*
|
||||
* Description:
|
||||
* Set the SDRAM control parameters.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl)
|
||||
{
|
||||
uint32_t val;
|
||||
uint32_t sdcr;
|
||||
|
||||
DEBUGASSERT((bank == 1) || (bank == 2));
|
||||
DEBUGASSERT((ctrl & FMC_SDRAM_CR_RESERVED) == 0);
|
||||
|
||||
sdcr = (bank == 1) ? STM32_FMC_SDCR1 : STM32_FMC_SDCR2;
|
||||
val = getreg32(sdcr);
|
||||
val &= FMC_SDRAM_CR_RESERVED; /* preserve reserved bits */
|
||||
val |= ctrl;
|
||||
putreg32(val, sdcr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_command
|
||||
*
|
||||
* Description:
|
||||
* Send a command to the SDRAM.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_command(uint32_t cmd)
|
||||
{
|
||||
DEBUGASSERT((cmd & FMC_SDRAM_CMD_RESERVED) == 0);
|
||||
putreg32(cmd, STM32_FMC_SDCMR);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32H7_FMC */
|
||||
159
arch/arm/src/stm32h7/stm32_fmc.h
Normal file
159
arch/arm/src/stm32h7/stm32_fmc.h
Normal file
@ -0,0 +1,159 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32/stm32_fmc.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Jason T. Harris <sirmanlypowers@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_STM32_FMC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_fmc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_wait
|
||||
*
|
||||
* Description:
|
||||
* Wait for the SDRAM controller to be ready.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_wait(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable clocking to the FMC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_enable_clk(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable clocking to the FMC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_disable(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_write_protect
|
||||
*
|
||||
* Description:
|
||||
* Enable/Disable writes to an SDRAM.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_write_protect(int bank, bool state);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_set_refresh_rate
|
||||
*
|
||||
* Description:
|
||||
* Set the SDRAM refresh rate.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_set_refresh_rate(int count);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable FMC SDRAM. Do this after issue refresh rate.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_enable(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_set_timing
|
||||
*
|
||||
* Description:
|
||||
* Set the SDRAM timing parameters.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_set_timing(int bank, uint32_t timing);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_set_control
|
||||
*
|
||||
* Description:
|
||||
* Set the SDRAM control parameters.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_set_control(int bank, uint32_t ctrl);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_fmc_sdram_command
|
||||
*
|
||||
* Description:
|
||||
* Send a command to the SDRAM.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_fmc_sdram_command(uint32_t cmd);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_STM32_FMC_H */
|
||||
Loading…
x
Reference in New Issue
Block a user