Add basic support for the STM32F334

arch/arm/include/stm32/chip.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/include/stm32/chip.h
  *
- *   Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011-2014, 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -86,6 +86,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -126,6 +127,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -166,6 +168,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -206,6 +209,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -246,6 +250,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -286,6 +291,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -404,6 +410,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -442,6 +449,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* FSMC */
@@ -483,6 +491,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* FSMC */
@@ -522,6 +531,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -600,6 +610,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* FSMC */
@@ -638,6 +649,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -676,6 +688,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -714,6 +727,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -757,6 +771,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -798,6 +813,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -839,6 +855,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx families */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -878,6 +895,7 @@
 #  define CONFIG_STM32_CONNECTIVITYLINE  1   /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -915,6 +933,7 @@
 #  define CONFIG_STM32_CONNECTIVITYLINE  1   /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -952,6 +971,7 @@
 #  define CONFIG_STM32_CONNECTIVITYLINE  1   /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -991,6 +1011,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  define CONFIG_STM32_STM32F20XX        1   /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1029,6 +1050,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  define CONFIG_STM32_STM32F20XX        1   /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1067,6 +1089,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  define CONFIG_STM32_STM32F20XX        1   /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1097,7 +1120,7 @@
 /* Part Numbering: STM32Fssscfxxx
  *
  *  Where
- *     sss = 302/303 or 372/373
+ *     sss = 302/303, 334 or 372/373
  *     c   = C (48pins) R (68 pins) V (100 pins)
  *     c   = K (32 pins), C (48 pins), R (68 pins), V (100 pins)
  *     f   = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
@@ -1154,6 +1177,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1194,6 +1218,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1234,6 +1259,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1274,6 +1300,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1314,6 +1341,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1354,6 +1382,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1394,6 +1423,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1434,6 +1464,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1474,6 +1505,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  define CONFIG_STM32_STM32F30XX        1   /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1502,6 +1534,138 @@
 #  define STM32_NRNG                     0   /* (0) No random number generator (RNG) */
 #  define STM32_NDCMI                    0   /* (0) No digital camera interface (DCMI) */
 
+#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8)
+#  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
+#  undef  CONFIG_STM32_HIGHDENSITY           /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef CONFIG_STM32_STM32F30XX             /* STM32F30xxx family */
+#  define CONFIG_STM32_STM32F33XX        1   /* STM32F33xxx family */
+#  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
+#  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
+#  define STM32_NFSMC                    0   /* No FSMC */
+
+#  define STM32_HRTIM                    1   /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
+#  define STM32_NATIM                    1   /* (1) Advanced 16-bit timers with DMA: TIM1*/
+#  define STM32_NGTIM                    5   /* (1) 16-bit general timers with DMA: TIM3
+                                              * (1) 32-bit general timers with DMA: TIM2
+                                              * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
+#  define STM32_NGTIMNDMA                0   /* All timers have DMA */
+#  define STM32_NBTIM                    2   /* (2) Basic timers: TIM6 and TIM7 */
+#  define STM32_NDMA                     1   /* (2) DMA1 (7 channels) */
+#  define STM32_NSPI                     1   /* (3) SPI1 */
+#  define STM32_NI2S                     0   /* (0) I2S1 */
+#  define STM32_NUSART                   2   /* (2) USART1-2 */
+#  define STM32_NI2C                     1   /* (2) I2C1 */
+#  define STM32_NCAN                     1   /* (1) CAN1 */
+#  define STM32_NSDIO                    0   /* (0) No SDIO */
+#  define STM32_NLCD                     0   /* (0) No LCD */
+#  define STM32_NUSBOTG                  0   /* (0) No USB */
+#  define STM32_NGPIO                    25  /* GPIOA-F */
+#  define STM32_NADC                     2   /* (3) 12-bit ADC1-2 */
+#  define STM32_NDAC                     2   /* (2) 12-bit DAC1-2 */
+#  define STM32_NCMP                     2   /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */
+#  define STM32_NPGA                     1   /* (1) Operational amplifiers: OPAMP */
+#  define STM32_NCAPSENSE                14  /* (14) No capacitive sensing channels */
+#  define STM32_NCRC                     1   /* (1) CRC calculation unit */
+#  define STM32_NETHERNET                0   /* (0) No Ethernet MAC */
+#  define STM32_NRNG                     0   /* (0) No random number generator (RNG) */
+#  define STM32_NDCMI                    0   /* (0) No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8)
+#  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
+#  undef  CONFIG_STM32_HIGHDENSITY           /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef CONFIG_STM32_STM32F30XX             /* STM32F30xxx family */
+#  define CONFIG_STM32_STM32F33XX        1   /* STM32F33xxx family */
+#  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
+#  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
+#  define STM32_NFSMC                    0   /* No FSMC */
+
+#  define STM32_HRTIM                    1   /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
+#  define STM32_NATIM                    1   /* (1) Advanced 16-bit timers with DMA: TIM1*/
+#  define STM32_NGTIM                    5   /* (1) 16-bit general timers with DMA: TIM3
+                                              * (1) 32-bit general timers with DMA: TIM2
+                                              * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
+#  define STM32_NGTIMNDMA                0   /* All timers have DMA */
+#  define STM32_NBTIM                    2   /* (2) Basic timers: TIM6 and TIM7 */
+#  define STM32_NDMA                     1   /* (2) DMA1 (7 channels) */
+#  define STM32_NSPI                     1   /* (3) SPI1 */
+#  define STM32_NI2S                     0   /* (0) I2S1 */
+#  define STM32_NUSART                   3   /* (2) USART1-3 */
+#  define STM32_NI2C                     1   /* (2) I2C1 */
+#  define STM32_NCAN                     1   /* (1) CAN1 */
+#  define STM32_NSDIO                    0   /* (0) No SDIO */
+#  define STM32_NLCD                     0   /* (0) No LCD */
+#  define STM32_NUSBOTG                  0   /* (0) No USB */
+#  define STM32_NGPIO                    37  /* GPIOA-F */
+#  define STM32_NADC                     3   /* (3) 12-bit ADC1-3 */
+#  define STM32_NDAC                     2   /* (2) 12-bit DAC1-2 */
+#  define STM32_NCMP                     3   /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */
+#  define STM32_NPGA                     1   /* (1) Operational amplifiers: OPAMP */
+#  define STM32_NCAPSENSE                17  /* (17) No capacitive sensing channels */
+#  define STM32_NCRC                     1   /* (1) CRC calculation unit */
+#  define STM32_NETHERNET                0   /* (0) No Ethernet MAC */
+#  define STM32_NRNG                     0   /* (0) No random number generator (RNG) */
+#  define STM32_NDCMI                    0   /* (0) No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8)
+#  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
+#  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite family */
+#  undef  CONFIG_STM32_STM32F10XX            /* STM32F10xxx family */
+#  undef  CONFIG_STM32_LOWDENSITY            /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMDENSITY         /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+#  undef  CONFIG_STM32_MEDIUMPLUSDENSITY     /* STM32L15xxC w/ 32/256 Kbytes */
+#  undef  CONFIG_STM32_HIGHDENSITY           /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+#  undef  CONFIG_STM32_VALUELINE             /* STM32F100x */
+#  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
+#  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
+#  undef CONFIG_STM32_STM32F30XX             /* STM32F30xxx family */
+#  define CONFIG_STM32_STM32F33XX        1   /* STM32F33xxx family */
+#  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
+#  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
+#  define STM32_NFSMC                    0   /* No FSMC */
+
+#  define STM32_HRTIM                    1   /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
+#  define STM32_NATIM                    1   /* (1) Advanced 16-bit timers with DMA: TIM1*/
+#  define STM32_NGTIM                    5   /* (1) 16-bit general timers with DMA: TIM3
+                                              * (1) 32-bit general timers with DMA: TIM2
+                                              * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
+#  define STM32_NGTIMNDMA                0   /* All timers have DMA */
+#  define STM32_NBTIM                    2   /* (2) Basic timers: TIM6 and TIM7 */
+#  define STM32_NDMA                     1   /* (2) DMA1 (7 channels) */
+#  define STM32_NSPI                     1   /* (3) SPI1 */
+#  define STM32_NI2S                     0   /* (0) I2S1 */
+#  define STM32_NUSART                   3   /* (2) USART1-3 */
+#  define STM32_NI2C                     1   /* (2) I2C1 */
+#  define STM32_NCAN                     1   /* (1) CAN1 */
+#  define STM32_NSDIO                    0   /* (0) No SDIO */
+#  define STM32_NLCD                     0   /* (0) No LCD */
+#  define STM32_NUSBOTG                  0   /* (0) No USB */
+#  define STM32_NGPIO                    51  /* GPIOA-F */
+#  define STM32_NADC                     3   /* (3) 12-bit ADC1-3 */
+#  define STM32_NDAC                     2   /* (3) 12-bit DAC1-2 */
+#  define STM32_NCMP                     3   /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */
+#  define STM32_NPGA                     1   /* (1) Operational amplifiers: OPAMP */
+#  define STM32_NCAPSENSE                18  /* (18) No capacitive sensing channels */
+#  define STM32_NCRC                     1   /* (1) CRC calculation unit */
+#  define STM32_NETHERNET                0   /* (0) No Ethernet MAC */
+#  define STM32_NRNG                     0   /* (0) No random number generator (RNG) */
+#  define STM32_NDCMI                    0   /* (0) No digital camera interface (DCMI) */
+
 #elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC)
 #  undef  CONFIG_STM32_STM32L15XX            /* STM32L151xx and STM32L152xx family */
 #  undef  CONFIG_STM32_ENERGYLITE            /* STM32L EnergyLite vamily */
@@ -1513,6 +1677,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  define CONFIG_STM32_STM32F37XX        1   /* STM32F37xxx family */
 #  undef  CONFIG_STM32_STM32F40XX            /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1558,6 +1723,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1596,6 +1762,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1634,6 +1801,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1672,6 +1840,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    0   /* No FSMC */
@@ -1710,6 +1879,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1748,6 +1918,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1786,6 +1957,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1824,6 +1996,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1862,6 +2035,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1900,6 +2074,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1938,6 +2113,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -1976,6 +2152,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx and STM32407xx */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2014,6 +2191,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2052,6 +2230,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2090,6 +2269,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2128,6 +2308,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2166,6 +2347,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437/429/439 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2204,6 +2386,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2242,6 +2425,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
 #  define STM32_NFSMC                    0   /* FSMC */
@@ -2280,6 +2464,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
 #  define STM32_NFSMC                    0   /* FSMC */
@@ -2318,6 +2503,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2356,6 +2542,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2394,6 +2581,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */
@@ -2435,6 +2623,7 @@
 #  undef  CONFIG_STM32_CONNECTIVITYLINE      /* STM32F105x and STM32F107x */
 #  undef  CONFIG_STM32_STM32F20XX            /* STM32F205x and STM32F207x */
 #  undef  CONFIG_STM32_STM32F30XX            /* STM32F30xxx family */
+#  undef  CONFIG_STM32_STM32F33XX            /* STM32F33xxx family */
 #  undef  CONFIG_STM32_STM32F37XX            /* STM32F37xxx family */
 #  define CONFIG_STM32_STM32F40XX        1   /* STM32F405xx, STM32407xx and STM32F427/437 */
 #  define STM32_NFSMC                    1   /* FSMC */

arch/arm/include/stm32/irq.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/include/stm32s/irq.h
  *
- *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -85,6 +85,8 @@
 #  include <arch/stm32/stm32f20xxx_irq.h>
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include <arch/stm32/stm32f30xxx_irq.h>
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include <arch/stm32/stm32f33xxx_irq.h>
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include <arch/stm32/stm32f37xxx_irq.h>
 #elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/include/stm32/stm32f33xxx_irq.h

@@ -0,0 +1,185 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32s/stm32f37xxx_irq.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/irq.h>
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers.  The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC.  This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15).  These common definitions can be found
+ * in nuttx/arch/arm/include/stm32/irq.h
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define STM32_IRQ_WWDG        (STM32_IRQ_FIRST+0)  /* 0:  Window Watchdog interrupt */
+#define STM32_IRQ_PVD         (STM32_IRQ_FIRST+1)  /* 1:  PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER      (STM32_IRQ_FIRST+2)  /* 2:  Tamper interrupt, or */
+#define STM32_IRQ_TIMESTAMP   (STM32_IRQ_FIRST+2)  /* 2:  Time stamp interrupt */
+#define STM32_IRQ_RTC_WKUP    (STM32_IRQ_FIRST+3)  /* 3:  RTC global interrupt */
+#define STM32_IRQ_FLASH       (STM32_IRQ_FIRST+4)  /* 4:  Flash global interrupt */
+#define STM32_IRQ_RCC         (STM32_IRQ_FIRST+5)  /* 5:  RCC global interrupt */
+#define STM32_IRQ_EXTI0       (STM32_IRQ_FIRST+6)  /* 6:  EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1       (STM32_IRQ_FIRST+7)  /* 7:  EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2       (STM32_IRQ_FIRST+8)  /* 8:  EXTI Line 2 interrupt, or */
+#define STM32_IRQ_TSC         (STM32_IRQ_FIRST+8)  /* 8:  TSC interrupt */
+#define STM32_IRQ_EXTI3       (STM32_IRQ_FIRST+9)  /* 9:  EXTI Line 3 interrupt */
+#define STM32_IRQ_EXTI4       (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1     (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2     (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3     (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4     (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5     (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6     (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7     (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC12       (STM32_IRQ_FIRST+18) /* 18: ADC1/ADC2 global interrupt */
+#define STM32_IRQ_CAN1TX      (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
+#define STM32_IRQ_CAN1RX0     (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts*/
+#define STM32_IRQ_CAN1RX1     (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
+#define STM32_IRQ_CAN1SCE     (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
+#define STM32_IRQ_EXTI95      (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM1BRK     (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt, or */
+#define STM32_IRQ_TIM15       (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
+#define STM32_IRQ_TIM1UP      (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt, or */
+#define STM32_IRQ_TIM16       (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
+#define STM32_IRQ_TIM1TRGCOM  (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts, or */
+#define STM32_IRQ_TIM17       (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
+#define STM32_IRQ_TIM1CC      (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2        (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3        (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+#define STM32_IRQ_RESERVED30  (STM32_IRQ_FIRST+30) /* 30: Reserved */
+#define STM32_IRQ_I2C1EV      (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER      (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_RESERVED33  (STM32_IRQ_FIRST+33) /* 33: Reserved */
+#define STM32_IRQ_RESERVED34  (STM32_IRQ_FIRST+34) /* 34: Reserved */
+#define STM32_IRQ_SPI1        (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_RESERVED36  (STM32_IRQ_FIRST+36) /* 36: Reserved */
+#define STM32_IRQ_USART1      (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2      (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3      (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+#define STM32_IRQ_EXTI1510    (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM     (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_RESERVED42  (STM32_IRQ_FIRST+42) /* 42: Reserved */
+#define STM32_IRQ_RESERVED43  (STM32_IRQ_FIRST+43) /* 43: Reserved */
+#define STM32_IRQ_RESERVED44  (STM32_IRQ_FIRST+44) /* 44: Reserved */
+#define STM32_IRQ_RESERVED45  (STM32_IRQ_FIRST+45) /* 45: Reserved */
+#define STM32_IRQ_RESERVED46  (STM32_IRQ_FIRST+46) /* 46: Reserved */
+#define STM32_IRQ_RESERVED47  (STM32_IRQ_FIRST+47) /* 47: Reserved */
+#define STM32_IRQ_RESERVED48  (STM32_IRQ_FIRST+48) /* 48: Reserved */
+#define STM32_IRQ_RESERVED49  (STM32_IRQ_FIRST+49) /* 49: Reserved */
+#define STM32_IRQ_RESERVED50  (STM32_IRQ_FIRST+50) /* 50: Reserved */
+#define STM32_IRQ_RESERVED51  (STM32_IRQ_FIRST+51) /* 51: Reserved */
+#define STM32_IRQ_RESERVED52  (STM32_IRQ_FIRST+52) /* 52: Reserved */
+#define STM32_IRQ_RESERVED53  (STM32_IRQ_FIRST+53) /* 53: Reserved */
+#define STM32_IRQ_TIM6        (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt, or */
+#define STM32_IRQ_DAC1        (STM32_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */
+#define STM32_IRQ_TIM7        (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt, or */
+#define STM32_IRQ_DAC2        (STM32_IRQ_FIRST+54) /* 55: DAC2 underrun error interrupts */
+#define STM32_IRQ_RESERVED56  (STM32_IRQ_FIRST+56) /* 56: Reserved */
+#define STM32_IRQ_RESERVED57  (STM32_IRQ_FIRST+57) /* 57: Reserved */
+#define STM32_IRQ_RESERVED58  (STM32_IRQ_FIRST+58) /* 58: Reserved */
+#define STM32_IRQ_RESERVED59  (STM32_IRQ_FIRST+59) /* 59: Reserved */
+#define STM32_IRQ_RESERVED60  (STM32_IRQ_FIRST+60) /* 60: Reserved */
+#define STM32_IRQ_RESERVED61  (STM32_IRQ_FIRST+61) /* 61: Reserved */
+#define STM32_IRQ_RESERVED62  (STM32_IRQ_FIRST+62) /* 62: Reserved */
+#define STM32_IRQ_RESERVED63  (STM32_IRQ_FIRST+63) /* 63: Reserved */
+#define STM32_IRQ_COMP2       (STM32_IRQ_FIRST+64) /* 64: COMP2 interrupts, or */
+#define STM32_IRQ_EXTI2129    (STM32_IRQ_FIRST+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */
+#define STM32_IRQ_COMP46      (STM32_IRQ_FIRST+65) /* 65: COMP4 & COMP6 interrupts, or */
+#define STM32_IRQ_EXTI3012    (STM32_IRQ_FIRST+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */
+#define STM32_IRQ_RESERVED66  (STM32_IRQ_FIRST+66) /* 66: Reserved */
+#define STM32_IRQ_HRTIMTM     (STM32_IRQ_FIRST+67) /* 67: HRTIM master timer interrupt */
+#define STM32_IRQ_HRTIMTA     (STM32_IRQ_FIRST+68) /* 68: HRTIM timer A interrupt */
+#define STM32_IRQ_HRTIMTB     (STM32_IRQ_FIRST+69) /* 69: HRTIM timer B interrupt */
+#define STM32_IRQ_HRTIMTC     (STM32_IRQ_FIRST+70) /* 70: HRTIM timer C interrupt */
+#define STM32_IRQ_HRTIMTD     (STM32_IRQ_FIRST+71) /* 71: HRTIM timer D interrupt */
+#define STM32_IRQ_HRTIMTE     (STM32_IRQ_FIRST+72) /* 72: HRTIM timer E interrupt */
+#define STM32_IRQ_HRTIMFLT    (STM32_IRQ_FIRST+73) /* 73: HRTIM fault interrupt */
+#define STM32_IRQ_RESERVED74  (STM32_IRQ_FIRST+74) /* 74: Reserved */
+#define STM32_IRQ_RESERVED75  (STM32_IRQ_FIRST+75) /* 75: Reserved */
+#define STM32_IRQ_RESERVED76  (STM32_IRQ_FIRST+76) /* 76: Reserved */
+#define STM32_IRQ_RESERVED77  (STM32_IRQ_FIRST+77) /* 77: Reserved */
+#define STM32_IRQ_RESERVED78  (STM32_IRQ_FIRST+78) /* 78: Reserved */
+#define STM32_IRQ_RESERVED79  (STM32_IRQ_FIRST+79) /* 79: Reserved */
+#define STM32_IRQ_RESERVED80  (STM32_IRQ_FIRST+80) /* 80: Reserved */
+#define STM32_IRQ_FPU         (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+
+#define NR_VECTORS            (STM32_IRQ_FIRST+82)
+#define NR_IRQS               (STM32_IRQ_FIRST+82)
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */

arch/arm/src/stm32/Kconfig

@@ -773,6 +773,60 @@ config ARCH_CHIP_STM32F303VC
 	select STM32_HAVE_UART5
 	select STM32_HAVE_USBDEV
 
+config ARCH_CHIP_STM32F334K4
+	bool "STM32F334K4"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334K6
+	bool "STM32F334K6"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334K8
+	bool "STM32F334K8"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334C4
+	bool "STM32F334C4"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334C6
+	bool "STM32F334C6"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334C8
+	bool "STM32F334C8"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334R4
+	bool "STM32F334R4"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334R6
+	bool "STM32F334R6"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
+config ARCH_CHIP_STM32F334R8
+	bool "STM32F334R8"
+	select ARCH_CORTEXM4
+	select STM32_STM32F33XX
+	select ARCH_HAVE_FPU
+
 config ARCH_CHIP_STM32F372C8
 	bool "STM32F372C8"
 	select ARCH_CORTEXM4
@@ -1388,6 +1442,25 @@ config STM32_STM32F303
 	select STM32_HAVE_DAC2
 	select STM32_HAVE_TIM7
 
+config STM32_STM32F33XX
+	bool
+       	default n
+	select STM32_HAVE_HRTIM1
+	select STM32_HAVE_COMP2
+	select STM32_HAVE_COMP4
+	select STM32_HAVE_COMP6
+	select STM32_HAVE_OPAMP
+	select STM32_HAVE_CCM
+	select STM32_HAVE_TIM1
+	select STM32_HAVE_TIM15
+	select STM32_HAVE_TIM16
+	select STM32_HAVE_TIM17
+	select STM32_HAVE_ADC2
+	select STM32_HAVE_CAN1
+	select STM32_HAVE_DAC1
+	select STM32_HAVE_DAC2
+	select STM32_HAVE_USART3
+
 config STM32_STM32F37XX
 	bool
 	default n
@@ -1673,6 +1746,10 @@ config STM32_HAVE_FSMC
 	bool
 	default n
 
+config STM32_HAVE_HRTIM1
+	bool
+	default n
+
 config STM32_HAVE_LTDC
 	bool
 	default n
@@ -1829,6 +1906,18 @@ config STM32_HAVE_CAN2
 	bool
 	default n
 
+config STM32_HAVE_COMP2
+       bool
+       default n
+
+config STM32_HAVE_COMP4
+       bool
+       default n
+
+config STM32_HAVE_COMP6
+       bool
+       default n
+
 config STM32_HAVE_DAC1
 	bool
 	default n
@@ -1881,6 +1970,10 @@ config STM32_HAVE_I2SPLL
 	bool
 	default n
 
+config STM32_HAVE_OPAMP
+       bool
+       default n
+
 # These are the peripheral selections proper
 
 config STM32_ADC1
@@ -1938,6 +2031,21 @@ config STM32_COMP
 	default n
 	depends on STM32_STM32L15XX
 
+config STM32_COMP2
+	bool "COMP2"
+	default n
+	depends on STM32_HAVE_COMP2
+
+config STM32_COMP4
+	bool "COMP4"
+	default n
+	depends on STM32_HAVE_COMP4
+
+config STM32_COMP6
+	bool "COMP6"
+	default n
+	depends on STM32_HAVE_COMP6
+
 config STM32_BKP
 	bool "BKP"
 	default n
@@ -2033,6 +2141,11 @@ config STM32_HASH
 	default n
 	depends on STM32_STM32F207 || STM32_STM32F40XX
 
+config STM32_HRTIM1
+	bool "HRTIM1"
+	default n
+	depends on STM32_HAVE_HRTIM1
+
 config STM32_I2C1
 	bool "I2C1"
 	default n
@@ -2068,6 +2181,11 @@ config STM32_DMA2D
 		The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation
 		available on the STM32F429 and STM32F439 devices.
 
+config STM32_OPAMP
+	bool "OPAMP"
+	default n
+	depends on STM32_HAVE_OPAMP
+
 config STM32_OTGFS
 	bool "OTG FS"
 	default n

arch/arm/src/stm32/chip.h

@@ -127,6 +127,8 @@
 
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_pinmap.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_pinmap.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_pinmap.h"
 
@@ -151,6 +153,8 @@
 #    include "chip/stm32f20xxx_vectors.h"
 #  elif defined(CONFIG_STM32_STM32F30XX)
 #    include "chip/stm32f30xxx_vectors.h"
+#  elif defined(CONFIG_STM32_STM32F33XX)
+#    include "chip/stm32f33xxx_vectors.h"
 #  elif defined(CONFIG_STM32_STM32F37XX)
 #    include "chip/stm32f37xxx_vectors.h"
 #  elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/chip/stm32_dbgmcu.h

@@ -53,7 +53,8 @@
 #define STM32_DBGMCU_IDCODE       0xe0042000  /* MCU identifier */
 #define STM32_DBGMCU_CR           0xe0042004  /* MCU debug */
 #if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F40XX) || defined(CONFIG_STM32_STM32L15XX)
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F40XX) || \
+    defined(CONFIG_STM32_STM32L15XX)
 #  define STM32_DBGMCU_APB1_FZ    0xe0042008  /* Debug MCU APB1 freeze register */
 #  define STM32_DBGMCU_APB2_FZ    0xe004200c  /* Debug MCU APB2 freeze register */
 #endif
@@ -118,7 +119,8 @@
 #  define DBGMCU_APB1_I2C3STOP    (1 << 23)  /* Bit 23: SMBUS timeout mode stopped when Core is halted */
 #  define DBGMCU_APB1_CAN1STOP    (1 << 25)  /* Bit 25: CAN1 stopped when core is halted */
 #  define DBGMCU_APB1_CAN2STOP    (1 << 26)  /* Bit 26: CAN2 stopped when core is halted */
-#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32L15XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+      defined(CONFIG_STM32_STM32L15XX)
 #  define DBGMCU_APB1_TIM2STOP    (1 << 0)   /* Bit 0: TIM2 stopped when core is halted */
 #  define DBGMCU_APB1_TIM3STOP    (1 << 1)   /* Bit 1: TIM3 stopped when core is halted */
 #  define DBGMCU_APB1_TIM4STOP    (1 << 2)   /* Bit 2: TIM4 stopped when core is halted */
@@ -129,7 +131,7 @@
 #  define DBGMCU_APB1_IWDGSTOP    (1 << 12)  /* Bit 12: Independent Watchdog stopped when core is halted */
 #  define DBGMCU_APB1_I2C1STOP    (1 << 21)  /* Bit 21: SMBUS timeout mode stopped when Core is halted */
 #  define DBGMCU_APB1_I2C2STOP    (1 << 22)  /* Bit 22: SMBUS timeout mode stopped when Core is halted */
-#  if defined(CONFIG_STM32_STM32F30XX)
+#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #    define DBGMCU_APB1_CAN1STOP  (1 << 25)  /* Bit 25: CAN1 stopped when core is halted */
 #  endif
 #endif
@@ -142,7 +144,7 @@
 #  define DBGMCU_APB2_TIM9STOP    (1 << 16)  /* Bit 16: TIM9 stopped when core is halted */
 #  define DBGMCU_APB2_TIM10STOP   (1 << 17)  /* Bit 17: TIM10 stopped when core is halted */
 #  define DBGMCU_APB2_TIM11STOP   (1 << 18)  /* Bit 18: TIM11 stopped when core is halted */
-#elif defined(CONFIG_STM32_STM32F30XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #  define DBGMCU_APB2_TIM1STOP    (1 << 0)   /* Bit 0:  TIM1 stopped when core is halted */
 #  define DBGMCU_APB2_TIM8STOP    (1 << 1)   /* Bit 1:  TIM8 stopped when core is halted */
 #  define DBGMCU_APB2_TIM15STOP   (1 << 2)   /* Bit 2:  TIM15 stopped when core is halted */

arch/arm/src/stm32/chip/stm32_exti.h

@@ -55,7 +55,7 @@
 #    define STM32_NEXTI          19
 #    define STM32_EXTI_MASK      0x0007ffff
 #  endif
-#elif defined(CONFIG_STM32_STM32F30XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #    define STM32_NEXTI1         31
 #    define STM32_EXTI1_MASK     0xffffffff
 #    define STM32_NEXTI2         4
@@ -69,7 +69,7 @@
 
 /* Register Offsets *****************************************************************/
 
-#if defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #  define STM32_EXTI1_OFFSET     0x0000  /* Offset to EXTI1 registers */
 #  define STM32_EXTI2_OFFSET     0x0018  /* Offset to EXTI2 registers */
 #endif
@@ -83,7 +83,7 @@
 
 /* Register Addresses ***************************************************************/
 
-#if defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #  define STM32_EXTI1_BASE       (STM32_EXTI_BASE+STM32_EXTI1_OFFSET)
 #  define STM32_EXTI2_BASE       (STM32_EXTI_BASE+STM32_EXTI2_OFFSET)
 
@@ -146,7 +146,8 @@
 #  define EXTI_RTC_TAMPER        (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
 #  define EXTI_RTC_TIMESTAMP     (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
 #  define EXTI_RTC_WAKEUP        (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */
-#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+      defined(CONFIG_STM32_STM32F37XX)
 #  define EXTI_PVD_LINE          (1 << 16) /* EXTI line 16 is connected to the PVD output */
 #  define EXTI_RTC_ALARM         (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
 #  define EXTI_OTGFS_WAKEUP      (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */
@@ -193,7 +194,7 @@
 
 /* Compatibility Definitions ********************************************************/
 
-#if defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)
 #  define STM32_NEXTI            STM32_NEXTI1
 #  define STM32_EXTI_MASK        STM32_EXTI1_MASK
 #  define STM32_EXTI_IMR         STM32_EXTI1_IMR

arch/arm/src/stm32/chip/stm32_flash.h

@@ -90,6 +90,10 @@
 #    define STM32_FLASH_NPAGES        128
 #    define STM32_FLASH_PAGESIZE      2048
 
+#  elif defined(CONFIG_STM32_STM32F33XX)
+#    define STM32_FLASH_NPAGES        32
+#    define STM32_FLASH_PAGESIZE      2048
+
 #  elif defined(CONFIG_STM32_STM32F37XX)
 #    define STM32_FLASH_NPAGES        128
 #    define STM32_FLASH_PAGESIZE      2048
@@ -212,7 +216,7 @@
 #define STM32_FLASH_CR_OFFSET      0x0010
 
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
 #  define STM32_FLASH_AR_OFFSET    0x0014
 #  define STM32_FLASH_OBR_OFFSET   0x001c
 #  define STM32_FLASH_WRPR_OFFSET  0x0020
@@ -233,7 +237,7 @@
 #define STM32_FLASH_CR             (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
 
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
 #  define STM32_FLASH_AR           (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
 #  define STM32_FLASH_OBR          (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
 #  define STM32_FLASH_WRPR         (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
@@ -267,10 +271,11 @@
 #    define FLASH_ACR_LATENCY_7     (7 << FLASH_ACR_LATENCY_SHIFT)    /* 111: Seven wait states */
 
 #  if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-      defined(CONFIG_STM32_STM32F37XX)
+      defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
 #    define FLASH_ACR_HLFCYA        (1 << 3)  /* Bit 3: FLASH half cycle access */
 #    define FLASH_ACR_PRTFBE        (1 << 4)  /* Bit 4: FLASH prefetch enable */
-#    if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#    if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+     defined(CONFIG_STM32_STM32F37XX)
 #      define FLASH_ACR_PRFTBS      (1 << 5)  /* Bit 5: FLASH prefetch buffer status */
 #    endif
 #  elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
@@ -285,7 +290,7 @@
 /* Flash Status Register (SR) */
 
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
 #  define FLASH_SR_BSY              (1 << 0)  /* Busy */
 #  define FLASH_SR_PGERR            (1 << 2)  /* Programming Error */
 #  define FLASH_SR_WRPRT_ERR        (1 << 4)  /* Write Protection Error */
@@ -303,7 +308,7 @@
 /* Flash Control Register (CR) */
 
 #if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX) || \
-    defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F33XX) || defined(CONFIG_STM32_STM32F37XX)
 #  define FLASH_CR_PG               (1 << 0)  /* Bit 0: Program Page */
 #  define FLASH_CR_PER              (1 << 1)  /* Bit 1: Page Erase */
 #  define FLASH_CR_MER              (1 << 2)  /* Bit 2: Mass Erase */
@@ -314,7 +319,8 @@
 #  define FLASH_CR_OPTWRE           (1 << 9)  /* Bit 8: Option Bytes Write Enable */
 #  define FLASH_CR_ERRIE            (1 << 10) /* Bit 10: Error Interrupt Enable */
 #  define FLASH_CR_EOPIE            (1 << 12) /* Bit 12: End of Program Interrupt Enable */
-#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+      defined(CONFIG_STM32_STM32F37XX)
 #    define FLASH_CR_OBL_LAUNCH     (1 << 13) /* Bit 13: Force option byte loading */
 #  endif
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/chip/stm32_memorymap.h

@@ -51,6 +51,8 @@
 #  include "chip/stm32f20xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_memorymap.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_memorymap.h"
 #elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/chip/stm32_pwr.h

@@ -150,7 +150,8 @@
 #if defined(CONFIG_STM32_STM32F30XX)
 #  define PWR_CSR_EWUP1        (1 << 8)  /* Bit 8:  Enable WKUP1 pin */
 #  define PWR_CSR_EWUP2        (1 << 9)  /* Bit 9:  Enable WKUP2 pin */
-#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F37XX)
+#elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F33XX) || \
+      defined(CONFIG_STM32_STM32F37XX)
 #  define PWR_CSR_EWUP1        (1 << 8)  /* Bit 8:  Enable WKUP1 pin */
 #  define PWR_CSR_EWUP2        (1 << 9)  /* Bit 9:  Enable WKUP2 pin */
 #  define PWR_CSR_EWUP3        (1 << 10) /* Bit 8:  Enable WKUP3 pin */

arch/arm/src/stm32/chip/stm32f10xxx_dma.h

@@ -520,6 +520,75 @@
 #  define DMACHAN_UART4_TX        STM32_DMA2_CHAN5
 #  define DMACHAN_TIM8_CH2        STM32_DMA2_CHAN5
 
+#elif defined(CONFIG_STM32_STM32F33XX)
+
+#  define DMACHAN_ADC1            STM32_DMA1_CHAN1
+#  define DMACHAN_TIM2_CH3        STM32_DMA1_CHAN1
+#  define DMACHAN_TIM17_CH1_1     STM32_DMA1_CHAN1
+#  define DMACHAN_TIM17_UP_1      STM32_DMA1_CHAN1
+
+#  define DMACHAN_ADC2_1          STM32_DMA1_CHAN2
+#  define DMACHAN_SPI1_RX_1       STM32_DMA1_CHAN2
+#  define DMACHAN_USART3_TX       STM32_DMA1_CHAN2
+#  define DMACHAN_I2C1_TX_3       STM32_DMA1_CHAN4
+#  define DMACHAN_TIM1_CH1        STM32_DMA1_CHAN2
+#  define DMACHAN_TIM2_UP         STM32_DMA1_CHAN2
+#  define DMACHAN_TIM3_CH3        STM32_DMA1_CHAN2
+#  define DMACHAN_HRTIM1_M        STM32_DMA1_CHAN2
+
+#  define DMACHAN_SPI1_TX_1       STM32_DMA1_CHAN3
+#  define DMACHAN_USART3_RX       STM32_DMA1_CHAN3
+#  define DMACHAN_I2C1_RX_2       STM32_DMA1_CHAN3
+#  define DMACHAN_TIM3_CH4        STM32_DMA1_CHAN3
+#  define DMACHAN_TIM3_UP         STM32_DMA1_CHAN3
+#  define DMACHAN_TIM6_UP         STM32_DMA1_CHAN3
+#  define DMACHAN_DAC1_CH1        STM32_DMA1_CHAN3
+#  define DMACHAN_DAC16_CH1_1     STM32_DMA1_CHAN3
+#  define DMACHAN_DAC16_UP_1      STM32_DMA1_CHAN3
+#  define DMACHAN_HRTIM1_A        STM32_DMA1_CHAN3
+
+#  define DMACHAN_ADC2_2          STM32_DMA1_CHAN4
+#  define DMACHAN_SPI1_RX_2       STM32_DMA1_CHAN4
+#  define DMACHAN_USART1_TX       STM32_DMA1_CHAN4
+#  define DMACHAN_I2C1_TX_3       STM32_DMA1_CHAN4
+#  define DMACHAN_TIM1_CH4        STM32_DMA1_CHAN4
+#  define DMACHAN_TIM1_TRIG       STM32_DMA1_CHAN4
+#  define DMACHAN_TIM1_COM        STM32_DMA1_CHAN4
+#  define DMACHAN_TIM7_UP         STM32_DMA1_CHAN4
+#  define DMACHAN_DAC2_CH2        STM32_DMA1_CHAN4
+#  define DMACHAN_HRTIM1_B        STM32_DMA1_CHAN4
+
+#  define DMACHAN_SPI1_TX_2       STM32_DMA1_CHAN5
+#  define DMACHAN_USART1_RX       STM32_DMA1_CHAN5
+#  define DMACHAN_I2C1_RX_3       STM32_DMA1_CHAN5
+#  define DMACHAN_TIM1_UP         STM32_DMA1_CHAN5
+#  define DMACHAN_TIM2_CH1        STM32_DMA1_CHAN5
+#  define DMACHAN_DAC2_CH1        STM32_DMA1_CHAN5
+#  define DMACHAN_TIM15_CH1       STM32_DMA1_CHAN5
+#  define DMACHAN_TIM15_UP        STM32_DMA1_CHAN5
+#  define DMACHAN_TIM15_TRIG      STM32_DMA1_CHAN5
+#  define DMACHAN_TIM15_COM       STM32_DMA1_CHAN5
+#  define DMACHAN_HRTIM1_C        STM32_DMA1_CHAN5
+
+#  define DMACHAN_SPI1_RX_3       STM32_DMA1_CHAN6
+#  define DMACHAN_USART2_RX       STM32_DMA1_CHAN6
+#  define DMACHAN_I2C1_TX_1       STM32_DMA1_CHAN6
+#  define DMACHAN_TIM1_CH3        STM32_DMA1_CHAN6
+#  define DMACHAN_TIM3_CH1        STM32_DMA1_CHAN6
+#  define DMACHAN_TIM3_TRIG       STM32_DMA1_CHAN6
+#  define DMACHAN_TIM16_CH1_2     STM32_DMA1_CHAN6
+#  define DMACHAN_TIM16_UP_2      STM32_DMA1_CHAN6
+#  define DMACHAN_HRTIM1_D        STM32_DMA1_CHAN6
+
+#  define DMACHAN_SPI1_TX_3       STM32_DMA1_CHAN7
+#  define DMACHAN_USART2_TX       STM32_DMA1_CHAN7
+#  define DMACHAN_I2C1_RX_1       STM32_DMA1_CHAN7
+#  define DMACHAN_TIM2_CH2        STM32_DMA1_CHAN7
+#  define DMACHAN_TIM2_CH4        STM32_DMA1_CHAN7
+#  define DMACHAN_TIM17_CH1_2     STM32_DMA1_CHAN7
+#  define DMACHAN_TIM17_UP_2      STM32_DMA1_CHAN7
+#  define DMACHAN_HRTIM1_E        STM32_DMA1_CHAN7
+
 #elif defined(CONFIG_STM32_STM32F37XX)
 
 #  define DMACHAN_ADC1            STM32_DMA1_CHAN1

arch/arm/src/stm32/chip/stm32f33xxx_dac.h

@@ -0,0 +1 @@
+/* todo */

arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h

@@ -0,0 +1,149 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f33xxx_memorymap.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* STM32F33XXX Address Blocks *******************************************************/
+
+#define STM32_CODE_BASE      0x00000000     /* 0x00000000-0x1fffffff: 512Mb code block */
+#define STM32_SRAM_BASE      0x20000000     /* 0x20000000-0x3fffffff: 512Mb sram block */
+#define STM32_PERIPH_BASE    0x40000000     /* 0x40000000-0x5fffffff: 512Mb peripheral block */
+                                            /* 0x60000000-0xdfffffff: Reserved */
+#define STM32_CORTEX_BASE    0xe0000000     /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
+
+#define STM32_REGION_MASK    0xf0000000
+#define STM32_IS_SRAM(a)     ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_SRAM_BASE)
+
+/* Code Base Addresses **************************************************************/
+
+#define STM32_BOOT_BASE      0x00000000     /* 0x00000000-0x0000ffff: Aliased boot memory */
+                                            /* 0x00010000-0x07ffffff: Reserved */
+#define STM32_FLASH_BASE     0x08000000     /* 0x08000000-0x0800ffff: FLASH memory */
+                                            /* 0x08100000-0x1ffeffff: Reserved */
+#define STM32_CCMRAM_BASE    0x10000000     /* 0x10000000-0x10000fff: 4Kb CCM data RAM */
+                                            /* 0x10001000-0x1ffeffff: Reserved */
+#define STM32_SYSMEM_BASE    0x1fffd800     /* 0x1fff0000-0x1fff7a0f: System memory */
+                                            /* 0x1fff7a10-0x1fff7fff: Reserved */
+#define STM32_OPTION_BASE    0x1ffff800     /* 0x1fffc000-0x1fffc007: Option bytes */
+                                            /* 0x1fffc008-0x1fffffff: Reserved */
+
+
+/* System Memory Addresses **********************************************************/
+
+#define STM32_SYSMEM_UID     0x1ffff7ac     /* The 96-bit unique device identifier */
+#define STM32_SYSMEM_FSIZE   0x1ffff7cc     /* This bitfield indicates the size of
+                                             * the device Flash memory expressed in
+                                             * Kbytes.  Example: 0x040 corresponds
+                                             * to 64 Kbytes
+                                             */
+
+/* Peripheral Base Addresses ********************************************************/
+
+#define STM32_APB1_BASE      0x40000000     /* 0x40000000-0x40009fff: APB1 */
+                                            /* 0x4000a000-0x4000ffff: Reserved */
+#define STM32_APB2_BASE      0x40010000     /* 0x40010000-0x40006bff: APB2 */
+                                            /* 0x40016c00-0x4001ffff: Reserved */
+#define STM32_AHB1_BASE      0x40020000     /* 0x40020000-0x400243ff: APB1 */
+                                            /* 0x40024400-0x4007ffff: Reserved */
+#define STM32_AHB2_BASE      0x48000000     /* 0x48000000-0x480017ff: AHB2 */
+                                            /* 0x48001800-0x4fffffff: Reserved */
+#define STM32_AHB3_BASE      0x50000000     /* 0x50000000-0x500003ff: AHB3 */
+
+/* APB1 Base Addresses **************************************************************/
+
+#define STM32_TIM2_BASE      0x40000000     /* 0x40000000-0x400003ff TIM2 */
+#define STM32_TIM3_BASE      0x40000400     /* 0x40000400-0x400007ff TIM3 */
+#define STM32_TIM6_BASE      0x40001000     /* 0x40001000-0x400013ff TIM6 */
+#define STM32_TIM7_BASE      0x40001400     /* 0x40001400-0x400017ff TIM7 */
+#define STM32_RTC_BASE       0x40002800     /* 0x40002800-0x40002bff RTC */
+#define STM32_BKP_BASE       0x40002850     /* 0x40002850-0x400028cc BKP */
+#define STM32_WWDG_BASE      0x40002c00     /* 0x40002c00-0x40002fff WWDG */
+#define STM32_IWDG_BASE      0x40003000     /* 0x40003000-0x400033ff IWDG */
+#define STM32_USART2_BASE    0x40004400     /* 0x40004400-0x400047ff USART2 */
+#define STM32_USART3_BASE    0x40004800     /* 0x40004800-0x40004bff USART3 */
+#define STM32_I2C1_BASE      0x40005400     /* 0x40005400-0x400057ff I2C1 */
+#define STM32_CAN1_BASE      0x40006400     /* 0x40006400-0x400067ff bxCAN */
+#define STM32_PWR_BASE       0x40007000     /* 0x40007000-0x400073ff PWR */
+#define STM32_DAC1_BASE      0x40007400     /* 0x40007400-0x400077ff DAC1 */
+#define STM32_DAC2_BASE      0x40009800     /* 0x40009800-0x40009bff DAC2 */
+
+/* APB2 Base Addresses **************************************************************/
+
+#define STM32_SYSCFG_BASE    0x40010000     /* 0x40010000-0x400103FF SYSCFG + COMP + OPAMP */
+#define STM32_EXTI_BASE      0x40010400     /* 0x40010400-0x400107FF EXTI */
+#define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00-0x40012fff TIM1 */
+#define STM32_SPI1_BASE      0x40013000     /* 0x40013000-0x400133ff SPI1 */
+#define STM32_USART1_BASE    0x40013800     /* 0x40013800-0x40013bff USART1 */
+#define STM32_TIM15_BASE     0x40014000     /* 0x40014000-0x400143ff TIM15 */
+#define STM32_TIM16_BASE     0x40014400     /* 0x40014400-0x400147ff TIM16 */
+#define STM32_TIM17_BASE     0x40014800     /* 0x40014800-0x40014bff TIM17 */
+#define STM32_HRTIM1_BASE    0x40017400     /* 0x40017400-0x400177ff TIM19 */
+
+/* AHB1 Base Addresses **************************************************************/
+
+#define STM32_DMA1_BASE      0x40020000     /* 0x40020000-0x400203ff: DMA1  */
+#define STM32_RCC_BASE       0x40021000     /* 0x40021000-0x400213ff: Reset and Clock control RCC */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000-0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE       0x40023000     /* 0x40023000-0x400233ff: CRC */
+#define STM32_TSC_BASE       0x40024000     /* 0x40024000-0x400243ff: TSC */
+
+/* AHB2 Base Addresses **************************************************************/
+
+#define STM32_GPIOA_BASE     0x48000000     /* 0x48000000-0x480003ff: GPIO Port A */
+#define STM32_GPIOB_BASE     0x48000400     /* 0x48000400-0x480007ff: GPIO Port B */
+#define STM32_GPIOC_BASE     0x48000800     /* 0x48000800-0x48000bff: GPIO Port C */
+#define STM32_GPIOD_BASE     0X48000C00     /* 0x48000c00-0x48000fff: GPIO Port D */
+#define STM32_GPIOE_BASE     0X48001000     /* 0x48001000-0x480013ff: GPIO Port E */
+#define STM32_GPIOF_BASE     0x48001400     /* 0x48001400-0x480017ff: GPIO Port F */
+
+/* AHB3 Base Addresses **************************************************************/
+
+#define STM32_ADC12_BASE      0x50000000     /* 0x50000000-0x500003ff: ADC12 */
+
+/* Cortex-M4 Base Addresses *********************************************************/
+/* Other registers -- see armv7-m/nvic.h for standard Cortex-M4 registers in this
+ * address range
+ */
+
+#define STM32_SCS_BASE      0xe000e000
+#define STM32_DEBUGMCU_BASE 0xe0042000
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_MEMORYMAP_H */

arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h

@@ -0,0 +1,464 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "stm32_gpio.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Alternate Pin Functions.  All members of the STM32F33xxx family share the same
+ * pin multiplexing (although they may differ in the pins physically available).
+ *
+ * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
+ * Drivers, however, will use the pin selection without the numeric suffix.
+ * Additional definitions are required in the board.h file.  For example, if
+ * CAN1_RX connects vis PA11 on some board, then the following definitions should
+ * appear inthe board.h header file for that board:
+ *
+ * #define GPIO_CAN1_RX GPIO_CAN1_RX_1
+ *
+ * The driver will then automatically configre PA11 as the CAN1 RX pin.
+ */
+
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as frequency,
+ * open-drain/push-pull, and pull-up/down!  Just the basics are defined for most
+ * pins in this file.
+ */
+
+/* ADC */
+
+#define GPIO_ADC1_IN1       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN2       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN3       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN4       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN3)
+#undef GPIO_ADC1_IN5
+#define GPIO_ADC1_IN6       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC1_IN7       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC1_IN8       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC1_IN9       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+#undef GPIO_ADC1_IN10
+#define GPIO_ADC1_IN11      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC1_IN12      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN13      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN13)
+
+#define GPIO_ADC2_IN1       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC2_IN2       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC2_IN3       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC2_IN4       (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC2_IN5       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC2_IN6       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC2_IN7       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC2_IN8       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC2_IN9       (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN3)
+#undef GPIO_ADC2_IN10
+#define GPIO_ADC2_IN11      (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ADC2_IN12      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_ADC2_IN13      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_ADC2_IN14      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_ADC2_IN15      (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN15)
+
+/* CAN */
+
+#define GPIO_CAN_RX_1       (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_CAN_RX_2       (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
+#undef GPIO_CAN_RX_3
+#define GPIO_CAN_TX_1       (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_CAN_TX_2       (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
+#undef GPIO_CAN_TX_3
+
+
+/* Comparator Outputs */
+
+#define GPIO_COMP2_OUT_1    (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_COMP2_OUT_2    (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_COMP2_OUT_3    (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_COMP4_OUT      (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_COMP6_OUT_1    (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_COMP6_OUT_2    (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN6)
+
+/* Comparator Inputs non inverting*/
+
+#define GPIO_COMP2_INP     (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_COMP4_INP     (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_COMP6_INP     (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN11)
+
+/* Comparator Inputs inverting*/
+
+#define GPIO_COMP2_INM      (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_COMP4_INM_1    (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_COMP4_INM_2    (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_COMP6_INM_1    (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_COMP6_INM_2    (GPIO_ALT|GPIO_AF8|GPIO_PORTB|GPIO_PIN15)
+
+
+/* DAC -" Once the DAC channelx is enabled, the corresponding GPIO pin
+ * (PA4 or PA5) is automatically connected to the analog converter output
+ * (DACy_OUTx). In order to avoid parasitic consumption, the PA4 or PA5 pin
+ * should first be configured to analog (AIN)".
+ */
+
+#define GPIO_DAC1_OUT1      (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC1_OUT2      (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_DAC2_OUT1      (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+
+/* I2C */
+
+#define GPIO_I2C1_SCL_1     (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_I2C1_SCL_2     (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_I2C1_SCL_3     (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_I2C1_SDA_1     (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_I2C1_SDA_2     (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C1_SDA_3     (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C1_SMBA      (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+
+/* IR */
+
+#define GPIO_IR_OUT_1       (GPIO_ALT|GPIO_AF5|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_IR_OUT_2       (GPIO_ALT|GPIO_AF6|GPIO_PORTB|GPIO_PIN9)
+
+/* JTAG/SWD */
+
+#define GPIO_JTDI           (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_JTDO_TRACES_WO (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_NJTRST         (GPIO_ALT|GPIO_AF0|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SWCLK_JTCK     (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_SWDIO_JTMS     (GPIO_ALT|GPIO_AF0|GPIO_PORTA|GPIO_PIN13)
+
+/* MCO */
+
+#define GPIO_MCO       	     (GPIO_ALT|GPIO_AF0|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8)
+
+/* SPI */
+
+#define GPIO_SPI1_MISO_1    (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_SPI1_MISO_2    (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SPI1_MOSI_1    (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_SPI1_MOSI_2    (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_SPI1_NSS_1     (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_SPI1_NSS_2     (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_SPI1_SCK_1     (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_SPI1_SCK_2     (GPIO_ALT|GPIO_AF5|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
+
+/* Timers */
+
+#define GPIO_TIM1_BKIN_1    (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM1_BKIN_2    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_TIM1_BKIN_3    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM1_BKIN_4    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_TIM1_BKIN2_1   (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM1_BKIN2_2   (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_TIM1_CH1IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_TIM1_CH1OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_TIM1_CH1IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_TIM1_CH1OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_TIM1_CH1N_1    (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_TIM1_CH1N_2    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM1_CH1N_3    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM1_CH1N_4    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_TIM1_CH2IN     (GPIO_ALT|GPIO_FLOAT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM1_CH2OUT    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM1_CH2N_1    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM1_CH2N_2    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM1_CH2N_3    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM1_CH3IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM1_CH3OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM1_CH3IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_TIM1_CH3OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_TIM1_CH3N_1    (GPIO_ALT|GPIO_AF4|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM1_CH3N_2    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM1_CH3N_3    (GPIO_ALT|GPIO_AF6|GPIO_SPEED_50MHz|GPIO_PORTF|GPIO_PIN0)
+#define GPIO_TIM1_CH4IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM1_CH4OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_TIM1_CH4IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_TIM1_CH4OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_TIM1_ETR_1     (GPIO_ALT|GPIO_FLOAT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM1_ETR_2     (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN4)
+
+#define GPIO_TIM2_CH1_ETR_1 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM2_CH1_ETR_2 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TIM2_CH1_ETR_3 (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_TIM2_CH2IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM2_CH2OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM2_CH2IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_TIM2_CH2OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_TIM2_CH3IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM2_CH3OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM2_CH3IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM2_CH3OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM2_CH3IN_3   (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_TIM2_CH3OUT_3  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_TIM2_CH4IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM2_CH4OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM2_CH4IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM2_CH4OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM2_CH4IN_3   (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_TIM2_CH4OUT_3  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11)
+
+#define GPIO_TIM3_CH1IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM3_CH1OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM3_CH1IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM3_CH1OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM3_CH1IN_3   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_TIM3_CH1OUT_3  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_TIM3_CH2IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_TIM3_CH2OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_TIM3_CH2IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM3_CH2OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM3_CH2IN_3   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM3_CH2OUT_3  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM3_CH2IN_4   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_TIM3_CH2OUT_4  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_TIM3_CH3IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM3_CH3OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM3_CH3IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_TIM3_CH3OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_TIM3_CH4IN_1   (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM3_CH4OUT_1  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM3_CH4IN_2   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM3_CH4OUT_2  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TIM3_CH4IN_3   (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_TIM3_CH4OUT_3  (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_TIM3_ETR_1     (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_TIM3_ETR_2     (GPIO_ALT|GPIO_FLOAT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN2)
+
+#define GPIO_TIM15_BKIN     (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM15_CH1IN_1  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM15_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TIM15_CH1IN_2  (GPIO_ALT|GPIO_FLOAT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM15_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM15_CH1N_1   (GPIO_ALT|GPIO_AF2|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM15_CH1N_2   (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM15_CH2IN_1  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM15_CH2OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_TIM15_CH2IN_2  (GPIO_ALT|GPIO_FLOAT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM15_CH2OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
+
+#define GPIO_TIM16_BKIN     (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM16_CH1IN_1  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM16_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_TIM16_CH1IN_2  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM16_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM16_CH1IN_3  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM16_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM16_CH1IN_4  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM16_CH1OUT_4 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_TIM16_CH1N_1   (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_TIM16_CH1N_2   (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6)
+
+#define GPIO_TIM17_BKIN_1   (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TIM17_BKIN_2   (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM17_CH1IN_1  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM17_CH1OUT_1 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM17_CH1IN_2  (GPIO_ALT|GPIO_FLOAT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM17_CH1OUT_2 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM17_CH1IN_3  (GPIO_ALT|GPIO_FLOAT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM17_CH1OUT_3 (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_TIM17_CH1N     (GPIO_ALT|GPIO_AF1|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7)
+
+/* HRTIM */
+
+#define GPIO_HRTIM1_SCOUT_1  (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_HRTIM1_SCOUT_2  (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_HRTIM1_SCIN_1   (GPIO_ALT|GPIO_AF11|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_HRTIM1_SCIN_2   (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_HRTIM1_CHA1     (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_HRTIM1_CHA2     (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_HRTIM1_CHB1     (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_HRTIM1_CHB2     (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_HRTIM1_CHC1     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_HRTIM1_CHC2     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_HRTIM1_CHD1     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_HRTIM1_CHD2     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_HRTIM1_CHE1     (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_HRTIM1_CHE2     (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_HRTIM1_FLT1     (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_HRTIM1_FLT2     (GPIO_ALT|GPIO_AF13|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_HRTIM1_FLT3     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_HRTIM1_FLT4     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_HRTIM1_FLT5     (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_HRTIM1_EEV1     (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN12)
+#define GPIO_HRTIM1_EEV2     (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_HRTIM1_EEV3     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_HRTIM1_EEV4     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_HRTIM1_EEV5     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_HRTIM1_EEV6     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_HRTIM1_EEV7     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_HRTIM1_EEV8     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_HRTIM1_EEV9     (GPIO_ALT|GPIO_AF13|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_HRTIM1_EEV10    (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN6)
+
+/* OPAMP */
+
+#define GPIO_OPAMP2_DIG      (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_OPAMP2_VINM_1   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_OPAMP2_VINM_2   (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_OPAMP2_VOUT     (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_OPAMP2_VINP_1   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_OPAMP2_VINP_2   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP2_VINP_3   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+
+/* TSC */
+
+#define GPIO_TSC_G1_IO1     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TSC_G1_IO2     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TSC_G1_IO3     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TSC_G1_IO4     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TSC_G2_IO1     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_TSC_G2_IO2     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_TSC_G2_IO3     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TSC_G2_IO4     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TSC_G3_IO1     (GPIO_ALT|GPIO_AF3|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_TSC_G3_IO2     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TSC_G3_IO3     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_TSC_G3_IO4     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_TSC_G4_IO1     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TSC_G4_IO2     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TSC_G4_IO3     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_TSC_G4_IO4     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_TSC_G5_IO1     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_TSC_G5_IO2     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_TSC_G5_IO3     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_TSC_G5_IO4     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TSC_G6_IO1     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_TSC_G6_IO2     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_TSC_G6_IO3     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_TSC_G6_IO4     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_TSC_SYNC_1     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_TSC_SYNC_2     (GPIO_ALT|GPIO_AF3|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_TSC_SYNC_3     (GPIO_ALT|GPIO_AF3|GPIO_PORTB|GPIO_PIN8)
+
+/* USARTs/UARTs */
+
+#define GPIO_USART1_CK      (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_USART1_CTS     (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_USART1_RTS     (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_USART1_RX_1    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_USART1_RX_2    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_USART1_RX_3    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_USART1_TX_1    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_USART1_TX_2    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_USART1_TX_3    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN4)
+
+#define GPIO_USART2_CK_1    (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_USART2_CK_2    (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_USART2_CTS     (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_USART2_RTS     (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_USART2_RX_1    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_USART2_RX_2    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_USART2_RX_3    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_USART2_TX_1    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_TX_2    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_USART2_TX_3    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
+
+#define GPIO_USART3_CK_1    (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_USART3_CK_2    (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
+#define GPIO_USART3_CTS_1   (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_USART3_CTS_2   (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_USART3_RTS     (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_USART3_RX_1    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_USART3_RX_2    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_USART3_RX_3    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_USART3_TX_1    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_USART3_TX_2    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_USART3_TX_3    (GPIO_ALT|GPIO_PUSHPULL|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN9)
+
+/* Event Outputs */
+
+#define GPIO_PA0_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_PA0_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_PA0_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_PA0_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_PA1_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_PA2_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_PA3_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_PA4_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_PA5_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_PA6_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_PA7_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_PA8_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_PA9_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_PA10_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_PA11_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN11)
+#define GPIO_PA12_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN12)
+#define GPIO_PA13_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN13)
+#define GPIO_PA14_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN14)
+#define GPIO_PA15_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTA|GPIO_PIN15)
+
+#define GPIO_PB0_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_PB1_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_PB2_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN2)
+#define GPIO_PB3_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_PB4_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_PB5_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_PB6_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_PB7_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_PB8_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_PB9_EVENT_OUT  (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_PB10_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_PB11_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_PB12_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_PB13_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_PB14_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_PB15_EVENT_OUT (GPIO_ALT|GPIO_AF15|GPIO_PORTB|GPIO_PIN15)
+
+#define GPIO_PC0_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_PC1_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_PC2_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_PC3_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_PC4_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_PC5_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_PC6_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_PC7_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_PC8_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_PC9_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_PC10_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_PC11_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_PC12_EVENT_OUT (GPIO_ALT|GPIO_AF1|GPIO_PORTC|GPIO_PIN12)
+
+#define GPIO_PD2_EVENT_OUT  (GPIO_ALT|GPIO_AF1|GPIO_PORTD|GPIO_PIN2)
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_PINMAP_H */

arch/arm/src/stm32/chip/stm32f33xxx_rcc.h

@@ -0,0 +1,361 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f33xx_rcc.h
+ * For STM32F33xx advanced ARM-based 32-bit MCUs
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_RCC_CR_OFFSET         0x0000  /* Clock control register */
+#define STM32_RCC_CFGR_OFFSET       0x0004  /* Clock configuration register */
+#define STM32_RCC_CIR_OFFSET        0x0008  /* Clock interrupt register */
+#define STM32_RCC_APB2RSTR_OFFSET   0x000c  /* APB2 Peripheral reset register */
+#define STM32_RCC_APB1RSTR_OFFSET   0x0010  /* APB1 Peripheral reset register */
+#define STM32_RCC_AHBENR_OFFSET     0x0014  /* AHB Peripheral Clock enable register */
+#define STM32_RCC_APB2ENR_OFFSET    0x0018  /* APB2 Peripheral Clock enable register */
+#define STM32_RCC_APB1ENR_OFFSET    0x001c  /* APB1 Peripheral Clock enable register */
+#define STM32_RCC_BDCR_OFFSET       0x0020  /* Backup domain control register */
+#define STM32_RCC_CSR_OFFSET        0x0024  /* Control/status register */
+#define STM32_RCC_AHBRSTR_OFFSET    0x0028  /* AHB Reset register */
+#define STM32_RCC_CFGR2_OFFSET      0x002c  /* Clock configuration register 2 */
+#define STM32_RCC_CFGR3_OFFSET      0x0030  /* Clock configuration register 3 */
+
+/* Register Addresses ***************************************************************/
+
+#define STM32_RCC_CR                (STM32_RCC_BASE+STM32_RCC_CR_OFFSET)
+#define STM32_RCC_CFGR              (STM32_RCC_BASE+STM32_RCC_CFGR_OFFSET)
+#define STM32_RCC_CIR               (STM32_RCC_BASE+STM32_RCC_CIR_OFFSET)
+#define STM32_RCC_APB2RSTR          (STM32_RCC_BASE+STM32_RCC_APB2RSTR_OFFSET)
+#define STM32_RCC_APB1RSTR          (STM32_RCC_BASE+STM32_RCC_APB1RSTR_OFFSET)
+#define STM32_RCC_AHBENR            (STM32_RCC_BASE+STM32_RCC_AHBENR_OFFSET)
+#define STM32_RCC_APB2ENR           (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
+#define STM32_RCC_APB1ENR           (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
+#define STM32_RCC_BDCR              (STM32_RCC_BASE+STM32_RCC_BDCR_OFFSET)
+#define STM32_RCC_CSR               (STM32_RCC_BASE+STM32_RCC_CSR_OFFSET)
+#define STM32_RCC_AHBRSTR           (STM32_RCC_BASE+STM32_RCC_AHBRSTR_OFFSET)
+#define STM32_RCC_CFGR2             (STM32_RCC_BASE+STM32_RCC_CFGR2_OFFSET)
+#define STM32_RCC_CFGR3             (STM32_RCC_BASE+STM32_RCC_CFGR3_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Clock control register */
+
+#define RCC_CR_HSION                (1 << 0)  /* Bit 0: Internal High Speed clock enable */
+#define RCC_CR_HSIRDY               (1 << 1)  /* Bit 1: Internal High Speed clock ready flag */
+#define RCC_CR_HSITRIM_SHIFT        (3)       /* Bits 7-3: Internal High Speed clock trimming */
+#define RCC_CR_HSITRIM_MASK         (0x1f << RCC_CR_HSITRIM_SHIFT)
+#define RCC_CR_HSICAL_SHIFT         (8)       /* Bits 15-8: Internal High Speed clock Calibration */
+#define RCC_CR_HSICAL_MASK          (0xff << RCC_CR_HSICAL_SHIFT)
+#define RCC_CR_HSEON                (1 << 16) /* Bit 16: External High Speed clock enable */
+#define RCC_CR_HSERDY               (1 << 17) /* Bit 17: External High Speed clock ready flag */
+#define RCC_CR_HSEBYP               (1 << 18) /* Bit 18: External High Speed clock Bypass */
+#define RCC_CR_CSSON                (1 << 19) /* Bit 19: Clock Security System enable */
+#define RCC_CR_PLLON                (1 << 24) /* Bit 24: PLL enable */
+#define RCC_CR_PLLRDY               (1 << 25) /* Bit 25: PLL clock ready flag */
+
+/* Clock configuration register */
+
+#define RCC_CFGR_SW_SHIFT           (0)       /* Bits 1-0: System clock Switch */
+#define RCC_CFGR_SW_MASK            (3 << RCC_CFGR_SW_SHIFT)
+#  define RCC_CFGR_SW_HSI           (0 << RCC_CFGR_SW_SHIFT) /* 00: HSI selected as system clock */
+#  define RCC_CFGR_SW_HSE           (1 << RCC_CFGR_SW_SHIFT) /* 01: HSE selected as system clock */
+#  define RCC_CFGR_SW_PLL           (2 << RCC_CFGR_SW_SHIFT) /* 10: PLL selected as system clock */
+#define RCC_CFGR_SWS_SHIFT          (2)       /* Bits 3-2: System Clock Switch Status */
+#define RCC_CFGR_SWS_MASK           (3 << RCC_CFGR_SWS_SHIFT)
+#  define RCC_CFGR_SWS_HSI          (0 << RCC_CFGR_SWS_SHIFT) /* 00: HSI oscillator used as system clock */
+#  define RCC_CFGR_SWS_HSE          (1 << RCC_CFGR_SWS_SHIFT) /* 01: HSE oscillator used as system clock */
+#  define RCC_CFGR_SWS_PLL          (2 << RCC_CFGR_SWS_SHIFT) /* 10: PLL used as system clock */
+#define RCC_CFGR_HPRE_SHIFT         (4)       /* Bits 7-4: AHB prescaler */
+#define RCC_CFGR_HPRE_MASK          (0x0f << RCC_CFGR_HPRE_SHIFT)
+#  define RCC_CFGR_HPRE_SYSCLK      (0 << RCC_CFGR_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
+#  define RCC_CFGR_HPRE_SYSCLKd2    (8 << RCC_CFGR_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+#  define RCC_CFGR_HPRE_SYSCLKd4    (9 << RCC_CFGR_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+#  define RCC_CFGR_HPRE_SYSCLKd8    (10 << RCC_CFGR_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+#  define RCC_CFGR_HPRE_SYSCLKd16   (11 << RCC_CFGR_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+#  define RCC_CFGR_HPRE_SYSCLKd64   (12 << RCC_CFGR_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+#  define RCC_CFGR_HPRE_SYSCLKd128  (13 << RCC_CFGR_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+#  define RCC_CFGR_HPRE_SYSCLKd256  (14 << RCC_CFGR_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+#  define RCC_CFGR_HPRE_SYSCLKd512  (15 << RCC_CFGR_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+#define RCC_CFGR_PPRE1_SHIFT        (8)       /* Bits 10-8: APB Low speed prescaler (APB1) */
+#define RCC_CFGR_PPRE1_MASK         (7 << RCC_CFGR_PPRE1_SHIFT)
+#  define RCC_CFGR_PPRE1_HCLK       (0 << RCC_CFGR_PPRE1_SHIFT) /* 0xx: HCLK not divided */
+#  define RCC_CFGR_PPRE1_HCLKd2     (4 << RCC_CFGR_PPRE1_SHIFT) /* 100: HCLK divided by 2 */
+#  define RCC_CFGR_PPRE1_HCLKd4     (5 << RCC_CFGR_PPRE1_SHIFT) /* 101: HCLK divided by 4 */
+#  define RCC_CFGR_PPRE1_HCLKd8     (6 << RCC_CFGR_PPRE1_SHIFT) /* 110: HCLK divided by 8 */
+#  define RCC_CFGR_PPRE1_HCLKd16    (7 << RCC_CFGR_PPRE1_SHIFT) /* 111: HCLK divided by 16 */
+#define RCC_CFGR_PPRE2_SHIFT        (11)      /* Bits 13-11: APB High speed prescaler (APB2) */
+#define RCC_CFGR_PPRE2_MASK         (7 << RCC_CFGR_PPRE2_SHIFT)
+#  define RCC_CFGR_PPRE2_HCLK       (0 << RCC_CFGR_PPRE2_SHIFT) /* 0xx: HCLK not divided */
+#  define RCC_CFGR_PPRE2_HCLKd2     (4 << RCC_CFGR_PPRE2_SHIFT) /* 100: HCLK divided by 2 */
+#  define RCC_CFGR_PPRE2_HCLKd4     (5 << RCC_CFGR_PPRE2_SHIFT) /* 101: HCLK divided by 4 */
+#  define RCC_CFGR_PPRE2_HCLKd8     (6 << RCC_CFGR_PPRE2_SHIFT) /* 110: HCLK divided by 8 */
+#  define RCC_CFGR_PPRE2_HCLKd16    (7 << RCC_CFGR_PPRE2_SHIFT) /* 111: HCLK divided by 16 */
+#define RCC_CFGR_PLLSRC             (1 << 16) /* Bit 16: PLL entry clock source */
+#define RCC_CFGR_PLLXTPRE           (1 << 17) /* Bit 17: HSE divider for PLL entry */
+#define RCC_CFGR_PLLMUL_SHIFT       (18)      /* Bits 21-18: PLL Multiplication Factor */
+#define RCC_CFGR_PLLMUL_MASK        (0x0f << RCC_CFGR_PLLMUL_SHIFT)
+#  define RCC_CFGR_PLLMUL_CLKx2     (0 << RCC_CFGR_PLLMUL_SHIFT)  /* 0000: PLL input clock x 2 */
+#  define RCC_CFGR_PLLMUL_CLKx3     (1 << RCC_CFGR_PLLMUL_SHIFT)  /* 0001: PLL input clock x 3 */
+#  define RCC_CFGR_PLLMUL_CLKx4     (2 << RCC_CFGR_PLLMUL_SHIFT)  /* 0010: PLL input clock x 4 */
+#  define RCC_CFGR_PLLMUL_CLKx5     (3 << RCC_CFGR_PLLMUL_SHIFT)  /* 0011: PLL input clock x 5 */
+#  define RCC_CFGR_PLLMUL_CLKx6     (4 << RCC_CFGR_PLLMUL_SHIFT)  /* 0100: PLL input clock x 6 */
+#  define RCC_CFGR_PLLMUL_CLKx7     (5 << RCC_CFGR_PLLMUL_SHIFT)  /* 0101: PLL input clock x 7 */
+#  define RCC_CFGR_PLLMUL_CLKx8     (6 << RCC_CFGR_PLLMUL_SHIFT)  /* 0110: PLL input clock x 8 */
+#  define RCC_CFGR_PLLMUL_CLKx9     (7 << RCC_CFGR_PLLMUL_SHIFT)  /* 0111: PLL input clock x 9 */
+#  define RCC_CFGR_PLLMUL_CLKx10    (8 << RCC_CFGR_PLLMUL_SHIFT)  /* 1000: PLL input clock x 10 */
+#  define RCC_CFGR_PLLMUL_CLKx11    (9 << RCC_CFGR_PLLMUL_SHIFT)  /* 1001: PLL input clock x 11 */
+#  define RCC_CFGR_PLLMUL_CLKx12    (10 << RCC_CFGR_PLLMUL_SHIFT) /* 1010: PLL input clock x 12 */
+#  define RCC_CFGR_PLLMUL_CLKx13    (11 << RCC_CFGR_PLLMUL_SHIFT) /* 1011: PLL input clock x 13 */
+#  define RCC_CFGR_PLLMUL_CLKx14    (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
+#  define RCC_CFGR_PLLMUL_CLKx15    (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
+#  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
+#define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 26-24: Microcontroller Clock Output */
+#define RCC_CFGR_MCO_MASK           (3 << RCC_CFGR_MCO_SHIFT)
+#  define RCC_CFGR_MCO_DISABLED     (0 << RCC_CFGR_MCO_SHIFT)  /* 000: MCO output disabled, no clock on MCO */
+#  define RCC_CFGR_MCO_LSICLK       (2 << RCC_CFGR_MCO_SHIFT)  /* 010: LSI clock selected */
+#  define RCC_CFGR_MCO_LSECLK       (3 << RCC_CFGR_MCO_SHIFT)  /* 011: LSE clock selected */
+#  define RCC_CFGR_MCO_SYSCLK       (4 << RCC_CFGR_MCO_SHIFT)  /* 100: System clock (SYSCLK) selected */
+#  define RCC_CFGR_MCO_HSICLK       (5 << RCC_CFGR_MCO_SHIFT)  /* 101: HSI clock selected */
+#  define RCC_CFGR_MCO_HSECLK       (6 << RCC_CFGR_MCO_SHIFT)  /* 101: HSE clock selected */
+#  define RCC_CFGR_PLLCLKd2         (7 << RCC_CFGR_MCO_SHIFT)  /* 111: PLL clock divided by 2 selected */
+#define RCC_CFGR_MCOPRE_SHIFT       (28)      /* Bits 30-28: Microcontroller Clock Output */
+#define RCC_CFGR_MCOPRE_MASK        (7 << RCC_CFGR_MCOPRE_SHIFT)
+#  define RCC_CFGR_MCOPRE_MCOd1     (0 << RCC_CFGR_MCOPRE_SHIFT)  /* 000: MCO is divided by 1 */
+#  define RCC_CFGR_MCOPRE_MCOd2     (1 << RCC_CFGR_MCOPRE_SHIFT)  /* 001: MCO is divided by 2 */
+#  define RCC_CFGR_MCOPRE_MCOd4     (2 << RCC_CFGR_MCOPRE_SHIFT)  /* 010: MCO is divided by 4 */
+#  define RCC_CFGR_MCOPRE_MCOd8     (3 << RCC_CFGR_MCOPRE_SHIFT)  /* 011: MCO is divided by 8 */
+#  define RCC_CFGR_MCOPRE_MCOd16    (4 << RCC_CFGR_MCOPRE_SHIFT)  /* 100: MCO is divided by 16 */
+#  define RCC_CFGR_MCOPRE_MCOd32    (5 << RCC_CFGR_MCOPRE_SHIFT)  /* 101: MCO is divided by 32 */
+#  define RCC_CFGR_MCOPRE_MCOd64    (6 << RCC_CFGR_MCOPRE_SHIFT)  /* 110: MCO is divided by 64 */
+#  define RCC_CFGR_MCOPRE_MCOd128   (7 << RCC_CFGR_MCOPRE_SHIFT)  /* 111: MCO is divided by 128 */
+#define RCC_CFGR_PLLNODIV           (1 << 31) /* Bit 31: Do not divide PLL to MCO */
+
+/* Clock interrupt register */
+
+#define RCC_CIR_LSIRDYF             (1 << 0)  /* Bit 0: LSI Ready Interrupt flag */
+#define RCC_CIR_LSERDYF             (1 << 1)  /* Bit 1: LSE Ready Interrupt flag */
+#define RCC_CIR_HSIRDYF             (1 << 2)  /* Bit 2: HSI Ready Interrupt flag */
+#define RCC_CIR_HSERDYF             (1 << 3)  /* Bit 3: HSE Ready Interrupt flag */
+#define RCC_CIR_PLLRDYF             (1 << 4)  /* Bit 4: PLL Ready Interrupt flag */
+#define RCC_CIR_CSSF                (1 << 7)  /* Bit 7: Clock Security System Interrupt flag */
+#define RCC_CIR_LSIRDYIE            (1 << 8)  /* Bit 8: LSI Ready Interrupt Enable */
+#define RCC_CIR_LSERDYIE            (1 << 9)  /* Bit 9: LSE Ready Interrupt Enable */
+#define RCC_CIR_HSIRDYIE            (1 << 10) /* Bit 10: HSI Ready Interrupt Enable */
+#define RCC_CIR_HSERDYIE            (1 << 11) /* Bit 11: HSE Ready Interrupt Enable */
+#define RCC_CIR_PLLRDYIE            (1 << 12) /* Bit 12: PLL Ready Interrupt Enable */
+#define RCC_CIR_LSIRDYC             (1 << 16) /* Bit 16: LSI Ready Interrupt Clear */
+#define RCC_CIR_LSERDYC             (1 << 17) /* Bit 17: LSE Ready Interrupt Clear */
+#define RCC_CIR_HSIRDYC             (1 << 18) /* Bit 18: HSI Ready Interrupt Clear */
+#define RCC_CIR_HSERDYC             (1 << 19) /* Bit 19: HSE Ready Interrupt Clear */
+#define RCC_CIR_PLLRDYC             (1 << 20) /* Bit 20: PLL Ready Interrupt Clear */
+#define RCC_CIR_CSSC                (1 << 23) /* Bit 23: Clock Security System Interrupt Clear */
+
+/* APB2 Peripheral reset register */
+
+#define RCC_APB2RSTR_SYSCFGRST      (1 << 0)  /* Bit 0: SYSCFG, Comparators and operational amplifiers reset */
+#define RCC_APB2RSTR_TIM1RST        (1 << 9)  /* Bit 9: TIM1 reset */
+#define RCC_APB2RSTR_SPI1RST        (1 << 12) /* Bit 12: SPI 1 reset */
+#define RCC_APB2RSTR_USART1RST      (1 << 14) /* Bit 14: USART1 reset */
+#define RCC_APB2RSTR_TIM15RST       (1 << 16) /* Bit 16: TIM15 reset */
+#define RCC_APB2RSTR_TIM16RST       (1 << 17) /* Bit 17: TIM16 reset */
+#define RCC_APB2RSTR_TIM17RST       (1 << 18) /* Bit 18: TIM17 reset */
+#define RCC_APB2RSTR_HRTIM1RST      (1 << 26) /* Bit 29: HRTIM1 reset */
+
+/* APB1 Peripheral reset register */
+
+#define RCC_APB1RSTR_TIM2RST        (1 << 0)  /* Bit 0: Timer 2 reset */
+#define RCC_APB1RSTR_TIM3RST        (1 << 1)  /* Bit 1: Timer 3 reset */
+#define RCC_APB1RSTR_TIM6RST        (1 << 4)  /* Bit 4: Timer 6 reset */
+#define RCC_APB1RSTR_TIM7RST        (1 << 5)  /* Bit 5: Timer 7 reset */
+#define RCC_APB1RSTR_WWDGRST        (1 << 11) /* Bit 11: Window Watchdog reset */
+#define RCC_APB1RSTR_USART2RST      (1 << 17) /* Bit 17: USART 2 reset */
+#define RCC_APB1RSTR_USART3RST      (1 << 18) /* Bit 18: USART 3 reset */
+#define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
+#define RCC_APB1RSTR_CANRST         (1 << 25) /* Bit 25: CAN reset */
+#define RCC_APB1RSTR_CAN1RST        (1 << 25) /* Bit 25: CAN reset */
+#define RCC_APB1RSTR_DAC2RST        (1 << 26) /* Bit 26: DAC2 interface reset */
+#define RCC_APB1RSTR_PWRRST         (1 << 28) /* Bit 28: Power interface reset */
+#define RCC_APB1RSTR_DAC1RST        (1 << 29) /* Bit 29: DAC1 interface reset */
+
+/* AHB Peripheral Clock enable register */
+
+#define RCC_AHBENR_DMA1EN           (1 << 0)  /* Bit 0: DMA1 clock enable */
+#define RCC_AHBENR_SRAMEN           (1 << 2)  /* Bit 2: SRAM interface clock enable */
+#define RCC_AHBENR_FLITFEN          (1 << 4)  /* Bit 4: FLITF clock enable */
+#define RCC_AHBENR_CRCEN            (1 << 6)  /* Bit 6: CRC clock enable */
+#define RCC_AHBENR_IOPAEN           (1 << 17) /* Bit 17: I/O port A clock enable */
+#define RCC_AHBENR_IOPBEN           (1 << 18) /* Bit 17: I/O port B clock enable */
+#define RCC_AHBENR_IOPCEN           (1 << 19) /* Bit 17: I/O port C clock enable */
+#define RCC_AHBENR_IOPDEN           (1 << 20) /* Bit 17: I/O port D clock enable */
+#define RCC_AHBENR_IOPFEN           (1 << 22) /* Bit 17: I/O port F clock enable */
+#define RCC_AHBENR_TSCEN            (1 << 24) /* Bit 24: TSCEN: Touch sensing controller clock enable */
+#define RCC_AHBENR_ADC12EN          (1 << 28) /* Bit 28: ADC1/ADC2 clock enable */
+
+/* APB2 Peripheral Clock enable register */
+
+#define RCC_APB2ENR_SYSCFGEN        (1 << 0)  /* Bit 0: SYSCFG, Comparators and operational amplifiers clock enable */
+#define RCC_APB2ENR_TIM1EN          (1 << 11) /* Bit 11: TIM1 clock enable */
+#define RCC_APB2ENR_SPI1EN          (1 << 12) /* Bit 12: SPI 1 clock enable */
+#define RCC_APB2ENR_USART1EN        (1 << 14) /* Bit 14: USART1 clock enable */
+#define RCC_APB2ENR_TIM15EN         (1 << 16) /* Bit 16: TIM15 clock enable */
+#define RCC_APB2ENR_TIM16EN         (1 << 17) /* Bit 17: TIM16 clock enable */
+#define RCC_APB2ENR_TIM17EN         (1 << 18) /* Bit 18: TIM17 clock enable */
+#define RCC_APB2ENR_HRTIM1EN        (1 << 29) /* Bit 29: HRTIM1 clock enable */
+
+/* APB1 Peripheral Clock enable register */
+
+#define RCC_APB1ENR_TIM2EN          (1 << 0)  /* Bit 0: Timer 2 clock enable */
+#define RCC_APB1ENR_TIM3EN          (1 << 1)  /* Bit 1: Timer 3 clock enable */
+#define RCC_APB1ENR_TIM6EN          (1 << 4)  /* Bit 4: Timer 6 clock enable */
+#define RCC_APB1ENR_TIM7EN          (1 << 5)  /* Bit 5: Timer 7 clock enable */
+#define RCC_APB1ENR_WWDGEN          (1 << 11) /* Bit 11: Window Watchdog clock enable */
+#define RCC_APB1ENR_USART2EN        (1 << 17) /* Bit 17: USART 2 clock enable */
+#define RCC_APB1ENR_USART3EN        (1 << 18) /* Bit 18: USART 3 clock enable */
+#define RCC_APB1ENR_I2C1EN          (1 << 21) /* Bit 21: I2C 1 clock enable */
+#define RCC_APB1ENR_CANEN           (1 << 25) /* Bit 25: CAN clock enable */
+#define RCC_APB1ENR_DAC2EN          (1 << 26) /* Bit 26: DAC1 interface clock enable */
+#define RCC_APB1ENR_PWREN           (1 << 28) /* Bit 28: Power interface clock enable */
+#define RCC_APB1ENR_DAC1EN          (1 << 29) /* Bit 29: DAC1 interface clock enable */
+
+/* Backup domain control register */
+
+#define RCC_BDCR_LSEON              (1 << 0)  /* Bit 0: External Low Speed oscillator enable */
+#define RCC_BDCR_LSERDY             (1 << 1)  /* Bit 1: External Low Speed oscillator Ready */
+#define RCC_BDCR_LSEBYP             (1 << 2)  /* Bit 2: External Low Speed oscillator Bypass */
+#define RCC_BDCR_LSEDRV_SHIFT       (3)       /* Bits 4:3: LSE oscillator drive capability */
+#define RCC_BDCR_LSEDRV_MASK        (3 << RCC_BDCR_LSEDRV_SHIFT)
+#  define RCC_BDCR_LSEDRV_LOW       (0 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' lower driving capability */
+#  define RCC_BDCR_LSEDRV_MEDLOW    (1 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' medium low driving capability */
+#  define RCC_BDCR_LSEDRV_MEDHIGH   (2 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' medium high driving capability */
+#  define RCC_BDCR_LSEDRV_HIGH      (3 << RCC_BDCR_LSEDRV_SHIFT) /* 'Xtal mode' higher driving capability */
+#define RCC_BDCR_RTCSEL_SHIFT       (8)       /* Bits 9:8: RTC clock source selection */
+#define RCC_BDCR_RTCSEL_MASK        (3 << RCC_BDCR_RTCSEL_SHIFT)
+#  define RCC_BDCR_RTCSEL_NOCLK     (0 << RCC_BDCR_RTCSEL_SHIFT) /* 00: No clock */
+#  define RCC_BDCR_RTCSEL_LSE       (1 << RCC_BDCR_RTCSEL_SHIFT) /* 01: LSE oscillator clock used as RTC clock */
+#  define RCC_BDCR_RTCSEL_LSI       (2 << RCC_BDCR_RTCSEL_SHIFT) /* 10: LSI oscillator clock used as RTC clock */
+#  define RCC_BDCR_RTCSEL_HSE       (3 << RCC_BDCR_RTCSEL_SHIFT) /* 11: HSE oscillator clock divided by 128 used as RTC clock */
+#define RCC_BDCR_RTCEN              (1 << 15) /* Bit 15: RTC clock enable */
+#define RCC_BDCR_BDRST              (1 << 16) /* Bit 16: Backup domain software reset */
+
+/* Control/status register */
+
+#define RCC_CSR_LSION               (1 << 0)  /* Bit 0: Internal Low Speed oscillator enable */
+#define RCC_CSR_LSIRDY              (1 << 1)  /* Bit 1: Internal Low Speed oscillator Ready */
+#define RCC_CSR_RMVF                (1 << 24) /* Bit 24: Remove reset flag */
+#define RCC_CSR_OBLRSTF             (1 << 25) /* Bit 25: Option byte loader reset flag */
+#define RCC_CSR_PINRSTF             (1 << 26) /* Bit 26: PIN reset flag */
+#define RCC_CSR_PORRSTF             (1 << 27) /* Bit 27: POR/PDR reset flag */
+#define RCC_CSR_SFTRSTF             (1 << 28) /* Bit 28: Software Reset flag */
+#define RCC_CSR_IWDGRSTF            (1 << 29) /* Bit 29: Independent Watchdog reset flag */
+#define RCC_CSR_WWDGRSTF            (1 << 30) /* Bit 30: Window watchdog reset flag */
+#define RCC_CSR_LPWRRSTF            (1 << 31) /* Bit 31: Low-Power reset flag */
+
+/* AHB peripheral clock reset register (RCC_AHBRSTR) */
+
+#define RCC_AHBRSTR_IOPARST         (1 << 17) /* Bit 17: I/O port A reset */
+#define RCC_AHBRSTR_IOPBRST         (1 << 18) /* Bit 18: I/O port B reset */
+#define RCC_AHBRSTR_IOPCRST         (1 << 29) /* Bit 19: I/O port C reset */
+#define RCC_AHBRSTR_IOPDRST         (1 << 20) /* Bit 20: I/O port D reset */
+#define RCC_AHBRSTR_IOPFRST         (1 << 22) /* Bit 22: I/O port F reset */
+#define RCC_AHBRSTR_TSCRST          (1 << 24) /* Bit 24: Touch sensing controller reset */
+#define RCC_AHBRSTR_ADC12RST        (1 << 28) /* Bit 24: ADC1/ADC2 reset */
+
+/* Clock configuration register 2 */
+
+#define RCC_CFGR2_PREDIV_SHIFT      (0)       /* Bits 0-3: PREDIV division factor */
+#define RCC_CFGR2_PREDIV_MASK       (15 << RCC_CFGR2_PREDIV_SHIFT)
+#  define RCC_CFGR2_PREDIVd1        (0 << RCC_CFGR2_PREDIV_SHIFT)  /* 0000: HSE input to PLL not divided */
+#  define RCC_CFGR2_PREDIVd2        (1 << RCC_CFGR2_PREDIV_SHIFT)  /* 0001: HSE input to PLL divided by 2 */
+#  define RCC_CFGR2_PREDIVd3        (2 << RCC_CFGR2_PREDIV_SHIFT)  /* 0010: HSE input to PLL divided by 3 */
+#  define RCC_CFGR2_PREDIVd4        (3 << RCC_CFGR2_PREDIV_SHIFT)  /* 0011: HSE input to PLL divided by 4 */
+#  define RCC_CFGR2_PREDIVd5        (4 << RCC_CFGR2_PREDIV_SHIFT)  /* 0100: HSE input to PLL divided by 5 */
+#  define RCC_CFGR2_PREDIVd6        (5 << RCC_CFGR2_PREDIV_SHIFT)  /* 0101: HSE input to PLL divided by 6 */
+#  define RCC_CFGR2_PREDIVd7        (6 << RCC_CFGR2_PREDIV_SHIFT)  /* 0110: HSE input to PLL divided by 7 */
+#  define RCC_CFGR2_PREDIVd8        (7 << RCC_CFGR2_PREDIV_SHIFT)  /* 0111: HSE input to PLL divided by 8 */
+#  define RCC_CFGR2_PREDIVd9        (8 << RCC_CFGR2_PREDIV_SHIFT)  /* 1000: HSE input to PLL divided by 9 */
+#  define RCC_CFGR2_PREDIVd10       (9 << RCC_CFGR2_PREDIV_SHIFT)  /* 1001: HSE input to PLL divided by 10 */
+#  define RCC_CFGR2_PREDIVd11       (10 << RCC_CFGR2_PREDIV_SHIFT) /* 1010: HSE input to PLL divided by 11 */
+#  define RCC_CFGR2_PREDIVd12       (11 << RCC_CFGR2_PREDIV_SHIFT) /* 1011: HSE input to PLL divided by 12 */
+#  define RCC_CFGR2_PREDIVd13       (12 << RCC_CFGR2_PREDIV_SHIFT) /* 1100: HSE input to PLL divided by 13 */
+#  define RCC_CFGR2_PREDIVd14       (13 << RCC_CFGR2_PREDIV_SHIFT) /* 1101: HSE input to PLL divided by 14 */
+#  define RCC_CFGR2_PREDIVd15       (14 << RCC_CFGR2_PREDIV_SHIFT) /* 1110: HSE input to PLL divided by 15 */
+#  define RCC_CFGR2_PREDIVd16       (15 << RCC_CFGR2_PREDIV_SHIFT) /* 1111: HSE input to PLL divided by 16 */
+#define RCC_CFGR2_ADC12PRES_SHIFT   (4)       /* Bits 4-8: ADC12PRES division factor */
+#define RCC_CFGR2_ADC12PRES_MASK    (32 << RCC_CFGR2_ADC12PRES_SHIFT)
+#  define RCC_CFGR2_ADC12DISABLED   (0 << RCC_CFGR2_ADC12PRES_SHIFT)  /* 00000: ADC12 clock disabled  */
+#  define RCC_CFGR2_ADC12PRESd1     (16 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10000: PLL clock divided by 1 */
+#  define RCC_CFGR2_ADC12PRESd2     (17 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10001: PLL clock divided by 2 */
+#  define RCC_CFGR2_ADC12PRESd4     (18 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10010: PLL clock divided by 4 */
+#  define RCC_CFGR2_ADC12PRESd6     (19 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10011: PLL clock divided by 6 */
+#  define RCC_CFGR2_ADC12PRESd8     (20 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10100: PLL clock divided by 8 */
+#  define RCC_CFGR2_ADC12PRESd10    (21 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10101: PLL clock divided by 10 */
+#  define RCC_CFGR2_ADC12PRESd12    (22 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10110: PLL clock divided by 12 */
+#  define RCC_CFGR2_ADC12PRESd16    (23 << RCC_CFGR2_ADC12PRES_SHIFT) /* 10111: PLL clock divided by 16 */
+#  define RCC_CFGR2_ADC12PRESd32    (24 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11000: PLL clock divided by 32 */
+#  define RCC_CFGR2_ADC12PRESd64    (25 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11001: PLL clock divided by 64 */
+#  define RCC_CFGR2_ADC12PRESd128   (26 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11010: PLL clock divided by 128 */
+#  define RCC_CFGR2_ADC12PRESd256   (27 << RCC_CFGR2_ADC12PRES_SHIFT) /* 11011: PLL clock divided by 256 */
+
+/* Clock configuration register 3 */
+
+#define RCC_CFGR3_USART1SW_SHIFT    (0)       /* Bits 0-1: USART1 clock source selection */
+#define RCC_CFGR3_USART1SW_MASK     (3 << RCC_CFGR3_USART1SW_SHIFT)
+#  define RCC_CFGR3_USART1SW_PCLK   (0 << RCC_CFGR3_USART1SW_SHIFT) /* PCLK */
+#  define RCC_CFGR3_USART1SW_SYSCLK (1 << RCC_CFGR3_USART1SW_SHIFT) /* System clock (SYSCLK) */
+#  define RCC_CFGR3_USART1SW_LSE    (2 << RCC_CFGR3_USART1SW_SHIFT) /* LSE clock */
+#  define RCC_CFGR3_USART1SW_HSI    (0 << RCC_CFGR3_USART1SW_SHIFT) /* HSI clock */
+#define RCC_CFGR3_I2C1SW            (1 << 4)  /* Bit 4: I2C1 clock source selection */
+#define RCC_CFGR3_TIM1SW            (1 << 8)  /* Bit 8: TIM1 clock source selection */
+#define RCC_CFGR3_HRTIM1SW          (1 << 9)  /* Bit 9: HRTIM clock source selection */
+#define RCC_CFGR3_USART2SW_SHIFT    (16)      /* Bits 16-17: USART2 clock source selection */
+#define RCC_CFGR3_USART2SW_MASK     (3 << RCC_CFGR3_USART2SW_SHIFT)
+#  define RCC_CFGR3_USART2SW_PCLK   (0 << RCC_CFGR3_USART2SW_SHIFT) /* PCLK */
+#  define RCC_CFGR3_USART2SW_SYSCLK (1 << RCC_CFGR3_USART2SW_SHIFT) /* System clock (SYSCLK) */
+#  define RCC_CFGR3_USART2SW_LSE    (2 << RCC_CFGR3_USART2SW_SHIFT) /* LSE clock */
+#  define RCC_CFGR3_USART2SW_HSI    (0 << RCC_CFGR3_USART2SW_SHIFT) /* HSI clock */
+#define RCC_CFGR3_USART3SW_SHIFT    (18)      /* Bits 18-19: USART3 clock source selection */
+#define RCC_CFGR3_USART3SW_MASK     (3 << RCC_CFGR3_USART3SW_SHIFT)
+#  define RCC_CFGR3_USART3SW_PCLK   (0 << RCC_CFGR3_USART3SW_SHIFT) /* PCLK */
+#  define RCC_CFGR3_USART3SW_SYSCLK (1 << RCC_CFGR3_USART3SW_SHIFT) /* System clock (SYSCLK) */
+#  define RCC_CFGR3_USART3SW_LSE    (2 << RCC_CFGR3_USART3SW_SHIFT) /* LSE clock */
+#  define RCC_CFGR3_USART3SW_HSI    (0 << RCC_CFGR3_USART3SW_SHIFT) /* HSI clock */
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_RCC_H */

arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h

@@ -0,0 +1,182 @@
+/****************************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f33xxx_syscfg.h
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+#ifdef CONFIG_STM32_STM32F33XX
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* Register Offsets *********************************************************************************/
+
+#define STM32_SYSCFG_CFGR1_OFFSET      0x0000 /* SYSCFG configuration register 1 */
+#define STM32_SYSCFG_RCR_OFFSET        0x0004 /* SYSCFG CCM SRAM protection register */
+
+#define STM32_SYSCFG_EXTICR_OFFSET(p)  (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
+#define STM32_SYSCFG_EXTICR1_OFFSET    0x0008 /* SYSCFG external interrupt configuration register 1 */
+#define STM32_SYSCFG_EXTICR2_OFFSET    0x000c /* SYSCFG external interrupt configuration register 2 */
+#define STM32_SYSCFG_EXTICR3_OFFSET    0x0010 /* SYSCFG external interrupt configuration register 3 */
+#define STM32_SYSCFG_EXTICR4_OFFSET    0x0014 /* SYSCFG external interrupt configuration register 4 */
+
+#define STM32_SYSCFG_CFGR2_OFFSET      0x0018 /* SYSCFG configuration register 2 */
+#define STM32_SYSCFG_CFGR3_OFFSET      0x0050 /* SYSCFG configuration register 3 */
+
+/* Register Addresses *******************************************************************************/
+
+#define STM32_SYSCFG_CFGR1             (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR1_OFFSET)
+#define STM32_SYSCFG_RCR               (STM32_SYSCFG_BASE+STM32_SYSCFG_RCR_OFFSET)
+
+#define STM32_SYSCFG_EXTICR(p)         (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR_OFFSET(p))
+#define STM32_SYSCFG_EXTICR1           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR1_OFFSET)
+#define STM32_SYSCFG_EXTICR2           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR2_OFFSET)
+#define STM32_SYSCFG_EXTICR3           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR3_OFFSET)
+#define STM32_SYSCFG_EXTICR4           (STM32_SYSCFG_BASE+STM32_SYSCFG_EXTICR4_OFFSET)
+
+#define STM32_SYSCFG_CFGR2             (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR2_OFFSET)
+#define STM32_SYSCFG_CFGR3             (STM32_SYSCFG_BASE+STM32_SYSCFG_CFGR3_OFFSET)
+
+/* Register Bitfield Definitions ********************************************************************/
+
+/* SYSCFG memory remap register */
+
+#define SYSCFG_CFGR1_MEMMODE_SHIFT     (0)       /* Bits 1:0 MEM_MODE: Memory mapping selection */
+#define SYSCFG_CFGR1_MEMMODE_MASK      (3 << SYSCFG_CFGR1_MEMMODE_SHIFT)
+#  define SYSCFG_CFGR1_MEMMODE_FLASH   (0 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 00: Main Flash at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_SYSTEM  (1 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 01: System Flash at 0x00000000 */
+#  define SYSCFG_CFGR1_MEMMODE_SRAM    (3 << SYSCFG_CFGR1_MEMMODE_SHIFT) /* 11: Embedded SRAM at 0x00000000 */
+#define SYSCFG_CFGR1_TIM1_ITR3RMP      (1 << 6)  /* Bit 6:  Timer 1 ITR3 selection */
+#define SYSCFG_CFGR1_DAC_TRIGRMP       (1 << 7)  /* Bit 7:  DAC trigger remap (when TSEL = 001) */
+#define SYSCFG_CFGR1_TIM16_DMARMP      (1 << 11) /* Bit 11: TIM16 DMA request remapping bit */
+#define SYSCFG_CFGR1_TIM17_DMARMP      (1 << 12) /* Bit 12: TIM17 DMA request remapping bit */
+#define SYSCFG_CFGR1_TIM6_DMARMP       (1 << 13) /* Bit 13: TIM6 DMA remap, or */
+#define SYSCFG_CFGR1_DAC1_DMARMP       (1 << 13) /* Bit 13: DAC channel DMA remap */
+#define SYSCFG_CFGR1_TIM7_DMARMP       (1 << 14) /* Bit 14: TIM7 DMA remap */
+#define SYSCFG_CFGR1_DAC2CH2_DMARMP    (1 << 14) /* Bit 14: DAC channel2 DMA remap */
+#define SYSCFG_CFGR1_DAC2CH1_DMARMP    (1 << 15) /* Bit 14: DAC channel1 DMA remap */
+#define SYSCFG_CFGR1_I2C_PBXFMP_SHIFT  (0)       /* Bits 16-19: Fast Mode Plus (FM+) driving capability */
+#define SYSCFG_CFGR1_I2C_PBXFMP_MASK   (15 << SYSCFG_CFGR1_I2C_PBXFMP_SHIFT)
+#define SYSCFG_CFGR1_I2C1_FMP          (1 << 20) /* Bit 20: I2C1 fast mode Plus driving capability */
+#define SYSCFG_CFGR1_I2C2_FMP          (1 << 21) /* Bit 21: I2C2 fast mode Plus driving capability */
+#define SYSCFG_CFGR1_ENCMODE_SHIFT     (22)       /* Bits 22-23: Encoder mode */
+#define SYSCFG_CFGR1_ENCMODE_MASK      (3 << SYSCFG_CFGR1_ENCMODE_SHIFT)
+#  define SYSCFG_CFGR1_ENCMODE_NONE    (0 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* No redirection */
+#  define SYSCFG_CFGR1_ENCMODE_TIM2    (1 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* TIM2 I2C1-2 -> TIM15 IC1/2 */
+#  define SYSCFG_CFGR1_ENCMODE_TIM3    (2 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* TIM3 I2C1-2 -> TIM15 IC1/2 */
+#  define SYSCFG_CFGR1_ENCMODE_TIM4    (3 << SYSCFG_CFGR1_ENCMODE_SHIFT) /* TIM4 I2C1-2 -> TIM15 IC1/2 */
+#define SYSCFG_CFGR1_FPUIE_SHIFT       (26)       /* Bits 26-31: Floating Point Unit interrupts enable bits */
+#define SYSCFG_CFGR1_FPUIE_MASK        (63 << SYSCFG_CFGR1_FPUIE_SHIFT)
+#  define SYSCFG_CFGR1_FPUIE_INVALIDOP (1 << SYSCFG_CFGR1_FPUIE_SHIFT)  /* Invalid operation interrupt enable */
+#  define SYSCFG_CFGR1_FPUIE_DIVZERO   (2 << SYSCFG_CFGR1_FPUIE_SHIFT)  /* Divide-by-zero interrupt enable */
+#  define SYSCFG_CFGR1_FPUIE_UNDERFLOW (4 << SYSCFG_CFGR1_FPUIE_SHIFT)  /* Underflow interrupt enable */
+#  define SYSCFG_CFGR1_FPUIE_OVERFLOW  (8 << SYSCFG_CFGR1_FPUIE_SHIFT)  /* Overflow interrupt enable */
+#  define SYSCFG_CFGR1_FPUIE_DENORMAL  (16 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Input denormal interrupt enable */
+#  define SYSCFG_CFGR1_FPUIE_INEXACT   (32 << SYSCFG_CFGR1_FPUIE_SHIFT) /* Inexact interrupt enable */
+
+/* SYSCFG CCM SRAM protection register */
+
+#define SYSCFG_RCR(page)               (1 << (page)) /* Bit n: Write protection page n */
+
+/* SYSCFG external interrupt configuration register 1-4 */
+
+#define SYSCFG_EXTICR_PORTA           (0)       /* 0000: PA[x] pin */
+#define SYSCFG_EXTICR_PORTB           (1)       /* 0001: PB[x] pin */
+#define SYSCFG_EXTICR_PORTC           (2)       /* 0010: PC[x] pin */
+#define SYSCFG_EXTICR_PORTD           (3)       /* 0011: PD[x] pin */
+#define SYSCFG_EXTICR_PORTE           (4)       /* 0100: PE[x] pin */
+
+#define SYSCFG_EXTICR_PORT_MASK       (15)
+#define SYSCFG_EXTICR_EXTI_SHIFT(g)   (((g) & 3) << 2)
+#define SYSCFG_EXTICR_EXTI_MASK(g)    (SYSCFG_EXTICR_PORT_MASK << (SYSCFG_EXTICR_EXTI_SHIFT(g)))
+
+#define SYSCFG_EXTICR1_EXTI0_SHIFT    (0)       /* Bits 0-3: EXTI 0 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI0_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI0_SHIFT)
+#define SYSCFG_EXTICR1_EXTI1_SHIFT    (4)       /* Bits 4-7: EXTI 1 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI1_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI1_SHIFT)
+#define SYSCFG_EXTICR1_EXTI2_SHIFT    (8)       /* Bits 8-11: EXTI 2 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI2_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI2_SHIFT)
+#define SYSCFG_EXTICR1_EXTI3_SHIFT    (12)      /* Bits 12-15: EXTI 3 coinfiguration */
+#define SYSCFG_EXTICR1_EXTI3_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR1_EXTI3_SHIFT)
+
+#define SYSCFG_EXTICR2_EXTI4_SHIFT    (0)       /* Bits 0-3: EXTI 4 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI4_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI4_SHIFT)
+#define SYSCFG_EXTICR2_EXTI5_SHIFT    (4)       /* Bits 4-7: EXTI 5 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI5_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI5_SHIFT)
+#define SYSCFG_EXTICR2_EXTI6_SHIFT    (8)       /* Bits 8-11: EXTI 6 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI6_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI6_SHIFT)
+#define SYSCFG_EXTICR2_EXTI7_SHIFT    (12)      /* Bits 12-15: EXTI 7 coinfiguration */
+#define SYSCFG_EXTICR2_EXTI7_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR2_EXTI7_SHIFT)
+
+#define SYSCFG_EXTICR3_EXTI8_SHIFT    (0)       /* Bits 0-3: EXTI 8 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI8_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI8_SHIFT)
+#define SYSCFG_EXTICR3_EXTI9_SHIFT    (4)       /* Bits 4-7: EXTI 9 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI9_MASK     (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI9_SHIFT)
+#define SYSCFG_EXTICR3_EXTI10_SHIFT   (8)       /* Bits 8-11: EXTI 10 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI10_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI10_SHIFT)
+#define SYSCFG_EXTICR3_EXTI11_SHIFT   (12)      /* Bits 12-15: EXTI 11 coinfiguration */
+#define SYSCFG_EXTICR3_EXTI11_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR3_EXTI11_SHIFT)
+
+#define SYSCFG_EXTICR4_EXTI12_SHIFT   (0)       /* Bits 0-3: EXTI 12 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI12_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI12_SHIFT)
+#define SYSCFG_EXTICR4_EXTI13_SHIFT   (4)       /* Bits 4-7: EXTI 13 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI13_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI13_SHIFT)
+#define SYSCFG_EXTICR4_EXTI14_SHIFT   (8)       /* Bits 8-11: EXTI 14 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI14_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI14_SHIFT)
+#define SYSCFG_EXTICR4_EXTI15_SHIFT   (12)      /* Bits 12-15: EXTI 15 coinfiguration */
+#define SYSCFG_EXTICR4_EXTI15_MASK    (SYSCFG_EXTICR_PORT_MASK << SYSCFG_EXTICR4_EXTI15_SHIFT)
+
+/* SYSCFG configuration register 2 */
+
+#define SYSCFG_CFGR2_LOCKUPLOCK       (1 << 0)  /* Bit 0: Cortex-M4 Hardfault output bit enable */
+#define SYSCFG_CFGR2_SRAM_PARITYLOCK  (1 << 1)  /* Bit 1: RAM parity lock */
+#define SYSCFG_CFGR2_PVDLOCK          (1 << 2)  /* Bit 2: PVD lock enable */
+#define SYSCFG_CFGR2_BYPADDPAR        (1 << 4)  /* Bit 4: Bypass address bit 29 in parity calculation */
+#define SYSCFG_CFGR2_SRAM_PEF         (1 << 8)  /* Bit 8: SRAM parity error */
+
+/* SYSCFG configuration register 3 */
+/* TODO */
+
+#endif /* CONFIG_STM32_STM32F33XX */
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F33XXX_SYSCFG_H */

arch/arm/src/stm32/chip/stm32f33xxx_vectors.h

@@ -0,0 +1,151 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32f33xxx_vectors.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Pre-processor definitions
+ ************************************************************************************/
+/* This file is included by stm32_vectors.S.  It provides the macro VECTOR that
+ * supplies each STM32F33xxx vector in terms of a (lower-case) ISR label and an
+ * (upper-case) IRQ number as defined in arch/arm/include/stm32/stm32f33xxx_irq.h.
+ * stm32_vectors.S will defined the VECTOR in different ways in order to generate
+ * the interrupt vectors and handlers in their final form.
+ */
+
+/* If the common ARMv7-M vector handling is used, then all it needs is the following
+ * definition that provides the number of supported vectors.
+ */
+
+#ifdef CONFIG_ARMV7M_CMNVECTOR
+
+/* Reserve 82 interrupt table entries for I/O interrupts. */
+
+#  define ARMV7M_PERIPHERAL_INTERRUPTS 82
+
+#else
+
+VECTOR(stm32_wwdg, STM32_IRQ_WWDG)             /* 0:  Window Watchdog interrupt */
+VECTOR(stm32_pvd, STM32_IRQ_PVD)               /* 1:  PVD through EXTI Line detection interrupt */
+VECTOR(stm32_tamper, STM32_IRQ_TAMPER)         /* 2:  Tamper or Time stamp interrupt */
+VECTOR(stm32_rtc_wkup, STM32_IRQ_RTC_WKUP)     /* 3:  RTC global interrupt */
+VECTOR(stm32_flash, STM32_IRQ_FLASH)           /* 4:  Flash global interrupt */
+VECTOR(stm32_rcc, STM32_IRQ_RCC)               /* 5:  RCC global interrupt */
+VECTOR(stm32_exti0, STM32_IRQ_EXTI0)           /* 6:  EXTI Line 0 interrupt */
+VECTOR(stm32_exti1, STM32_IRQ_EXTI1)           /* 7:  EXTI Line 1 interrupt */
+VECTOR(stm32_exti2, STM32_IRQ_EXTI2)           /* 8:  EXTI Line 2 or TSC interrupt */
+VECTOR(stm32_exti3, STM32_IRQ_EXTI3)           /* 9:  EXTI Line 3 interrupt */
+
+VECTOR(stm32_exti4, STM32_IRQ_EXTI4)           /* 10: EXTI Line 4 interrupt */
+VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1)       /* 11: DMA1 channel 1 global interrupt */
+VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2)       /* 12: DMA1 channel 2 global interrupt */
+VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3)       /* 13: DMA1 channel 3 global interrupt */
+VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4)       /* 14: DMA1 channel 4 global interrupt */
+VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5)       /* 15: DMA1 channel 5 global interrupt */
+VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)       /* 16: DMA1 channel 6 global interrupt */
+VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7)       /* 17: DMA1 channel 7 global interrupt */
+VECTOR(stm32_adc12, STM32_IRQ_ADC12)           /* 18: ADC1/ADC2 global interrupt */
+VECTOR(stm32_can1tx, STM32_IRQ_CAN1TX)         /* 19: USB High Priority or CAN1 TX interrupts */
+
+VECTOR(stm32_can1rx0, STM32_IRQ_CAN1RX0)       /* 20: USB Low Priority or CAN1 RX0 interrupts*/
+VECTOR(stm32_can1rx1, STM32_IRQ_CAN1RX1)       /* 21: CAN1 RX1 interrupt */
+VECTOR(stm32_can1sce, STM32_IRQ_CAN1SCE)       /* 22: CAN1 SCE interrupt */
+VECTOR(stm32_exti95, STM32_IRQ_EXTI95)         /* 23: EXTI Line[9:5] interrupts */
+VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK)       /* 24: TIM1 Break or TIM15 global interrupt */
+VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP)         /* 25: TIM1 Update or TIM16 global interrupt */
+VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM) /* 26: TIM1 Trigger or TIM17 global interrupt */
+VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC)         /* 27: TIM1 Capture Compare interrupt */
+VECTOR(stm32_tim2, STM32_IRQ_TIM2)             /* 28: TIM2 global interrupt */
+VECTOR(stm32_tim3, STM32_IRQ_TIM3)             /* 29: TIM3 global interrupt */
+
+UNUSED(STM32_IRQ_RESERVED30)                   /* 30: Reserved */
+VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV)         /* 31: I2C1 event or EXTI Line23 interrupt */
+VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER)         /* 32: I2C1 error interrupt */
+UNUSED(STM32_IRQ_RESERVED33)                   /* 33: Reserved */
+UNUSED(STM32_IRQ_RESERVED34)                   /* 34: Reserved */
+VECTOR(stm32_spi1, STM32_IRQ_SPI1)             /* 35: SPI1 global interrupt */
+UNUSED(STM32_IRQ_RESERVED36)                   /* 36: Reserved */
+VECTOR(stm32_usart1, STM32_IRQ_USART1)         /* 37: USART1 global or EXTI Line 25 interrupt */
+VECTOR(stm32_usart2, STM32_IRQ_USART2)         /* 38: USART2 global or EXTI Line 26 interrupt */
+VECTOR(stm32_usart3, STM32_IRQ_USART3)         /* 39: USART3 global or EXTI Line 28 interrupt */
+
+VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510)     /* 40: EXTI Line[15:10] interrupts */
+VECTOR(stm32_rtcalrm, STM32_IRQ_RTCALRM)       /* 41: RTC alarm through EXTI line interrupt */
+UNUSED(STM32_IRQ_RESERVED42)                   /* 42: Reserved*/
+UNUSED(STM32_IRQ_RESERVED43)                   /* 43: Reserved */
+UNUSED(STM32_IRQ_RESERVED44)                   /* 44: Reserved */
+UNUSED(STM32_IRQ_RESERVED45)                   /* 45: Reserved */
+UNUSED(STM32_IRQ_RESERVED46)                   /* 46: Reserved */
+UNUSED(STM32_IRQ_RESERVED47)                   /* 47: Reserved*/
+UNUSED(STM32_IRQ_RESERVED48)                   /* 48: Reserved */
+UNUSED(STM32_IRQ_RESERVED49)                   /* 49: Reserved */
+
+UNUSED(STM32_IRQ_RESERVED50)                   /* 50: Reserved */
+UNUSED(STM32_IRQ_RESERVED51)                   /* 51: Reserved */
+UNUSED(STM32_IRQ_RESERVED51)                   /* 52: Reserved*/
+UNUSED(STM32_IRQ_RESERVED52)                   /* 53: Reserved */
+VECTOR(stm32_dac1, STM32_IRQ_DAC1)             /* 54: TIM6 global or DAC1 underrun interrupts */
+VECTOR(stm32_dac2, STM32_IRQ_DAC2)             /* 55: TIM7 global or DAC2 underrun interrupt */
+UNUSED(STM32_IRQ_RESERVED56)                   /* 56: Reserved */
+UNUSED(STM32_IRQ_RESERVED57)                   /* 57: Reserved */
+UNUSED(STM32_IRQ_RESERVED58)                   /* 58: Reserved */
+UNUSED(STM32_IRQ_RESERVED59)                   /* 59: Reserved */
+
+UNUSED(STM32_IRQ_RESERVED60)                   /* 60: Reserved */
+UNUSED(STM32_IRQ_RESERVED61)                   /* 61: Reserved */
+UNUSED(STM32_IRQ_RESERVED62)                   /* 62: Reserved */
+UNUSED(STM32_IRQ_RESERVED63)                   /* 63: Reserved */
+VECTOR(stm32_comp2, STM32_IRQ_COMP2)           /* 64: COMP2 or EXTI Lines 21-2 and 29 interrupts */
+VECTOR(stm32_comp46, STM32_IRQ_COMP46)         /* 65: COMP4/COMP6 or EXTI Lines 30-2 interrupts */
+UNUSED(STM32_IRQ_RESERVED66)                   /* 66: Reserved */
+VECTOR(stm32_hrtim_tm, STM32_IRQ_HRTIMTM)      /* 67: HRTIM master timer interrutp */
+VECTOR(stm32_hrtim_ta, STM32_IRQ_HRTIMTA)      /* 68: HRTIM timer A interrutp */
+VECTOR(stm32_hrtim_tb, STM32_IRQ_HRTIMTB)      /* 69: HRTIM timer B interrutp */
+
+VECTOR(stm32_hrtim_tc, STM32_IRQ_HRTIMTC)      /* 70: HRTIM timer C interrutp */
+VECTOR(stm32_hrtim_td, STM32_IRQ_HRTIMTD)      /* 71: HRTIM timer D interrutp */
+VECTOR(stm32_hrtim_te, STM32_IRQ_HRTIMTE)      /* 72: HRTIM timer E interrutp */
+VECTOR(stm32_hrtim_flt, STM32_IRQ_HRTIMFLT)    /* 73: HRTIM fault interrutp */
+UNUSED(STM32_IRQ_RESERVED73)                   /* 74: Reserved */
+UNUSED(STM32_IRQ_RESERVED74)                   /* 75: Reserved */
+UNUSED(STM32_IRQ_RESERVED75)                   /* 76: Reserved */
+UNUSED(STM32_IRQ_RESERVED76)                   /* 77: Reserved */
+UNUSED(STM32_IRQ_RESERVED77)                   /* 78: Reserved */
+UNUSED(STM32_IRQ_RESERVED78)                   /* 79: Reserved */
+
+UNUSED(STM32_IRQ_RESERVED79)                   /* 80: Reserved */
+UNUSED(STM32_IRQ_RESERVED80)                   /* 81: Reserved */
+VECTOR(stm32_fpu, STM32_IRQ_FPU)               /* 82: FPU global interrupt */
+
+#endif /* CONFIG_ARMV7M_CMNVECTOR */

arch/arm/src/stm32/gnu/stm32_vectors.S

@@ -177,6 +177,8 @@ _vectors:
 #  include "chip/stm32f20xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_vectors.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F40XX)
@@ -222,6 +224,8 @@ handlers:
 #  include "chip/stm32f20xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_vectors.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/iar/stm32_vectors.S

@@ -461,6 +461,8 @@ __vector_table:
 	DCD	stm32_hash        /* Vector 16+80: Hash and Rng global interrupt */
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_vectors.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
@@ -778,6 +780,8 @@ handlers:
 
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_vectors.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_vectors.h"
 #elif defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)

arch/arm/src/stm32/stm32_allocateheap.c

@@ -222,6 +222,76 @@
 #      endif
 #    endif
 
+/* All members of the STM32F33xxx families have 16 Kbi ram and 4 KB CCM SRAM.
+ * No external RAM is supported (the F3 family has no FSMC).
+ *
+ * As a complication, CCM SRAM cannot be used for DMA.  So, if STM32 DMA is
+ * enabled, CCM SRAM should probably be excluded from the heap.
+ */
+#elif defined(CONFIG_STM32_STM32F33XX)
+
+   /* Set the end of system SRAM */
+
+#  define SRAM1_END CONFIG_RAM_END
+
+/* Set the range of CCM SRAM as well (although we may not use it) */
+
+#  define SRAM2_START 0x10000000
+#  define SRAM2_END   0x10001000
+
+   /* There is no FSMC */
+
+#  undef CONFIG_STM32_FSMC_SRAM
+
+   /* There are 2 possible SRAM configurations:
+    *
+    * Configuration 1. System SRAM (only)
+    *                  CONFIG_MM_REGIONS == 1
+    *                  CONFIG_STM32_CCMEXCLUDE defined
+    * Configuration 2. System SRAM and CCM SRAM
+    *                  CONFIG_MM_REGIONS == 2
+    *                  CONFIG_STM32_CCMEXCLUDE NOT defined
+    */
+
+#    if CONFIG_MM_REGIONS < 2
+
+       /* Only one memory region.  Force Configuration 1 */
+
+#      ifndef CONFIG_STM32_CCMEXCLUDE
+#        if CONFIG_STM32_HAVE_CCM
+#          warning "CCM SRAM excluded from the heap"
+#        endif
+#        define CONFIG_STM32_CCMEXCLUDE 1
+#      endif
+
+   /* CONFIG_MM_REGIONS may be 2 if CCM SRAM is included in the head */
+
+#    elif CONFIG_MM_REGIONS >= 2
+#      if CONFIG_MM_REGIONS > 2
+#         error "No more than two memory regions can be supported (CONFIG_MM_REGIONS)"
+#         undef CONFIG_MM_REGIONS
+#         define CONFIG_MM_REGIONS 2
+#      endif
+
+     /* Two memory regions is okay if CCM SRAM is not disabled. */
+
+#      ifdef CONFIG_STM32_CCMEXCLUDE
+
+         /* Configuration 1: CONFIG_MM_REGIONS should have been 2 */
+
+#        error "CONFIG_MM_REGIONS >= 2 but but CCM SRAM is excluded (CONFIG_STM32_CCMEXCLUDE)"
+#        undef CONFIG_MM_REGIONS
+#        define CONFIG_MM_REGIONS 1
+#      else
+
+         /* Configuration 2: DMA should be disabled */
+
+#        ifdef CONFIG_ARCH_DMA
+#          warning "CCM SRAM is included in the heap AND DMA is enabled"
+#        endif
+#      endif
+#  endif
+
 /* All members of the STM32F37xxx families have 16-32 Kib ram in a single
  * bank. No external RAM is supported (the F3 family has no FSMC).
  */
@@ -246,7 +316,6 @@
 #    error "CONFIG_MM_REGIONS > 1.  The STM32L15X has only one memory region."
 #  endif
 
-
 /* Most members of both the STM32F20xxx and STM32F40xxx families have 128Kib
  * in two banks:
  *

arch/arm/src/stm32/stm32_ccm.h

@@ -58,7 +58,8 @@
 #if defined(CONFIG_STM32_STM32F30XX)
 #  define CCM_START 0x10000000
 #  define CCM_END   0x10002000
-#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
+      defined(CONFIG_STM32_STM32F33XX)
 #  define CCM_START 0x10000000
 #  define CCM_END   0x10010000
 #else

arch/arm/src/stm32/stm32_dac.c

@@ -94,6 +94,12 @@
 #     undef CONFIG_STM32_DAC1_DMA
 #     undef CONFIG_STM32_DAC2_DMA
 #   endif
+# elif defined(CONFIG_STM32_STM32F33XX)
+#   ifndef CONFIG_STM32_DMA1
+#     warning "STM32 F334 DAC DMA support requires CONFIG_STM32_DMA1"
+#     undef CONFIG_STM32_DAC1_DMA
+#     undef CONFIG_STM32_DAC2_DMA
+#   endif
 # elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #   ifndef CONFIG_STM32_DMA1
 #     warning "STM32 F4 DAC DMA support requires CONFIG_STM32_DMA1"
@@ -147,7 +153,8 @@
 #   define DAC_DMA         2
 #   define DAC1_DMA_CHAN   DMACHAN_DAC_CHAN1
 #   define DAC2_DMA_CHAN   DMACHAN_DAC_CHAN2
-# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+# elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) || \
+  defined(CONFIG_STM32_STM32F33XX)
 #   define HAVE_DMA        1
 #   define DAC_DMA         1
 #   define DAC1_DMA_CHAN   DMAMAP_DAC1

arch/arm/src/stm32/stm32_dma.c

@@ -56,7 +56,8 @@
  */
 
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
 #  include "stm32f10xxx_dma.c"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "stm32f20xxx_dma.c"

arch/arm/src/stm32/stm32_dma.h

@@ -48,7 +48,8 @@
 /* Include the correct DMA register definitions for this STM32 family */
 
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f10xxx_dma.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_dma.h"
@@ -63,7 +64,8 @@
  */
 
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
 #  define DMA_STATUS_FEIF         0                     /* (Not available in F1) */
 #  define DMA_STATUS_DMEIF        0                     /* (Not available in F1) */
 #  define DMA_STATUS_TEIF         DMA_CHAN_TEIF_BIT     /* Channel Transfer Error */
@@ -106,7 +108,8 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
 
 #ifdef CONFIG_DEBUG_DMA_INFO
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
 struct stm32_dmaregs_s
 {
   uint32_t isr;

arch/arm/src/stm32/stm32_dumpgpio.c

@@ -172,7 +172,8 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
             g_portchar[port], getreg32(STM32_RCC_AHBENR));
     }
 
-#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+      defined(CONFIG_STM32_STM32F33XX)
   DEBUGASSERT(port < STM32_NGPIO_PORTS);
 
   _info("GPIO%c pinset: %08x base: %08x -- %s\n",

arch/arm/src/stm32/stm32_gpio.c

@@ -55,8 +55,8 @@
 #include "stm32_gpio.h"
 
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
 #  include "chip/stm32_syscfg.h"
 #endif
 
@@ -427,8 +427,8 @@ int stm32_configgpio(uint32_t cfgset)
  ****************************************************************************/
 
 #if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+    defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-    defined(CONFIG_STM32_STM32F40XX)
+    defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
 int stm32_configgpio(uint32_t cfgset)
 {
   uintptr_t base;
@@ -585,7 +585,8 @@ int stm32_configgpio(uint32_t cfgset)
             setting = GPIO_OSPEED_50MHz;
             break;
 
-#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F37XX)
+#if !defined(CONFIG_STM32_STM32F30XX) && !defined(CONFIG_STM32_STM32F33XX) && \
+    !defined(CONFIG_STM32_STM32F37XX)
           case GPIO_SPEED_100MHz:   /* 100 MHz High speed output */
             setting = GPIO_OSPEED_100MHz;
             break;
@@ -681,8 +682,8 @@ int stm32_unconfiggpio(uint32_t cfgset)
 #if defined(CONFIG_STM32_STM32F10XX)
   cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
 #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-      defined(CONFIG_STM32_STM32F40XX)
+      defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
   cfgset |= GPIO_INPUT | GPIO_FLOAT;
 #else
 # error "Unsupported STM32 chip"
@@ -707,8 +708,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
 #if defined(CONFIG_STM32_STM32F10XX)
   uint32_t offset;
 #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-      defined(CONFIG_STM32_STM32F40XX)
+      defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
   uint32_t bit;
 #endif
   unsigned int port;
@@ -741,8 +742,8 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
       putreg32((1 << pin), base + offset);
 
 #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-      defined(CONFIG_STM32_STM32F40XX)
+      defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
 
       if (value)
         {

arch/arm/src/stm32/stm32_gpio.h

@@ -59,7 +59,8 @@
 #  include "chip/stm32f10xxx_gpio.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_gpio.h"
-#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+      defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f30xxx_gpio.h"
 #elif defined(CONFIG_STM32_STM32F40XX)
 #  include "chip/stm32f40xxx_gpio.h"
@@ -201,8 +202,8 @@
 #define GPIO_PIN15                    (15 << GPIO_PIN_SHIFT)
 
 #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-      defined(CONFIG_STM32_STM32F40XX)
+      defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
 
 /* Each port bit of the general-purpose I/O (GPIO) ports can be individually configured
  * by software in several modes:

arch/arm/src/stm32/stm32_i2c.h

@@ -44,7 +44,8 @@
 #include <nuttx/i2c/i2c_master.h>
 
 #include "chip.h"
-#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+    defined(CONFIG_STM32_STM32F33XX)
 #  include "chip/stm32f30xxx_i2c.h"
 #else
 #  include "chip/stm32_i2c.h"

arch/arm/src/stm32/stm32_lowputc.c

@@ -62,7 +62,11 @@
 #ifdef HAVE_CONSOLE
 #  if defined(CONFIG_USART1_SERIAL_CONSOLE)
 #    define STM32_CONSOLE_BASE     STM32_USART1_BASE
+#    if defined(CONFIG_STM32_STM32F33XX)
+#      define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY /* Errata 2.5.1 */
+#    else
 #      define STM32_APBCLOCK         STM32_PCLK2_FREQUENCY
+#    endif
 #    define STM32_CONSOLE_APBREG   STM32_RCC_APB2ENR
 #    define STM32_CONSOLE_APBEN    RCC_APB2ENR_USART1EN
 #    define STM32_CONSOLE_BAUD     CONFIG_USART1_BAUD
@@ -230,7 +234,8 @@
 #    define USART_CR1_PARITY_VALUE 0
 #  endif
 
-#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+   defined(CONFIG_STM32_STM32F37XX)
 #    define USART_CR1_CLRBITS\
       (USART_CR1_UESM | USART_CR1_RE | USART_CR1_TE | USART_CR1_PS | \
        USART_CR1_PCE | USART_CR1_WAKE | USART_CR1_M | USART_CR1_MME | \
@@ -252,7 +257,8 @@
 #    define USART_CR2_STOP2_VALUE 0
 #  endif
 
-#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+   defined(CONFIG_STM32_STM32F37XX)
 #    define USART_CR2_CLRBITS \
       (USART_CR2_ADDM7 | USART_CR2_LBDL | USART_CR2_LBDIE | USART_CR2_LBCL | \
        USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_STOP_MASK | \
@@ -268,7 +274,8 @@
 
   /* CR3 settings */
 
-#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+   defined(CONFIG_STM32_STM32F37XX)
 
 #    define USART_CR3_CLRBITS \
       (USART_CR3_EIE | USART_CR3_IREN | USART_CR3_IRLP | USART_CR3_HDSEL | \
@@ -288,7 +295,8 @@
 
   /* Calculate USART BAUD rate divider */
 
-#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#  if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+   defined(CONFIG_STM32_STM32F37XX)
 
     /* Baud rate for standard USART (SPI mode included):
      *
@@ -563,8 +571,8 @@ void stm32_lowsetup(void)
 }
 
 #elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F20XX) || \
-      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX) || \
+      defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
-      defined(CONFIG_STM32_STM32F40XX)
+      defined(CONFIG_STM32_STM32F37XX) || defined(CONFIG_STM32_STM32F40XX)
 
 void stm32_lowsetup(void)
 {

arch/arm/src/stm32/stm32_rcc.c

@@ -82,6 +82,8 @@
 #  include "stm32f20xxx_rcc.c"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "stm32f30xxx_rcc.c"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "stm32f33xxx_rcc.c"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "stm32f37xxx_rcc.c"
 #elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/stm32_rcc.h

@@ -53,6 +53,8 @@
 #  include "chip/stm32f20xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_rcc.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_rcc.h"
 #elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/stm32_serial.c

@@ -151,7 +151,8 @@
 #    endif
 
 #  elif defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-        defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F30XX)
+        defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+        defined(CONFIG_STM32_STM32F37XX)
 
 #    if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
       defined(CONFIG_USART3_RXDMA)
@@ -188,7 +189,8 @@
 
 #  ifndef CONFIG_USART_DMAPRIO
 #    if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-        defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+        defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+        defined(CONFIG_STM32_STM32F37XX)
 #      define CONFIG_USART_DMAPRIO  DMA_CCR_PRIMED
 #    elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
 #      define CONFIG_USART_DMAPRIO  DMA_SCR_PRIMED
@@ -197,7 +199,8 @@
 #    endif
 #  endif
 #    if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
-        defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+        defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+        defined(CONFIG_STM32_STM32F37XX)
 #    if (CONFIG_USART_DMAPRIO & ~DMA_CCR_PL_MASK) != 0
 #      error "Illegal value for CONFIG_USART_DMAPRIO"
 #    endif
@@ -540,7 +543,11 @@ static struct up_dev_s g_usart1priv =
   .bits          = CONFIG_USART1_BITS,
   .stopbits2     = CONFIG_USART1_2STOP,
   .baud          = CONFIG_USART1_BAUD,
+#if defined(CONFIG_STM32_STM32F33XX)
+  .apbclock      = STM32_PCLK1_FREQUENCY, /* Errata 2.5.1 */
+#else
   .apbclock      = STM32_PCLK2_FREQUENCY,
+#endif
   .usartbase     = STM32_USART1_BASE,
   .tx_gpio       = GPIO_USART1_TX,
   .rx_gpio       = GPIO_USART1_RX,
@@ -1173,7 +1180,8 @@ static int up_dma_nextrx(struct up_dev_s *priv)
 static void up_set_format(struct uart_dev_s *dev)
 {
   struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
-#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
   uint32_t usartdiv8;
 #else
   uint32_t usartdiv32;
@@ -1187,7 +1195,8 @@ static void up_set_format(struct uart_dev_s *dev)
 
   regval = up_serialin(priv, STM32_USART_CR1_OFFSET);
 
-#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX)|| \
+    defined(CONFIG_STM32_STM32F37XX)
   /* This first implementation is for U[S]ARTs that support oversampling
    * by 8 in additional to the standard oversampling by 16.
    * With baud rate of fCK / Divider for oversampling by 16.
@@ -1855,7 +1864,8 @@ static int up_interrupt_common(struct up_dev_s *priv)
 
       else if ((priv->sr & (USART_SR_ORE | USART_SR_NE | USART_SR_FE)) != 0)
         {
-#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#if defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
           /* These errors are cleared by writing the corresponding bit to the
            * interrupt clear register (ICR).
            */

arch/arm/src/stm32/stm32_syscfg.h

@@ -49,6 +49,8 @@
 #  include "chip/stm32f20xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f30xxx_syscfg.h"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f37xxx_syscfg.h"
 #elif defined(CONFIG_STM32_STM32F40XX)

arch/arm/src/stm32/stm32_uart.h

@@ -50,7 +50,8 @@
 #  include "chip/stm32f10xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_uart.h"
-#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F37XX)
+#elif defined(CONFIG_STM32_STM32F30XX) || defined(CONFIG_STM32_STM32F33XX) || \
+    defined(CONFIG_STM32_STM32F37XX)
 #  include "chip/stm32f30xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F40XX)
 #  include "chip/stm32f40xxx_uart.h"

arch/arm/src/stm32/stm32f33xxx_rcc.c

@@ -0,0 +1,628 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32f33xxx_rcc.c
+ *
+ *   Copyright (C) 2012, 2015, 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Modified for STM32F334 by Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Allow up to 100 milliseconds for the high speed clock to become ready.
+ * that is a very long delay, but if the clock does not become ready we are
+ * hosed anyway.  Normally this is very fast, but I have seen at least one
+ * board that required this long, long timeout for the HSE to be ready.
+ */
+
+#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: rcc_reset
+ *
+ * Description:
+ *   Put all RCC registers in reset state
+ *
+ ****************************************************************************/
+
+static inline void rcc_reset(void)
+{
+  uint32_t regval;
+
+  putreg32(0, STM32_RCC_APB2RSTR);          /* Disable APB2 Peripheral Reset */
+  putreg32(0, STM32_RCC_APB1RSTR);          /* Disable APB1 Peripheral Reset */
+  putreg32(RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN, STM32_RCC_AHBENR); /* FLITF and SRAM Clock ON */
+  putreg32(0, STM32_RCC_APB2ENR);           /* Disable APB2 Peripheral Clock */
+  putreg32(0, STM32_RCC_APB1ENR);           /* Disable APB1 Peripheral Clock */
+
+  regval  = getreg32(STM32_RCC_CR);         /* Set the HSION bit */
+  regval |= RCC_CR_HSION;
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CFGR);       /* Reset SW, HPRE, PPRE1, PPRE2, and MCO bits */
+  regval &= ~(RCC_CFGR_SW_MASK | RCC_CFGR_HPRE_MASK | RCC_CFGR_PPRE1_MASK |
+              RCC_CFGR_PPRE2_MASK | RCC_CFGR_MCO_MASK);
+
+  putreg32(regval, STM32_RCC_CFGR);
+
+  regval  = getreg32(STM32_RCC_CFGR2);       /* Reset PREDIV, and ADC12PRE bits */
+  regval &= ~(RCC_CFGR2_PREDIV_MASK | RCC_CFGR2_ADC12PRES_MASK);
+  putreg32(regval, STM32_RCC_CFGR2);
+
+  regval  = getreg32(STM32_RCC_CFGR3);       /* Reset all U[S]ARTs, I2C1, TIM1 and HRTIM1 bits */
+  regval &= ~(RCC_CFGR3_USART1SW_MASK | RCC_CFGR3_USART2SW_MASK | RCC_CFGR3_USART3SW_MASK | \
+              RCC_CFGR3_I2C1SW | RCC_CFGR3_TIM1SW | RCC_CFGR3_HRTIM1SW);
+  putreg32(regval, STM32_RCC_CFGR3);
+
+  regval  = getreg32(STM32_RCC_CR);         /* Reset HSEON, CSSON and PLLON bits */
+  regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CR);         /* Reset HSEBYP bit */
+  regval &= ~RCC_CR_HSEBYP;
+  putreg32(regval, STM32_RCC_CR);
+
+  regval  = getreg32(STM32_RCC_CFGR);       /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  putreg32(0, STM32_RCC_CIR);               /* Disable all interrupts */
+}
+
+/****************************************************************************
+ * Name: rcc_enableahb
+ *
+ * Description:
+ *   Enable selected AHB peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableahb(void)
+{
+  uint32_t regval;
+
+  /* Always enable FLITF clock and SRAM clock */
+
+  regval = RCC_AHBENR_FLITFEN | RCC_AHBENR_SRAMEN;
+
+  /* Enable GPIO PORTA, PORTB, ... PORTF */
+
+  regval |= (RCC_AHBENR_IOPAEN | RCC_AHBENR_IOPBEN | RCC_AHBENR_IOPCEN |
+             RCC_AHBENR_IOPDEN | RCC_AHBENR_IOPFEN);
+
+#ifdef CONFIG_STM32_DMA1
+  /* DMA 1 clock enable */
+
+  regval |= RCC_AHBENR_DMA1EN;
+#endif
+
+#ifdef CONFIG_STM32_CRC
+  /* CRC clock enable */
+
+  regval |= RCC_AHBENR_CRCEN;
+#endif
+
+#ifdef CONFIG_STM32_TSC
+  /* CRC clock enable */
+
+  regval |= RCC_AHBENR_TSCEN;
+#endif
+
+#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2)
+  /* ADC1/ADC2 interface clock enable */
+
+  regval |= RCC_AHBENR_ADC12EN;
+#endif
+
+  putreg32(regval, STM32_RCC_AHBENR);   /* Enable peripherals */
+}
+
+/****************************************************************************
+ * Name: rcc_enableapb1
+ *
+ * Description:
+ *   Enable selected APB1 peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableapb1(void)
+{
+  uint32_t regval;
+
+  /* Set the appropriate bits in the APB1ENR register to enabled the
+   * selected APB1 peripherals.
+   */
+
+  regval  = getreg32(STM32_RCC_APB1ENR);
+
+#ifdef CONFIG_STM32_TIM2
+  /* Timer 2 clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM2EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM3
+  /* Timer 3 clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM3EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM6
+  /* Timer 6 clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM6EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM7
+  /* Timer 7 clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM7EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_WWDG
+  /* Window Watchdog clock enable */
+
+  regval |= RCC_APB1ENR_WWDGEN;
+#endif
+
+#ifdef CONFIG_STM32_USART2
+  /* USART 2 clock enable */
+
+  regval |= RCC_APB1ENR_USART2EN;
+#endif
+
+#ifdef CONFIG_STM32_USART3
+  /* USART 3 clock enable */
+
+  regval |= RCC_APB1ENR_USART3EN;
+#endif
+
+#ifdef CONFIG_STM32_I2C1
+  /* I2C 1 clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_I2C1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_CAN1
+  /* CAN1 clock enable */
+
+  regval |= RCC_APB1ENR_CAN1EN;
+#endif
+
+#ifdef CONFIG_STM32_DAC2
+  /* DAC2 interface clock enable */
+
+  regval |= RCC_APB1ENR_DAC2EN;
+#endif
+
+#ifdef CONFIG_STM32_PWR
+  /*  Power interface clock enable */
+
+  regval |= RCC_APB1ENR_PWREN;
+#endif
+
+#ifdef CONFIG_STM32_DAC1
+  /* DAC1 interface clock enable */
+
+  regval |= RCC_APB1ENR_DAC1EN;
+#endif
+
+  putreg32(regval, STM32_RCC_APB1ENR);
+}
+
+/****************************************************************************
+ * Name: rcc_enableapb2
+ *
+ * Description:
+ *   Enable selected APB2 peripherals
+ *
+ ****************************************************************************/
+
+static inline void rcc_enableapb2(void)
+{
+  uint32_t regval;
+
+  /* Set the appropriate bits in the APB2ENR register to enabled the
+   * selected APB2 peripherals.
+   */
+
+  regval = getreg32(STM32_RCC_APB2ENR);
+
+#ifdef CONFIG_STM32_SYSCFG
+  /* SYSCFG clock */
+
+  regval |= RCC_APB2ENR_SYSCFGEN;
+#endif
+
+#ifdef CONFIG_STM32_TIM1
+  /* TIM1 Timer clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM1EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_SPI1
+  /* SPI 1 clock enable */
+
+  regval |= RCC_APB2ENR_SPI1EN;
+#endif
+
+#ifdef CONFIG_STM32_USART1
+  /* USART1 clock enable */
+
+  regval |= RCC_APB2ENR_USART1EN;
+#endif
+
+#ifdef CONFIG_STM32_TIM15
+  /* TIM15 Timer clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM15EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM16
+  /* TIM16 Timer clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM16EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM17
+  /* TIM17 Timer clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM17EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_HRTIM1
+  /* HRTIM1 Timer clock enable */
+
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_HRTIM1EN;
+#endif
+#endif
+
+  putreg32(regval, STM32_RCC_APB2ENR);
+}
+
+/****************************************************************************
+ * Name: stm32_stdclockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on settings in board.h.  This
+ *   version is for the Connectivity Line parts.
+ *
+ *   NOTE:  This logic would need to be extended if you need to select low-
+ *   power clocking modes!
+ ****************************************************************************/
+
+#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && defined(CONFIG_STM32_CONNECTIVITYLINE)
+static void stm32_stdclockconfig(void)
+{
+  uint32_t regval;
+
+  /* Enable HSE */
+
+  regval  = getreg32(STM32_RCC_CR);
+  regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
+  regval |= RCC_CR_HSEON;           /* Enable HSE */
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Set flash wait states
+   * Sysclk runs with 72MHz -> 2 waitstates.
+   * 0WS from 0-24MHz
+   * 1WS from 24-48MHz
+   * 2WS from 48-72MHz
+   */
+
+  regval  = getreg32(STM32_FLASH_ACR);
+  regval &= ~FLASH_ACR_LATENCY_MASK;
+  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  putreg32(regval, STM32_FLASH_ACR);
+
+  /* Set up PLL input scaling (with source = PLL2) */
+
+  regval = getreg32(STM32_RCC_CFGR2);
+  regval &= ~(RCC_CFGR2_PREDIV2_MASK | RCC_CFGR2_PLL2MUL_MASK |
+              RCC_CFGR2_PREDIV1SRC_MASK | RCC_CFGR2_PREDIV1_MASK);
+  regval |=  (STM32_PLL_PREDIV2 | STM32_PLL_PLL2MUL |
+              RCC_CFGR2_PREDIV1SRC_PLL2 | STM32_PLL_PREDIV1);
+  putreg32(regval, STM32_RCC_CFGR2);
+
+  /* Set the PCLK2 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_PPRE2_MASK | RCC_CFGR_HPRE_MASK);
+  regval |= STM32_RCC_CFGR_PPRE2;
+  regval |= RCC_CFGR_HPRE_SYSCLK;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK1 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE1_MASK;
+  regval |= STM32_RCC_CFGR_PPRE1;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Enable PLL2 */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLL2ON;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait for PLL2 ready */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
+
+  /* Setup PLL3 for MII/RMII clock on MCO */
+
+#if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
+  regval = getreg32(STM32_RCC_CFGR2);
+  regval &= ~(RCC_CFGR2_PLL3MUL_MASK);
+  regval |= STM32_PLL_PLL3MUL;
+  putreg32(regval, STM32_RCC_CFGR2);
+
+  /* Switch PLL3 on */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLL3ON;
+  putreg32(regval, STM32_RCC_CR);
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0);
+#endif
+
+  /* Set main PLL source and multiplier */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL_MASK);
+  regval |= (RCC_CFGR_PLLSRC | STM32_PLL_PLLMUL);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Switch main PLL on */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLLON;
+  putreg32(regval, STM32_RCC_CR);
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+
+  /* Select PLL as system clock source */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_SW_MASK;
+  regval |= RCC_CFGR_SW_PLL;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Wait until PLL is used as the system clock source */
+
+  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_PLL) == 0);
+}
+#endif
+
+/****************************************************************************
+ * Name: stm32_stdclockconfig
+ *
+ * Description:
+ *   Called to change to new clock based on settings in board.h.  This
+ *   version is for the non-Connectivity Line parts.
+ *
+ *   NOTE:  This logic would need to be extended if you need to select low-
+ *   power clocking modes!
+ ****************************************************************************/
+
+#if !defined(CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG) && \
+    !defined(CONFIG_STM32_CONNECTIVITYLINE)
+static void stm32_stdclockconfig(void)
+{
+  uint32_t regval;
+
+  /* If the PLL is using the HSE, or the HSE is the system clock */
+
+#if (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC) || (STM32_SYSCLK_SW == RCC_CFGR_SW_HSE)
+  {
+    volatile int32_t timeout;
+
+    /* Enable External High-Speed Clock (HSE) */
+
+    regval  = getreg32(STM32_RCC_CR);
+    regval &= ~RCC_CR_HSEBYP;         /* Disable HSE clock bypass */
+    regval |= RCC_CR_HSEON;           /* Enable HSE */
+    putreg32(regval, STM32_RCC_CR);
+
+    /* Wait until the HSE is ready (or until a timeout elapsed) */
+
+    for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
+      {
+        /* Check if the HSERDY flag is the set in the CR */
+
+        if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+          {
+            /* If so, then break-out with timeout > 0 */
+
+            break;
+          }
+      }
+
+    if (timeout == 0)
+      {
+        /* In the case of a timeout starting the HSE, we really don't have a
+         * strategy.  This is almost always a hardware failure or
+         * misconfiguration.
+         */
+
+        return;
+      }
+  }
+
+# if defined(CONFIG_STM32_VALUELINE) && (STM32_CFGR_PLLSRC == RCC_CFGR_PLLSRC)
+  /* If this is a value-line part and we are using the HSE as the PLL */
+
+# if (STM32_CFGR_PLLXTPRE >> 17) != (STM32_CFGR2_PREDIV1 & 1)
+#  error STM32_CFGR_PLLXTPRE must match the LSB of STM32_CFGR2_PREDIV1
+# endif
+
+  /* Set the HSE prescaler */
+
+  regval = STM32_CFGR2_PREDIV1;
+  putreg32(regval, STM32_RCC_CFGR2);
+
+# endif
+#endif
+
+#ifndef CONFIG_STM32_VALUELINE
+  /* Value-line devices don't implement flash prefetch/waitstates */
+  /* Enable FLASH prefetch buffer and 2 wait states */
+
+  regval  = getreg32(STM32_FLASH_ACR);
+  regval &= ~FLASH_ACR_LATENCY_MASK;
+  regval |= (FLASH_ACR_LATENCY_2 | FLASH_ACR_PRTFBE);
+  putreg32(regval, STM32_FLASH_ACR);
+#endif
+
+  /* Set the HCLK source/divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_HPRE_MASK;
+  regval |= STM32_RCC_CFGR_HPRE;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK2 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE2_MASK;
+  regval |= STM32_RCC_CFGR_PPRE2;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Set the PCLK1 divider */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_PPRE1_MASK;
+  regval |= STM32_RCC_CFGR_PPRE1;
+  putreg32(regval, STM32_RCC_CFGR);
+
+#if STM32_SYSCLK_SW == RCC_CFGR_SW_PLL
+  /* If we are using the PLL, configure and start it */
+  /* Set the PLL divider and multiplier */
+
+  regval = getreg32(STM32_RCC_CFGR);
+  regval &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL_MASK);
+  regval |= (STM32_CFGR_PLLSRC | STM32_CFGR_PLLXTPRE | STM32_CFGR_PLLMUL);
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Enable the PLL */
+
+  regval = getreg32(STM32_RCC_CR);
+  regval |= RCC_CR_PLLON;
+  putreg32(regval, STM32_RCC_CR);
+
+  /* Wait until the PLL is ready */
+
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+
+#endif
+
+  /* Select the system clock source (probably the PLL) */
+
+  regval  = getreg32(STM32_RCC_CFGR);
+  regval &= ~RCC_CFGR_SW_MASK;
+  regval |= STM32_SYSCLK_SW;
+  putreg32(regval, STM32_RCC_CFGR);
+
+  /* Wait until the selected source is used as the system clock source */
+
+  while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != STM32_SYSCLK_SWS);
+
+#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
+  /* Low speed internal clock source LSI
+   *
+   * TODO: There is another case where the LSI needs to
+   * be enabled: if the MCO pin selects LSI as source.
+   */
+
+  stm32_rcc_enablelsi();
+#endif
+
+#if defined(CONFIG_RTC_LSECLOCK)
+  /* Low speed external clock source LSE
+   *
+   * TODO: There is another case where the LSE needs to
+   * be enabled: if the MCO pin selects LSE as source.
+   *
+   * TODO: There is another case where the LSE needs to
+   * be enabled: if USARTx selects LSE as source.
+   */
+
+  stm32_rcc_enablelse();
+#endif
+}
+#endif
+
+/****************************************************************************
+ * Name: rcc_enableperiphals
+ ****************************************************************************/
+
+static inline void rcc_enableperipherals(void)
+{
+  rcc_enableahb();
+  rcc_enableapb2();
+  rcc_enableapb1();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/