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arch/risc-v: Refine riscv_cpuindex.c

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2022-01-15 17:42:21 +08:00 committed by Xiang Xiao
parent 56a95ad0b5
commit 3200c936cc
2 changed files with 6 additions and 6 deletions
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6
arch/risc-v/src/k210/k210_cpuindex.c → arch/risc-v/src/common/riscv_cpuindex.c
View File

@ -1,5 +1,5 @@
/****************************************************************************
* arch/risc-v/src/k210/k210_cpuindex.c
* arch/risc-v/src/common/riscv_cpuindex.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@ -28,8 +28,6 @@
#include "riscv_arch.h"
#ifdef CONFIG_SMP
/****************************************************************************
* Public Functions
****************************************************************************/
@ -57,5 +55,3 @@ int up_cpu_index(void)
asm volatile ("csrr %0, mhartid": "=r" (mhartid));
return mhartid;
}
#endif /* CONFIG_SMP */

6
arch/risc-v/src/k210/Make.defs
View File

@ -35,6 +35,10 @@ CMN_CSRCS += riscv_releasestack.c riscv_stackframe.c riscv_schedulesigaction.c
CMN_CSRCS += riscv_sigdeliver.c riscv_unblocktask.c riscv_usestack.c
CMN_CSRCS += riscv_mdelay.c riscv_copyfullstate.c
ifeq ($(CONFIG_SMP), y)
CMN_CSRCS += riscv_cpuindex.c
endif
ifeq ($(CONFIG_SCHED_BACKTRACE),y)
CMN_CSRCS += riscv_backtrace.c
endif
@ -54,7 +58,7 @@ CHIP_CSRCS += k210_lowputc.c k210_serial.c k210_fpioa.c
CHIP_CSRCS += k210_start.c k210_timerisr.c k210_gpiohs.c
ifeq ($(CONFIG_SMP), y)
CHIP_CSRCS += k210_cpuidlestack.c k210_cpuindex.c
CHIP_CSRCS += k210_cpuidlestack.c
CHIP_CSRCS += k210_cpupause.c k210_cpustart.c
endif