From 329db99e512e9d2884dd836931960cce4174ae7a Mon Sep 17 00:00:00 2001 From: Abdelatif Guettouche Date: Tue, 8 Mar 2022 10:21:02 +0100 Subject: [PATCH] arch/xtensa: Use `rsync` around manipulating interrupt registers and replace `isync` by `rsync` in other places. Signed-off-by: Abdelatif Guettouche --- arch/xtensa/include/irq.h | 4 +++- arch/xtensa/include/syscall.h | 14 +++++++------- arch/xtensa/src/common/xtensa_context.S | 2 +- arch/xtensa/src/common/xtensa_cpuint.S | 2 ++ 4 files changed, 13 insertions(+), 9 deletions(-) diff --git a/arch/xtensa/include/irq.h b/arch/xtensa/include/irq.h index cf99de03d4..9c00ba6a00 100644 --- a/arch/xtensa/include/irq.h +++ b/arch/xtensa/include/irq.h @@ -213,7 +213,7 @@ static inline void up_irq_restore(uint32_t ps) { __asm__ __volatile__ ( - "wsr %0, PS \n" + "wsr %0, PS\n" "rsync \n" : : "r"(ps) @@ -276,6 +276,7 @@ static inline void xtensa_disable_all(void) ( "movi a2, 0\n" "xsr a2, INTENABLE\n" + "rsync\n" : : : "a2" ); } @@ -289,6 +290,7 @@ static inline void xtensa_intclear(uint32_t mask) __asm__ __volatile__ ( "wsr %0, INTCLEAR\n" + "rsync\n" : : "r"(mask) : diff --git a/arch/xtensa/include/syscall.h b/arch/xtensa/include/syscall.h index 0c0236f300..1fdf664314 100644 --- a/arch/xtensa/include/syscall.h +++ b/arch/xtensa/include/syscall.h @@ -176,7 +176,7 @@ static inline uintptr_t sys_call0(unsigned int nbr) ( "movi a3, %1\n" "wsr a3, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0) : "a3", "memory" @@ -202,7 +202,7 @@ static inline uintptr_t sys_call1(unsigned int nbr, uintptr_t parm1) ( "movi a4, %1\n" "wsr a4, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1) : "a4", "memory" @@ -230,7 +230,7 @@ static inline uintptr_t sys_call2(unsigned int nbr, uintptr_t parm1, ( "movi a5, %1\n" "wsr a5, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2) : "a5", "memory" @@ -259,7 +259,7 @@ static inline uintptr_t sys_call3(unsigned int nbr, uintptr_t parm1, ( "movi a6, %1\n" "wsr a6, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3) @@ -291,7 +291,7 @@ static inline uintptr_t sys_call4(unsigned int nbr, uintptr_t parm1, ( "movi a7, %1\n" "wsr a7, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3), "r"(reg4) @@ -324,7 +324,7 @@ static inline uintptr_t sys_call5(unsigned int nbr, uintptr_t parm1, ( "movi a8, %1\n" "wsr a8, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3), "r"(reg4), "r"(reg5) @@ -359,7 +359,7 @@ static inline uintptr_t sys_call6(unsigned int nbr, uintptr_t parm1, ( "movi a9, %1\n" "wsr a9, intset\n" - "isync\n" + "rsync\n" : "=r"(reg0) : "i"(XCHAL_SWINT_CALL), "r"(reg0), "r"(reg1), "r"(reg2), "r"(reg3), "r"(reg4), "r"(reg5) diff --git a/arch/xtensa/src/common/xtensa_context.S b/arch/xtensa/src/common/xtensa_context.S index 6885d4aeae..c1198be6b0 100644 --- a/arch/xtensa/src/common/xtensa_context.S +++ b/arch/xtensa/src/common/xtensa_context.S @@ -548,7 +548,7 @@ xtensa_context_restore: movi a2, SYS_restore_context movi a4, XCHAL_SWINT_CALL wsr a4, intset - isync + rsync RET(16) diff --git a/arch/xtensa/src/common/xtensa_cpuint.S b/arch/xtensa/src/common/xtensa_cpuint.S index da60961b84..cdfb604d04 100644 --- a/arch/xtensa/src/common/xtensa_cpuint.S +++ b/arch/xtensa/src/common/xtensa_cpuint.S @@ -82,6 +82,7 @@ xtensa_enable_cpuint: s32i a5, a2, 0 /* shadow |= mask */ wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */ + rsync mov a3, a4 /* Return previous shadow content */ RET(16) @@ -122,6 +123,7 @@ xtensa_disable_cpuint: s32i a5, a2, 0 /* shadow &= ~mask */ wsr a5, INTENABLE /* Set CPU INTENABLE to shadow */ + rsync mov a3, a4 /* Return previous shadow content */ RET(16)