Add RCC support

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2101 42af7a65-404d-4744-a932-0658087f49c3

configs/stm3210e-eval/include/board.h

@@ -44,6 +44,7 @@
 #ifndef __ASSEMBLY__
 # include <sys/types.h>
 #endif
+#include "stm32_rcc.h"
 #include "stm32_internal.h"
 
 /************************************************************************************
@@ -52,10 +53,41 @@
 
 /* Clocking *************************************************************************/
 
-# warning "These frequencies are still needed"
+/* On-board crystal frequency is 8MHz (HSE) */
-#define SYSCLK_FREQUENCY 1
+
-#define STM32_PCLK1_FREQUENCY 1
+#define STM32_BOARD_XTAL       8000000ul
-#define STM32_PCLK2_FREQUENCY 1
+
+/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
+
+#define STM32_CFGR_PLLSRC      RCC_CFGR_PLLSRC
+#define STM32_CFGR_PLLXTPRE    0
+#define STM32_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx9
+#define STM32_PLL_FREQUENCY    (9*STM32_BOARD_XTAL)
+
+/* Use the PLL and set the SYSCLK source to be the PLL */
+
+#define STM32_SYSCLK_SW        RCC_CFGR_SW_PLL
+#define STM32_SYSCLK_SWS       RCC_CFGR_SWS_PLL
+#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
+
+/* AHB clock (HCLK) is SYSCLK (72MHz) */
+
+#define STM32_RCC_CFGR_HPRE    RCC_CFGR_HPRE_SYSCLK
+#define STM32_HCLK_FREQUENCY   STM32_PLL_FREQUENCY
+
+/* APB2 clock (PCLK2) is HCLK (72MHz) */
+
+#define STM32_RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_HCLK
+#define STM32_PCLK_FREQUENCY   STM32_HCLK_FREQUENCY
+
+/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
+
+#define STM32_RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_HCLKd2
+#define STM32_PCLK1_FREQUENCY  (STM32_HCLK_FREQUENCY/2)
+
+/* USB divider */
+
+#define STM32_CFGR_USBPRE      0
 
 /* LED definitions ******************************************************************/