m9s12x context save structure
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3298 42af7a65-404d-4744-a932-0658087f49c3
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@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/hc/include/hcs12/irq.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -50,6 +50,79 @@
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/************************************************************************************
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* Register state save strucure
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* Low Address <-- SP after state save
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* [PPAGE]
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* [soft regisers]
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* XYH
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* XYL
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* ZH
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* ZL
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* TMPH
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* TMPL
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* FRAMEH
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* FRAMEL <-- SP after interrupt
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* CCR
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* B
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* A
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* XH
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* XL
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* YH
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* YL
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* PCH
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* High Address PCL <-- SP before interrupt
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*
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************************************************************************************/
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/* Byte offsets */
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#ifndef CONFIG_HCS12_NONBANKED
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# define REG_PPAGE 0
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# define REG_FIRST_SOFTREG 1
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#else
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# define REG_FIRST_SOFTREG 0
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#endif
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#if CONFIG_HCS12_MSOFTREGS > 2
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# error "Need to save more registers"
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#elif CONFIG_HCS12_MSOFTREGS == 2
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# define REG_SOFTREG1 REG_FIRST_SOFTREG
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# define REG_SOFTREG2 (REG_FIRST_SOFTREG+2)
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# define REG_FIRST_HARDREG (REG_FIRST_SOFTREG+4)
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#elif CONFIG_HCS12_MSOFTREGS == 1
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# define REG_SOFTREG1 REG_FIRST_SOFTREG
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# define REG_FIRST_HARDREG (REG_FIRST_SOFTREG+2)
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#else
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# define REG_FIRST_HARDREG REG_FIRST_SOFTREG
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#endif
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#define REG_XY REG_FIRST_HARDREG
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#define REG_Z (REG_FIRST_HARDREG+2)
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# define REG_ZH (REG_FIRST_HARDREG+2)
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# define REG_ZL (REG_FIRST_HARDREG+3)
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#define REG_TMP (REG_FIRST_HARDREG+4)
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# define REG_TMPH (REG_FIRST_HARDREG+4)
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# define REG_TMPL (REG_FIRST_HARDREG+5)
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#define REG_FRAME (REG_FIRST_HARDREG+6)
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# define REG_FRAMEH (REG_FIRST_HARDREG+6)
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# define REG_FRAMEL (REG_FIRST_HARDREG+7)
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#define REG_CCR (REG_FIRST_HARDREG+8)
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#define REG_BA (REG_FIRST_HARDREG+9)
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# define REG_B (REG_FIRST_HARDREG+9)
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# define REG_A (REG_FIRST_HARDREG+10)
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#define REG_X (REG_FIRST_HARDREG+11)
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# define REG_XH (REG_FIRST_HARDREG+11)
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# define REG_XL (REG_FIRST_HARDREG+12)
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#define REG_Y (REG_FIRST_HARDREG+13)
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# define REG_YH (REG_FIRST_HARDREG+13)
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# define REG_YL (REG_FIRST_HARDREG+14)
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#define REG_PC (REG_FIRST_HARDREG+15)
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# define REG_PCH (REG_FIRST_HARDREG+15)
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# define REG_PCL (REG_FIRST_HARDREG+16)
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#define XCPTCONTEXT_REGS (REG_FIRST_HARDREG+17)
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/************************************************************************************
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* Public Types
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@ -60,7 +133,7 @@
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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int dummy; /* For now */
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uint8_t regs[XCPTCONTEXT_REGS];
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};
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/****************************************************************************
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@ -2,7 +2,7 @@
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* arch/hc/src/m9s12/m9s12_vectors.S
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* arch/hc/src/chip/m9s12_vectors.S
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -56,8 +56,24 @@
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* Macros
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************************************************************************************/
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/* On entry into an I- or X-interrupt, into an SWI, or into an undefined instruction
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* interrupt, the stack frame created by hardware looks like:
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*
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* Low Address <-- SP after interrupt
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* CCR
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* B
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* A
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* XH
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* XL
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* YH
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* YL
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* PCH
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* High Address PCL <-- SP before interrupt
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*/
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.macro HANDLER, label, irqno
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\label:
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#warning "Missing Logic"
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.endm
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/************************************************************************************
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@ -189,11 +205,83 @@ handlers:
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* Common IRQ handling logic
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*
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* Description:
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* To be provided
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* On entry into an I- or X-interrupt, into an SWI, or into an undefined
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* instruction interrupt, the stack frame created by hardware looks like:
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*
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* Low Address <-- SP after state save
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* [PPAGE]
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* [soft regisers]
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* XYH
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* XYL
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* ZH
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* ZL
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* TMPH
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* TMPL
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* FRAMEH
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* FRAMEL <-- SP after interrupt
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* CCR
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* B
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* A
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* XH
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* XL
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* YH
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* YL
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* PCH
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* High Address PCL <-- SP before interrupt
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*
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************************************************************************************/
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vcommon:
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/* Save the rest of the frame */
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movw _.frame, 2, -sp
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movw _.tmp, 2, -sp
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movw _.z, 2, -sp
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movw _.xy, 2, -sp
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/* Save the soft registers */
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#if CONFIG_HCS12_MSOFTREGS > 2
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# error "Need to save more registers"
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#endif
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#if CONFIG_HCS12_MSOFTREGS > 1
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movw _.d2, 2, -sp
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#endif
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#if CONFIG_HCS12_MSOFTREGS > 0
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movw _.d1, 2, -sp
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#endif
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/* Save the PPAGE register */
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#ifndef CONFIG_HCS12_NONBANKED
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movb HCS12_MMC_PPAGE, 1, -sp
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#endif
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/* Handle the IRQ */
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#warning "Missing Logic"
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/* Restore registers and return */
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/* Restore the PPAGE register */
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#ifndef CONFIG_HCS12_NONBANKED
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movb 1, sp+, HCS12_MMC_PPAGE
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#endif
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/* Restore the soft registers */
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#if CONFIG_HCS12_MSOFTREGS > 0
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movw 2, sp+, _.d1
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#endif
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#if CONFIG_HCS12_MSOFTREGS > 1
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movw 2, sp+, _.d2
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#endif
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movw 2, sp+, _.xy
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movw 2, sp+, _.z
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movw 2, sp+, _.tmp
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movw 2, sp+, _.frame
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rti
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.size handlers, .-handlers
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/************************************************************************************
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@ -203,7 +291,8 @@ vcommon:
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* Name: up_interruptstack/g_userstack
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*
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* Description:
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* Shouldn't happen
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* If CONFIG_ARCH_INTERRUPTSTACK is defined, this sets aside memory for the
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* interrupt stack.
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*
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************************************************************************************/
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