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arch: arm: stm32, stm32h7, stm32l5: Fix typos in KConfig help texts

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arch/arm/src/stm32/Kconfig:
* In configs STM32_ADC_MAX_SAMPLES, STM32_FOC_HAS_PWM_COMPLEMENTARY:
  Fix typos in help text.

arch/arm/src/stm32h7/Kconfig:
* In configs STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY,
  STM32H7_FLASH_CR_PSIZE, STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY,
  and STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY: Fix typos in help text.

arch/arm/src/stm32l5/Kconfig:
* In configs STM32L5_FLOWCONTROL_BROKEN, STM32L5_SDMMC1_DMAPRIO: Fix
  typos in help text.
This commit is contained in:
Nathan Hartman 2021-07-23 16:21:55 -04:00 committed by Gustavo Henrique Nihei
parent 5500dcdf64
commit 3346ba304b
3 changed files with 19 additions and 20 deletions
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4
arch/arm/src/stm32/Kconfig
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@ -8244,7 +8244,7 @@ config STM32_ADC_MAX_SAMPLES
responsibility to correctly select this value.
Since the interfece to update the sampling time is available
for all supported devices, the user can change the default
vaules in the board initialization logic and avoid ADC overrun.
values in the board initialization logic and avoid ADC overrun.
config STM32_ADC_NO_STARTUP_CONV
bool "Do not start conversion when opening ADC device"
@ -11258,7 +11258,7 @@ config STM32_FOC_HAS_PWM_COMPLEMENTARY
---help---
Enable complementary outputs for the FOC PWM (sometimes called 6-PWM mode)
# hiden variables and automatic configuration
# hidden variables and automatic configuration
config STM32_FOC_USE_TIM1
bool

31
arch/arm/src/stm32h7/Kconfig
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@ -303,7 +303,7 @@ config STM32H7_FLASH_CR_PSIZE
range 0 3
---help---
On some hardware the fastest 64 bit wide flash writes cause too
high power consumption which may compromize the system stability.
high power consumption which may compromise the system stability.
This option can be used to reduce the program size. The options are:
0: 8 bits
1: 16 bits
@ -1565,18 +1565,18 @@ config STM32H7_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
bool "Automatically boost the LSE oscillator drive capability level until it starts-up"
default n
---help---
This will cycle through the correct* values from low to high. To avoid
damaging the the crystal. We want to use the lowest setting that gets
the OSC running. See app note AN2867
This will cycle through the correct* values from low to high. To
avoid damaging the crystal, we want to use the lowest setting that
gets the OSC running. See app note AN2867
0 = Low drive capability (default)
1 = Medium low drive capability
2 = Medium high drive capability
3 = High drive capability
*It will take into account the rev of the silicon and use
the correct code points to achive the drive strength.
See Eratta ES0392 Rev 7 2.2.14 LSE oscillator driving capability
*It will take into account the revision of the silicon and use
the correct code points to achieve the drive strength.
See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability
selection bits are swapped.
config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY
@ -1590,9 +1590,9 @@ config STM32H7_RTC_LSECLOCK_START_DRV_CAPABILITY
2 = Medium high drive capability
3 = High drive capability
It will take into account the rev of the silicon and use
the correct code points tp achive the drive strength.
See Eratta ES0392 Rev 7 2.2.14 LSE oscillator driving capability
It will take into account the revision of the silicon and use
the correct code points to achieve the drive strength.
See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability
selection bits are swapped.
config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
@ -1606,14 +1606,13 @@ config STM32H7_RTC_LSECLOCK_RUN_DRV_CAPABILITY
2 = Medium high drive capability
3 = High drive capability
It will take into account the rev of the silicon and use
the correct code points tp achive the drive strength.
See Eratta ES0392 Rev 7 2.2.14 LSE oscillator driving capability
It will take into account the revision of the silicon and use
the correct code points to achieve the drive strength.
See Errata ES0392 Rev 7 2.2.14 LSE oscillator driving capability
selection bits are swapped.
WARNING this RUN setting does not apear to work!
it apears that the LSEDRV bits can not be changes once the OSC
is running.
WARNING this RUN setting does not appear to work! It appears
that the LSEDRV bits cannot be changed once the OSC is running.
endif # STM32H7_RTC_LSECLOCK

4
arch/arm/src/stm32l5/Kconfig
View File

@ -2845,7 +2845,7 @@ config STM32L5_FLOWCONTROL_BROKEN
Enable UART RTS flow control using Software. Because STM
Current STM32 have broken HW based RTS behavior (they assert
nRTS after every byte received) Enable this setting workaround
this issue by useing software based management of RTS
this issue by using software based management of RTS
config STM32L5_USART_BREAKS
bool "Add TIOxSBRK to support sending Breaks"
@ -2989,7 +2989,7 @@ config STM32L5_SDMMC1_DMAPRIO
hex "SDMMC1 DMA priority"
default 0x00001000
---help---
Select SDMMC1 DMA prority.
Select SDMMC1 DMA priority.
Options are: 0x00000000 low, 0x00001000 medium,
0x00002000 high, 0x00003000 very high. Default: medium.