diff --git a/arch/arm/include/armv7-a/spinlock.h b/arch/arm/include/armv7-a/spinlock.h index 5c5d1ae6ac..f43df337b8 100644 --- a/arch/arm/include/armv7-a/spinlock.h +++ b/arch/arm/include/armv7-a/spinlock.h @@ -45,8 +45,11 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Not a useful feature */ -#ifdef CONFIG_SMP +#undef SMP_INTERCPU_NONCACHED + +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* In SMP configurations, save spinlocks and other inter-CPU communications * data in a non-cached memory region. */ diff --git a/arch/arm/src/armv7-a/scu.h b/arch/arm/src/armv7-a/scu.h new file mode 100644 index 0000000000..cd44da392d --- /dev/null +++ b/arch/arm/src/armv7-a/scu.h @@ -0,0 +1,159 @@ +/**************************************************************************** + * arch/arm/src/armv7-a/scu.h + * Generic Interrupt Controller Definitions + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Reference: + * Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI + * 0407I (ID091612). + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_ARMV7_A_SCU_H +#define __ARCH_ARM_SRC_ARMV7_A_SCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "mpcore.h" /* For MPCORE_SCU_VBASE */ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define SCU_CTRL_OFFSET 0x0000 /* SCU Control Register (Implementation defined) */ +#define SCU_CONFIG_OFFSET 0x0004 /* SCU Configuration Register (Implementation defined) */ +#define SCU_PWRSTATUS_OFFSET 0x0008 /* SCU CPU Power Status Register */ +#define SCU_INVALIDATE_OFFSET 0x000c /* SCU Invalidate All Registers in Secure State */ +#define SCU_FILTERSTART_OFFSET 0x0040 /* Filtering Start Address Register Defined by FILTERSTART input */ +#define SCU_FILTEREND_OFFSET 0x0044 /* Filtering End Address Register Defined by FILTEREND input */ +#define SCU_SAC_OFFSET 0x0050 /* SCU Access Control (SAC) Register */ +#define SCU_SNSAC_OFFSET 0x0054 /* SCU Non-secure Access Control (SNSAC) Register */ + +/* Register addresses *******************************************************/ + +#define SCU_CTRL (MPCORE_SCU_VBASE+SCU_CTRL_OFFSET) +#define SCU_CONFIG (MPCORE_SCU_VBASE+SCU_CONFIG_OFFSET) +#define SCU_PWRSTATUS (MPCORE_SCU_VBASE+SCU_PWRSTATUS_OFFSET) +#define SCU_INVALIDATE (MPCORE_SCU_VBASE+SCU_INVALIDATE_OFFSET) +#define SCU_FILTERSTART (MPCORE_SCU_VBASE+SCU_FILTERSTART_OFFSET) +#define SCU_FILTEREND (MPCORE_SCU_VBASE+SCU_FILTEREND_OFFSET) +#define SCU_SAC (MPCORE_SCU_VBASE+SCU_SAC_OFFSET) +#define SCU_SNSAC (MPCORE_SCU_VBASE+SCU_SNSAC_OFFSET) + +/* Register bit-field definitions *******************************************/ + +/* SCU Control Register (Implementation defined) */ + +#define SCU_CTRL_ENABLE (1 << 0) /* SCU enable */ +#define SCU_CTRL_ADDRFILTER (1 << 1) /* Address filtering enable */ +#define SCU_CTRL_RAMPARITY (1 << 2) /* SCU RAMs parity enable */ +#define SCU_CTRL_LINFILL (1 << 3) /* SCU speculative linefill enable */ +#define SCU_CTRL_PORT0 (1 << 4) /* Force all device to port0 enable */ +#define SCU_CTRL_STANDBY (1 << 5) /* SCU standby enable */ +#define SCU_CTRL_ICSTANDBY (1 << 6) /* IC standby enable */ + +/* SCU Configuration Register (Implementation defined) */ + +#define SCU_CONFIG_NCPUS_SHIFT 0 /* CPU number Number of CPUs present */ +#define SCU_CONFIG_NCPUS_MASK (3 << SCU_CONFIG_NCPUS_SHIFT) +# define SCU_CONFIG_NCPUS(r) ((((uint32_t)(r) & SCU_CONFIG_NCPUS_MASK) >> SCU_CONFIG_NCPUS_SHIFT) + 1) +#define SCU_CONFIG_SMPCPUS_SHIFT 4 /* Processors that are in SMP or AMP mode */ +#define SCU_CONFIG_SMPCPUS_MASK (15 << SCU_CONFIG_SMPCPUS_SHIFT) +# define SCU_CONFIG_CPU0_SMP (1 << 4) +# define SCU_CONFIG_CPU1_SMP (1 << 5) +# define SCU_CONFIG_CPU2_SMP (1 << 6) +# define SCU_CONFIG_CPU3_SMP (1 << 7) + +#define SCU_CONFIG_TAGRAM_16KB 0 +#define SCU_CONFIG_TAGRAM_32KB 1 +#define SCU_CONFIG_TAGRAM_64KB 2 + +#define SCU_CONFIG_CPU0_TAGRAM_SHIFT 8 /* CPU 0 tag RAM size */ +#define SCU_CONFIG_CPU0_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) +#define SCU_CONFIG_CPU1_TAGRAM_SHIFT 10 /* CPU 1 tag RAM size */ +#define SCU_CONFIG_CPU1_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) +#define SCU_CONFIG_CPU2_TAGRAM_SHIFT 12 /* CPU 1 tag RAM size */ +#define SCU_CONFIG_CPU2_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) +#define SCU_CONFIG_CPU3_TAGRAM_SHIFT 14 /* CPU 1 tag RAM size */ +#define SCU_CONFIG_CPU3_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT) + +/* SCU CPU Power Status Register */ + +#define SCU_PWRSTATUS_NORMAL 0 +#define SCU_PWRSTATUS_DORMANT 2 +#define SCU_PWRSTATUS_PWROFF 3 + +#define SCU_PWRSTATUS_CPU0_SHIFT 0 /* CPU0 status Power status */ +#define SCU_PWRSTATUS_CPU0_MASK (3 << SCU_PWRSTATUS_CPU0_SHIFT) +#define SCU_PWRSTATUS_CPU1_SHIFT 8 /* CPU1 status Power status */ +#define SCU_PWRSTATUS_CPU1_MASK (3 << SCU_PWRSTATUS_CPU1_SHIFT) +#define SCU_PWRSTATUS_CPU2_SHIFT 16 /* CPU2 status Power status */ +#define SCU_PWRSTATUS_CPU2_MASK (3 << SCU_PWRSTATUS_CPU2_SHIFT) +#define SCU_PWRSTATUS_CPU3_SHIFT 24 /* CPU3 status Power status */ +#define SCU_PWRSTATUS_CPU3_MASK (3 << SCU_PWRSTATUS_CPU3_SHIFT) + +/* SCU Invalidate All Registers in Secure State */ + +#define SCU_INVALIDATE_CPU0_SHIFT 0 /* Ways that must be invalidated for CPU0 */ +#define SCU_INVALIDATE_CPU0_MASK (15 << SCU_INVALIDATE_CPU0_SHIFT) +#define SCU_INVALIDATE_CPU1_SHIFT 4 /* Ways that must be invalidated for CPU1 */ +#define SCU_INVALIDATE_CPU1_MASK (15 << SCU_INVALIDATE_CPU1_SHIFT) +#define SCU_INVALIDATE_CPU2_SHIFT 8 /* Ways that must be invalidated for CPU2 */ +#define SCU_INVALIDATE_CPU2_MASK (15 << SCU_INVALIDATE_CPU2_SHIFT) +#define SCU_INVALIDATE_CPU3_SHIFT 12 /* Ways that must be invalidated for CPU3 */ +#define SCU_INVALIDATE_CPU3_MASK (15 << SCU_INVALIDATE_CPU3_SHIFT) + +/* Filtering Start Address Register Defined by FILTERSTART input */ + +#define SCU_FILTERSTART_SHIFT 10 /* Filtering start address */ +#define SCU_FILTERSTART_MASK (0xfff << SCU_FILTERSTART_SHIFT) + +/* Filtering End Address Register Defined by FILTEREND input */ + +#define SCU_FILTEREND_SHIFT 10 /* Filtering start address */ +#define SCU_FILTEREND_MASK (0xfff << SCU_FILTEREND_SHIFT) + +/* SCU Access Control (SAC) Register */ + +#define SCU_SAC_CPU(n) (1 << (n)) /* CPUn may access components */ + +/* SCU Non-secure Access Control (SNSAC) Register */ + +#define SCU_SNSAC_COMP_CPU(n) (1 << (n)) /* CPUn has non-secure access to components */ +#define SCU_SNSAC_PTIM_CPU(n) (1 << ((n)+4)) /* CPUn has non-secure access to private timers */ +#define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */ + +#endif /* __ARCH_ARM_SRC_ARMV7_A_SCU_H */ diff --git a/arch/arm/src/imx6/chip/imx_memorymap.h b/arch/arm/src/imx6/chip/imx_memorymap.h index 38632b9a22..17304c2474 100644 --- a/arch/arm/src/imx6/chip/imx_memorymap.h +++ b/arch/arm/src/imx6/chip/imx_memorymap.h @@ -959,7 +959,7 @@ # define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE) # define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE) -# ifdef CONFIG_SMP +# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002400 @@ -984,7 +984,7 @@ * cacheable, inter-processor communication data. */ -# ifdef CONFIG_SMP +# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Paging L2 page table offset/size */ # define PGTABLE_L2_OFFSET 0x000002000 @@ -1013,7 +1013,7 @@ #define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE) #define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE) -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Non-cached inter-processor communication data */ # define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE) @@ -1061,7 +1061,7 @@ # define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE # define IMX_VECTOR_VADDR 0x00000000 -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Inter-processor communications. * * NOTICE that we use the unused virtual address space at 0x00400000 for @@ -1089,7 +1089,7 @@ # define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE) # define IMX_VECTOR_VADDR 0xffff0000 -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Inter-processor communications * * NOTICE that we use the unused virtual address space at 0x00400000 for diff --git a/arch/arm/src/imx6/imx_boot.c b/arch/arm/src/imx6/imx_boot.c index 59ccb8ac06..eb731a3315 100644 --- a/arch/arm/src/imx6/imx_boot.c +++ b/arch/arm/src/imx6/imx_boot.c @@ -233,7 +233,7 @@ static void imx_vectormapping(void) * ****************************************************************************/ -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) static void imx_intercpu_mapping(void) { uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK; @@ -433,7 +433,7 @@ void arm_boot(void) #if defined(CONFIG_ARCH_RAMFUNCS) const uint32_t *src; #endif -#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP) +#if defined(CONFIG_ARCH_RAMFUNCS) || defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) uint32_t *dest; #endif @@ -458,7 +458,7 @@ void arm_boot(void) imx_vectormapping(); imx_lowputc('B'); -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Provide a special mapping for the OCRAM interrupt vector positioned in * high memory. */ @@ -545,7 +545,7 @@ void arm_boot(void) imx_lowputc('L'); #endif -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED) /* Initialize the uncached, inter-CPU communications area */ for (dest = &_snocache; dest < &_enocache; )