diff --git a/arch/arm/src/armv7-m/arm_systemreset.c b/arch/arm/src/armv7-m/arm_systemreset.c
index 2228fcbf6d..0710744bc7 100644
--- a/arch/arm/src/armv7-m/arm_systemreset.c
+++ b/arch/arm/src/armv7-m/arm_systemreset.c
@@ -53,7 +53,7 @@ void up_systemreset(void)
    */
 
   regval  = getreg32(NVIC_AIRCR) & NVIC_AIRCR_PRIGROUP_MASK;
-  regval |= ((0x5fa << NVIC_AIRCR_VECTKEY_SHIFT) | NVIC_AIRCR_SYSRESETREQ);
+  regval |= (NVIC_AIRCR_VECTKEY | NVIC_AIRCR_SYSRESETREQ);
   putreg32(regval, NVIC_AIRCR);
 
   /* Ensure completion of memory accesses */
diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h
index 40299630f1..265292ff0d 100644
--- a/arch/arm/src/armv7-m/nvic.h
+++ b/arch/arm/src/armv7-m/nvic.h
@@ -559,8 +559,10 @@
 #define NVIC_AIRCR_ENDIANNESS           (1 << 15) /* Bit 15: 1=Big endian */
 #define NVIC_AIRCR_VECTKEY_SHIFT        (16)      /* Bits 16-31: VECTKEY */
 #define NVIC_AIRCR_VECTKEY_MASK         (0xffff << NVIC_AIRCR_VECTKEY_SHIFT)
+#define NVIC_AIRCR_VECTKEY              (0x05fa << NVIC_AIRCR_VECTKEY_SHIFT)
 #define NVIC_AIRCR_VECTKEYSTAT_SHIFT    (16)      /* Bits 16-31: VECTKEYSTAT */
 #define NVIC_AIRCR_VECTKEYSTAT_MASK     (0xffff << NVIC_AIRCR_VECTKEYSTAT_SHIFT)
+#define NVIC_AIRCR_VECTKEYSTAT          (0xfa05 << NVIC_AIRCR_VECTKEYSTAT_SHIFT)
 
 /* System handler control and state register (SYSHCON) */
 
diff --git a/arch/arm/src/armv8-m/arm_systemreset.c b/arch/arm/src/armv8-m/arm_systemreset.c
index 05969e1ce9..567ecd0f9f 100644
--- a/arch/arm/src/armv8-m/arm_systemreset.c
+++ b/arch/arm/src/armv8-m/arm_systemreset.c
@@ -53,7 +53,7 @@ void up_systemreset(void)
    */
 
   regval  = getreg32(NVIC_AIRCR) & NVIC_AIRCR_PRIGROUP_MASK;
-  regval |= ((0x5fa << NVIC_AIRCR_VECTKEY_SHIFT) | NVIC_AIRCR_SYSRESETREQ);
+  regval |= (NVIC_AIRCR_VECTKEY | NVIC_AIRCR_SYSRESETREQ);
   putreg32(regval, NVIC_AIRCR);
 
   /* Ensure completion of memory accesses */
diff --git a/arch/arm/src/armv8-m/nvic.h b/arch/arm/src/armv8-m/nvic.h
index 7817195ace..fb350e0d1f 100644
--- a/arch/arm/src/armv8-m/nvic.h
+++ b/arch/arm/src/armv8-m/nvic.h
@@ -578,8 +578,10 @@
 #define NVIC_AIRCR_ENDIANNESS           (1 << 15) /* Bit 15: 1=Big endian */
 #define NVIC_AIRCR_VECTKEY_SHIFT        (16)      /* Bits 16-31: VECTKEY */
 #define NVIC_AIRCR_VECTKEY_MASK         (0xffff << NVIC_AIRCR_VECTKEY_SHIFT)
+#define NVIC_AIRCR_VECTKEY              (0x05fa << NVIC_AIRCR_VECTKEY_SHIFT)
 #define NVIC_AIRCR_VECTKEYSTAT_SHIFT    (16)      /* Bits 16-31: VECTKEYSTAT */
 #define NVIC_AIRCR_VECTKEYSTAT_MASK     (0xffff << NVIC_AIRCR_VECTKEYSTAT_SHIFT)
+#define NVIC_AIRCR_VECTKEYSTAT          (0xfa05 << NVIC_AIRCR_VECTKEYSTAT_SHIFT)
 
 /* System handler control and state register (SYSHCON) */
 
diff --git a/arch/arm/src/rtl8720c/ameba_nvic.c b/arch/arm/src/rtl8720c/ameba_nvic.c
index 6947a87f00..0366ba567f 100644
--- a/arch/arm/src/rtl8720c/ameba_nvic.c
+++ b/arch/arm/src/rtl8720c/ameba_nvic.c
@@ -401,7 +401,7 @@ void up_irqinitialize(void)
    */
 
   modifyreg32(NVIC_AIRCR, NVIC_AIRCR_VECTKEY_MASK | NVIC_AIRCR_PRIGROUP_MASK,
-  (0x5fa << NVIC_AIRCR_VECTKEY_SHIFT) | (0x5 << NVIC_AIRCR_PRIGROUP_SHIFT));
+              NVIC_AIRCR_VECTKEY | (0x5 << NVIC_AIRCR_PRIGROUP_SHIFT));
 
   /* Set all interrupts (and exceptions) to the default priority */