arch: lc823450: Fix style violations
Summary: - Fix style violations under lc823450 - NOTE: still some files need to be fixed Impact: - Some register naming were changed but all files are included Testing: - Build check only Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa
Xiang Xiao
parent
22a9b497b1
commit
336bd8c3a2
@ -66,15 +66,15 @@
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#define IPICLR_INTISR1_CLR_2 (0x1 << 10)
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#define IPICLR_INTISR1_CLR_3 (0x1 << 11)
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#define EXTINTn_BASE (LC823450_INTC_REGBASE + 0x400)
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#define EXTINTnS_BASE (LC823450_INTC_REGBASE + 0x418)
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#define EXTINTnM_BASE (LC823450_INTC_REGBASE + 0x430)
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#define EXTINTnC0_BASE (LC823450_INTC_REGBASE + 0x448)
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#define EXTINTnC1_BASE (LC823450_INTC_REGBASE + 0x460)
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#define EXTINTnCND_BASE (LC823450_INTC_REGBASE + 0x478)
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#define EXTINTnCLR_BASE (LC823450_INTC_REGBASE + 0x490)
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#define EXTINTnFEN_BASE (LC823450_INTC_REGBASE + 0x4A8)
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#define EXTINTnSET_BASE (LC823450_INTC_REGBASE + 0x4C0)
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#define EXTINT_BASE (LC823450_INTC_REGBASE + 0x400)
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#define EXTINTS_BASE (LC823450_INTC_REGBASE + 0x418)
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#define EXTINTM_BASE (LC823450_INTC_REGBASE + 0x430)
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#define EXTINTC0_BASE (LC823450_INTC_REGBASE + 0x448)
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#define EXTINTC1_BASE (LC823450_INTC_REGBASE + 0x460)
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#define EXTINTCND_BASE (LC823450_INTC_REGBASE + 0x478)
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#define EXTINTCLR_BASE (LC823450_INTC_REGBASE + 0x490)
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#define EXTINTFEN_BASE (LC823450_INTC_REGBASE + 0x4A8)
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#define EXTINTSET_BASE (LC823450_INTC_REGBASE + 0x4C0)
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#define INTC_REG(base,port) ((base) + 4 * (port))
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@ -119,7 +119,8 @@ static struct
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uint32_t size;
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uint32_t enc;
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uint32_t offset;
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} chunk[10];
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}
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chunk[10];
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} upg_image;
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/****************************************************************************
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@ -192,7 +193,10 @@ static int blk_write(const void *buf, int len, const char *path, int offset)
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static int install_recovery(const char *srcpath)
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{
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int rfd, i, len, rem;
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int rfd;
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int i;
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int len;
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int rem;
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int ret = 0;
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void *handle = NULL;
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@ -223,7 +227,6 @@ static int install_recovery(const char *srcpath)
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sysreset();
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/* NOT REACHED */
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}
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#endif
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@ -308,7 +311,6 @@ static void load_kernel(const char *name, const char *devname)
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"ldr sp, [r1, #0]\n" /* set sp */
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"ldr pc, [r1, #4]" /* set pc, start nuttx */
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);
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}
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/****************************************************************************
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@ -377,18 +379,18 @@ static int check_forceusbboot(void)
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/* start ADC0,1 */
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putreg32(rADCCTL_fADCNVCK_DIV32 | rADCCTL_fADACT | rADCCTL_fADCHSCN |
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1 /* 0,1 ch */, rADCCTL);
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putreg32(ADCCTL_ADCNVCK_DIV32 | ADCCTL_ADACT | ADCCTL_ADCHSCN |
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1 /* 0,1 ch */, ADCCTL);
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putreg32(53, rADCSMPL);
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putreg32(53, ADCSMPL);
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/* wait for adc done */
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while ((getreg32(rADCSTS) & rADCSTS_fADCMPL) == 0)
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while ((getreg32(ADCSTS) & ADCSTS_ADCMPL) == 0)
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;
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val = getreg32(rADC0DT);
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val1 = getreg32(rADC1DT);
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val = getreg32(ADC0DT);
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val1 = getreg32(ADC1DT);
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_info("val = %d, val1 = %d\n", val, val1);
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@ -399,21 +401,21 @@ static int check_forceusbboot(void)
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/* check KEY0_AD_D key pressed */
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if (val >= (0x3A << 2) && val < (0x57 << 2))
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if (val >= (0x3a << 2) && val < (0x57 << 2))
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{
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return 1;
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}
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/* check KEY0_AD_B key pressed */
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if (val >= (0x0B << 2) && val < (0x20 << 2))
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if (val >= (0x0b << 2) && val < (0x20 << 2))
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{
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return 1;
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}
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/* check KEY1_AD_B key pressed */
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if (val1 >= (0x0B << 2) && val1 < (0x20 << 2))
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if (val1 >= (0x0b << 2) && val1 < (0x20 << 2))
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{
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return 1;
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}
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@ -495,11 +497,11 @@ static void chg_disable(void)
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/* I2C pinmux */
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modifyreg32(PMDCNT0, 0x0003C000, 0x00014000);
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modifyreg32(PMDCNT0, 0x0003c000, 0x00014000);
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/* I2C drv : 4mA */
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modifyreg32(PTDRVCNT0, 0x0003C000, 0x0003C000);
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modifyreg32(PTDRVCNT0, 0x0003c000, 0x0003c000);
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/* Enable I2C controller */
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@ -612,6 +614,7 @@ static int msc_enable(int forced)
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_info("Install recovery\n");
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/* clear old MBR */
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memset(copybuf, 0, sizeof(copybuf));
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set_config(0, copybuf);
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}
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@ -625,6 +628,7 @@ static int msc_enable(int forced)
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sysreset();
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/* not reached */
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return 0;
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}
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#endif
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@ -749,7 +753,6 @@ int ipl2_main(int argc, char *argv[])
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install_recovery("/mnt/sd0/UPG.IMG");
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load_kernel("recovery", CONFIG_MTD_RECOVERY_DEVPATH);
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}
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else
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{
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@ -304,7 +304,7 @@ static void lc823450_extint_clr(int irq)
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port = (irq & 0x70) >> 4;
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pin = irq & 0xf;
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regaddr = INTC_REG(EXTINTnCLR_BASE, port);
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regaddr = INTC_REG(EXTINTCLR_BASE, port);
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putreg32(1 << pin, regaddr);
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return;
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@ -330,12 +330,12 @@ static int lc823450_extint_isr(int irq, FAR void *context, FAR void *arg)
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/* Read irq factor */
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regaddr = INTC_REG(EXTINTn_BASE, port);
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regaddr = INTC_REG(EXTINT_BASE, port);
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pending = getreg32(regaddr);
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/* Clear irq factor */
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regaddr = INTC_REG(EXTINTnCLR_BASE, port);
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regaddr = INTC_REG(EXTINTCLR_BASE, port);
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putreg32(pending, regaddr);
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irq = LC823450_IRQ_GPIO00 + (port * 0x10);
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@ -412,7 +412,7 @@ static int lc823450_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
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{
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int port = ((irq - LC823450_IRQ_GPIO00) & 0x70) >> 4;
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*regaddr = INTC_REG(EXTINTnM_BASE, port);
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*regaddr = INTC_REG(EXTINTM_BASE, port);
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*bit = 1 << ((irq - LC823450_IRQ_GPIO00) & 0xf);
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}
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else if (irq >= LC823450_IRQ_INTERRUPTS)
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@ -846,7 +846,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype)
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flags = spin_lock_irqsave();
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regaddr = INTC_REG(EXTINTnCND_BASE, port);
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regaddr = INTC_REG(EXTINTCND_BASE, port);
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regval = getreg32(regaddr);
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regval &= ~(3 << gpio * 2);
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@ -84,48 +84,48 @@
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/* #define CHECK_INTERVAL */
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#ifdef CONFIG_LC823450_MTM0_TICK
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# define rMT00STS (LC823450_MTM0_REGBASE + LC823450_MTM_0STS)
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# define rMT00A (LC823450_MTM0_REGBASE + LC823450_MTM_0A)
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# define rMT00B (LC823450_MTM0_REGBASE + LC823450_MTM_0B)
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# define rMT00CTL (LC823450_MTM0_REGBASE + LC823450_MTM_0CTL)
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# define rMT00PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_0PSCL)
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# define rMT00TIER (LC823450_MTM0_REGBASE + LC823450_MTM_0TIER)
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# define rMT00OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR)
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# define rMT00CNT (LC823450_MTM0_REGBASE + LC823450_MTM_0CNT)
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# define MT00STS (LC823450_MTM0_REGBASE + LC823450_MTM_0STS)
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# define MT00A (LC823450_MTM0_REGBASE + LC823450_MTM_0A)
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# define MT00B (LC823450_MTM0_REGBASE + LC823450_MTM_0B)
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# define MT00CTL (LC823450_MTM0_REGBASE + LC823450_MTM_0CTL)
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# define MT00PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_0PSCL)
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# define MT00TIER (LC823450_MTM0_REGBASE + LC823450_MTM_0TIER)
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# define MT00OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR)
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# define MT00CNT (LC823450_MTM0_REGBASE + LC823450_MTM_0CNT)
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# define MTM_RELOAD (XT1OSC_CLK / (CLK_TCK * 10))
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#endif
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#ifdef CONFIG_HRT_TIMER
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# define LC823450_MTM2_REGBASE 0x40045000
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# define rMT20STS (LC823450_MTM2_REGBASE + LC823450_MTM_0STS)
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# define rMT20A (LC823450_MTM2_REGBASE + LC823450_MTM_0A)
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# define rMT20PSCL (LC823450_MTM2_REGBASE + LC823450_MTM_0PSCL)
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# define rMT20TIER (LC823450_MTM2_REGBASE + LC823450_MTM_0TIER)
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# define rMT2OPR (LC823450_MTM2_REGBASE + LC823450_MTM_OPR)
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# define rMT20CNT (LC823450_MTM2_REGBASE + LC823450_MTM_0CNT)
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# define MT20STS (LC823450_MTM2_REGBASE + LC823450_MTM_0STS)
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# define MT20A (LC823450_MTM2_REGBASE + LC823450_MTM_0A)
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# define MT20PSCL (LC823450_MTM2_REGBASE + LC823450_MTM_0PSCL)
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# define MT20TIER (LC823450_MTM2_REGBASE + LC823450_MTM_0TIER)
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# define MT2OPR (LC823450_MTM2_REGBASE + LC823450_MTM_OPR)
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# define MT20CNT (LC823450_MTM2_REGBASE + LC823450_MTM_0CNT)
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#endif /* CONFIG_HRT_TIMER */
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#ifdef CONFIG_PROFILE
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# define LC823450_MTM3_REGBASE 0x40046000
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# define rMT30STS (LC823450_MTM3_REGBASE + LC823450_MTM_0STS)
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# define rMT30A (LC823450_MTM3_REGBASE + LC823450_MTM_0A)
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# define rMT30B (LC823450_MTM3_REGBASE + LC823450_MTM_0B)
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# define rMT30CTL (LC823450_MTM3_REGBASE + LC823450_MTM_0CTL)
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# define rMT30PSCL (LC823450_MTM3_REGBASE + LC823450_MTM_0PSCL)
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# define rMT30TIER (LC823450_MTM3_REGBASE + LC823450_MTM_0TIER)
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# define rMT30OPR (LC823450_MTM3_REGBASE + LC823450_MTM_OPR)
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# define rMT30CNT (LC823450_MTM3_REGBASE + LC823450_MTM_0CNT)
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# define MT30STS (LC823450_MTM3_REGBASE + LC823450_MTM_0STS)
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# define MT30A (LC823450_MTM3_REGBASE + LC823450_MTM_0A)
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# define MT30B (LC823450_MTM3_REGBASE + LC823450_MTM_0B)
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# define MT30CTL (LC823450_MTM3_REGBASE + LC823450_MTM_0CTL)
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# define MT30PSCL (LC823450_MTM3_REGBASE + LC823450_MTM_0PSCL)
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# define MT30TIER (LC823450_MTM3_REGBASE + LC823450_MTM_0TIER)
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# define MT30OPR (LC823450_MTM3_REGBASE + LC823450_MTM_OPR)
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# define MT30CNT (LC823450_MTM3_REGBASE + LC823450_MTM_0CNT)
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#endif /* CONFIG_PROFILE */
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#ifdef CONFIG_DVFS
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# define rMT01STS (LC823450_MTM0_REGBASE + LC823450_MTM_1STS)
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# define rMT01A (LC823450_MTM0_REGBASE + LC823450_MTM_1A)
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# define rMT01B (LC823450_MTM0_REGBASE + LC823450_MTM_1B)
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# define rMT01CTL (LC823450_MTM0_REGBASE + LC823450_MTM_1CTL)
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# define rMT01PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_1PSCL)
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# define rMT01TIER (LC823450_MTM0_REGBASE + LC823450_MTM_1TIER)
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# define rMT01CNT (LC823450_MTM0_REGBASE + LC823450_MTM_1CNT)
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# define rMT0OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR)
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# define MT01STS (LC823450_MTM0_REGBASE + LC823450_MTM_1STS)
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# define MT01A (LC823450_MTM0_REGBASE + LC823450_MTM_1A)
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# define MT01B (LC823450_MTM0_REGBASE + LC823450_MTM_1B)
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# define MT01CTL (LC823450_MTM0_REGBASE + LC823450_MTM_1CTL)
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# define MT01PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_1PSCL)
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# define MT01TIER (LC823450_MTM0_REGBASE + LC823450_MTM_1TIER)
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# define MT01CNT (LC823450_MTM0_REGBASE + LC823450_MTM_1CNT)
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# define MT0OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR)
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#endif
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#ifndef container_of
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@ -200,7 +200,7 @@ static void hrt_queue_refresh(void)
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irqstate_t flags;
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flags = spin_lock_irqsave();
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elapsed = (uint64_t)getreg32(rMT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK;
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elapsed = (uint64_t)getreg32(MT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK;
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for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent))
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{
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@ -209,6 +209,7 @@ static void hrt_queue_refresh(void)
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}
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cont:
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/* serch for expired */
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for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent))
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@ -267,12 +268,12 @@ static void hrt_usleep_setup(void)
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count = 0x7fff;
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}
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putreg32(0, rMT20CNT); /* counter */
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putreg32(count, rMT20A); /* AEVT counter */
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putreg32(0, MT20CNT); /* counter */
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putreg32(count, MT20A); /* AEVT counter */
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/* Enable MTM2-Ch0 */
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putreg32(1, rMT2OPR);
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putreg32(1, MT2OPR);
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spin_unlock_irqrestore(flags);
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}
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#endif
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@ -286,11 +287,11 @@ static int hrt_interrupt(int irq, FAR void *context, FAR void *arg)
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{
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/* Disable MTM2-Ch0 */
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putreg32(0, rMT2OPR);
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putreg32(0, MT2OPR);
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/* clear AEVT Interrupt */
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putreg32(1 << 0, rMT20STS);
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putreg32(1 << 0, MT20STS);
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hrt_queue_refresh();
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hrt_usleep_setup();
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@ -308,7 +309,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
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/* Disable MTM2-Ch0 */
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putreg32(0, rMT2OPR);
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putreg32(0, MT2OPR);
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hrt_queue_refresh();
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@ -324,6 +325,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
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break;
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}
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}
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if (pent)
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{
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dq_addbefore(pent, &phrt->ent, &hrt_timer_queue);
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@ -350,7 +352,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
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#ifdef CONFIG_PROFILE
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int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
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{
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putreg32(1 << 1, rMT30STS);
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putreg32(1 << 1, MT30STS);
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if (profile_en)
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{
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if (profile_ptr != CONFIG_PROFILE_SAMPLES)
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@ -363,8 +365,8 @@ int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
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profile_en = 0;
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tmrinfo("PROFILING DONE\n");
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}
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}
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return 0;
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}
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#endif /* CONFIG_PROFILE */
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@ -375,7 +377,7 @@ int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
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int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
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{
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/* Process timer interrupt */
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/* Process timer interrupt */
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#ifdef CONFIG_DVFS
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lc823450_dvfs_tick_callback();
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@ -384,7 +386,7 @@ int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
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#ifdef CONFIG_LC823450_MTM0_TICK
|
||||
/* Clear the interrupt (BEVT) */
|
||||
|
||||
putreg32(1 << 1, rMT00STS);
|
||||
putreg32(1 << 1, MT00STS);
|
||||
#endif
|
||||
|
||||
nxsched_process_timer();
|
||||
@ -436,11 +438,11 @@ static uint64_t up_get_timer_fraction(void)
|
||||
|
||||
/* read the counter */
|
||||
|
||||
regval = getreg32(rMT00CNT);
|
||||
regval = getreg32(MT00CNT);
|
||||
|
||||
/* check if the timer interrupt is underway */
|
||||
|
||||
if (getreg32(rMT00STS) & 0x2 && regval < (MTM_RELOAD/10))
|
||||
if (getreg32(MT00STS) & 0x2 && regval < (MTM_RELOAD / 10))
|
||||
{
|
||||
return NSEC_PER_TICK;
|
||||
}
|
||||
@ -457,9 +459,9 @@ static uint64_t up_get_timer_fraction(void)
|
||||
|
||||
/* check if the systick interrupt is pending or active */
|
||||
|
||||
if ((getreg32(0xE000ED04) & (1 << 26) ||
|
||||
getreg32(0xE000ED24) & (1 << 11))
|
||||
&& (SYSTICK_RELOAD - cur) < (SYSTICK_RELOAD/10))
|
||||
if ((getreg32(0xe000ed04) & (1 << 26) ||
|
||||
getreg32(0xe000ed24) & (1 << 11))
|
||||
&& (SYSTICK_RELOAD - cur) < (SYSTICK_RELOAD / 10))
|
||||
{
|
||||
return NSEC_PER_TICK;
|
||||
}
|
||||
@ -491,11 +493,11 @@ void up_timer_initialize(void)
|
||||
|
||||
/* Enable AEVT Interrupt */
|
||||
|
||||
putreg32(1 << 0, rMT20TIER);
|
||||
putreg32(1 << 0, MT20TIER);
|
||||
|
||||
/* Set prescaler to (1/10) */
|
||||
|
||||
putreg32(10 - 1, rMT20PSCL);
|
||||
putreg32(10 - 1, MT20PSCL);
|
||||
|
||||
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0);
|
||||
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0);
|
||||
@ -515,28 +517,29 @@ void up_timer_initialize(void)
|
||||
|
||||
modifyreg32(MRSTCNTEXT1, 0x0, MRSTCNTEXT1_MTM3_RSTB);
|
||||
|
||||
/* Input clock for the MTM3 is XT1 (i.e. 24M or 20M) */
|
||||
/* then the clock will be set to 1/10 by the internal divider */
|
||||
/* To implement 10ms timer, ADT=0, BDT=MTM_RELOAD */
|
||||
/* Input clock for the MTM3 is XT1 (i.e. 24M or 20M)
|
||||
* then the clock will be set to 1/10 by the internal divider
|
||||
* To implement 10ms timer, ADT=0, BDT=MTM_RELOAD
|
||||
*/
|
||||
|
||||
putreg32(0, rMT30A); /* AEVT counter */
|
||||
putreg32((XT1OSC_CLK / 1010) - 1, rMT30B); /* BEVT counter */
|
||||
putreg32(0, MT30A); /* AEVT counter */
|
||||
putreg32((XT1OSC_CLK / 1010) - 1, MT30B); /* BEVT counter */
|
||||
|
||||
/* Clear the counter by BEVT */
|
||||
|
||||
putreg32(0x80, rMT30CTL);
|
||||
putreg32(0x80, MT30CTL);
|
||||
|
||||
/* Set prescaler to 9 : (1/10) */
|
||||
|
||||
putreg32(9, rMT30PSCL);
|
||||
putreg32(9, MT30PSCL);
|
||||
|
||||
/* Enable BEVT Interrupt */
|
||||
|
||||
putreg32(1 << 1, rMT30TIER);
|
||||
putreg32(1 << 1, MT30TIER);
|
||||
|
||||
/* Enable MTM3-Ch0 */
|
||||
|
||||
putreg32(1, rMT30OPR);
|
||||
putreg32(1, MT30OPR);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
@ -559,28 +562,29 @@ void up_timer_initialize(void)
|
||||
|
||||
modifyreg32(MRSTCNTEXT1, 0x0, MRSTCNTEXT1_MTM0_RSTB);
|
||||
|
||||
/* Input clock for the MTM0 is XT1 (i.e. 24M or 20M) */
|
||||
/* then the clock will be set to 1/10 by the internal divider */
|
||||
/* To implement the tick timer, ADT=0, BDT=MTM_RELOAD-1 */
|
||||
/* Input clock for the MTM0 is XT1 (i.e. 24M or 20M)
|
||||
* then the clock will be set to 1/10 by the internal divider
|
||||
* To implement the tick timer, ADT=0, BDT=MTM_RELOAD-1
|
||||
*/
|
||||
|
||||
putreg32(0, rMT00A); /* AEVT counter */
|
||||
putreg32(MTM_RELOAD - 1, rMT00B); /* BEVT counter */
|
||||
putreg32(0, MT00A); /* AEVT counter */
|
||||
putreg32(MTM_RELOAD - 1, MT00B); /* BEVT counter */
|
||||
|
||||
/* Clear the counter by BEVT */
|
||||
|
||||
putreg32(0x80, rMT00CTL);
|
||||
putreg32(0x80, MT00CTL);
|
||||
|
||||
/* Set prescaler to 9 : (1/10) */
|
||||
|
||||
putreg32(9, rMT00PSCL);
|
||||
putreg32(9, MT00PSCL);
|
||||
|
||||
/* Enable BEVT Interrupt */
|
||||
|
||||
putreg32(1 << 1, rMT00TIER);
|
||||
putreg32(1 << 1, MT00TIER);
|
||||
|
||||
/* Enable MTM0-Ch0 */
|
||||
|
||||
putreg32(1, rMT00OPR);
|
||||
putreg32(1, MT00OPR);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
@ -655,25 +659,24 @@ void lc823450_mtm_start_oneshot(int msec)
|
||||
r /= 10; /* 1ms */
|
||||
r *= msec;
|
||||
|
||||
putreg32(0, rMT01A); /* AEVT counter */
|
||||
putreg32(r - 1, rMT01B); /* BEVT counter */
|
||||
putreg32(0, MT01A); /* AEVT counter */
|
||||
putreg32(r - 1, MT01B); /* BEVT counter */
|
||||
|
||||
/* Clear the counter by BEVT */
|
||||
|
||||
putreg32(0x80, rMT01CTL);
|
||||
putreg32(0x80, MT01CTL);
|
||||
|
||||
/* Set prescaler to 9 : (1/10) */
|
||||
|
||||
putreg32(9, rMT01PSCL);
|
||||
putreg32(9, MT01PSCL);
|
||||
|
||||
/* Enable BEVT Interrupt */
|
||||
|
||||
putreg32(1 << 1, rMT01TIER);
|
||||
|
||||
putreg32(1 << 1, MT01TIER);
|
||||
|
||||
/* Enable MTM0-ch1 */
|
||||
|
||||
modifyreg32(rMT0OPR, 0, 1 << 1);
|
||||
modifyreg32(MT0OPR, 0, 1 << 1);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -686,11 +689,11 @@ void lc823450_mtm_stop_oneshot(void)
|
||||
{
|
||||
/* Clear the interrupt (BEVT) */
|
||||
|
||||
putreg32(1 << 1, rMT01STS);
|
||||
putreg32(1 << 1, MT01STS);
|
||||
|
||||
/* Disable MTM0-ch1 */
|
||||
|
||||
modifyreg32(rMT0OPR, 1 << 1, 0);
|
||||
modifyreg32(MT0OPR, 1 << 1, 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user