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arch: lc823450: Fix style violations

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Summary:
- Fix style violations under lc823450
- NOTE: still some files need to be fixed

Impact:
- Some register naming were changed but all files are included

Testing:
- Build check only

Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
This commit is contained in:
Masayuki Ishikawa 2020-07-30 09:32:29 +09:00 committed by Xiang Xiao
parent 22a9b497b1
commit 336bd8c3a2
4 changed files with 111 additions and 105 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
arch/arm/src/lc823450/lc823450_intc.h
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@ -66,15 +66,15 @@
#define IPICLR_INTISR1_CLR_2 (0x1 << 10) #define IPICLR_INTISR1_CLR_2 (0x1 << 10)
#define IPICLR_INTISR1_CLR_3 (0x1 << 11) #define IPICLR_INTISR1_CLR_3 (0x1 << 11)
#define EXTINTn_BASE (LC823450_INTC_REGBASE + 0x400) #define EXTINT_BASE (LC823450_INTC_REGBASE + 0x400)
#define EXTINTnS_BASE (LC823450_INTC_REGBASE + 0x418) #define EXTINTS_BASE (LC823450_INTC_REGBASE + 0x418)
#define EXTINTnM_BASE (LC823450_INTC_REGBASE + 0x430) #define EXTINTM_BASE (LC823450_INTC_REGBASE + 0x430)
#define EXTINTnC0_BASE (LC823450_INTC_REGBASE + 0x448) #define EXTINTC0_BASE (LC823450_INTC_REGBASE + 0x448)
#define EXTINTnC1_BASE (LC823450_INTC_REGBASE + 0x460) #define EXTINTC1_BASE (LC823450_INTC_REGBASE + 0x460)
#define EXTINTnCND_BASE (LC823450_INTC_REGBASE + 0x478) #define EXTINTCND_BASE (LC823450_INTC_REGBASE + 0x478)
#define EXTINTnCLR_BASE (LC823450_INTC_REGBASE + 0x490) #define EXTINTCLR_BASE (LC823450_INTC_REGBASE + 0x490)
#define EXTINTnFEN_BASE (LC823450_INTC_REGBASE + 0x4A8) #define EXTINTFEN_BASE (LC823450_INTC_REGBASE + 0x4A8)
#define EXTINTnSET_BASE (LC823450_INTC_REGBASE + 0x4C0) #define EXTINTSET_BASE (LC823450_INTC_REGBASE + 0x4C0)
#define INTC_REG(base,port) ((base) + 4 * (port)) #define INTC_REG(base,port) ((base) + 4 * (port))

35
arch/arm/src/lc823450/lc823450_ipl2.c
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@ -119,7 +119,8 @@ static struct
uint32_t size; uint32_t size;
uint32_t enc; uint32_t enc;
uint32_t offset; uint32_t offset;
} chunk[10]; }
chunk[10];
} upg_image; } upg_image;
/**************************************************************************** /****************************************************************************
@ -192,7 +193,10 @@ static int blk_write(const void *buf, int len, const char *path, int offset)
static int install_recovery(const char *srcpath) static int install_recovery(const char *srcpath)
{ {
int rfd, i, len, rem; int rfd;
int i;
int len;
int rem;
int ret = 0; int ret = 0;
void *handle = NULL; void *handle = NULL;
@ -223,7 +227,6 @@ static int install_recovery(const char *srcpath)
sysreset(); sysreset();
/* NOT REACHED */ /* NOT REACHED */
} }
#endif #endif
@ -308,7 +311,6 @@ static void load_kernel(const char *name, const char *devname)
"ldr sp, [r1, #0]\n" /* set sp */ "ldr sp, [r1, #0]\n" /* set sp */
"ldr pc, [r1, #4]" /* set pc, start nuttx */ "ldr pc, [r1, #4]" /* set pc, start nuttx */
); );
} }
/**************************************************************************** /****************************************************************************
@ -377,18 +379,18 @@ static int check_forceusbboot(void)
/* start ADC0,1 */ /* start ADC0,1 */
putreg32(rADCCTL_fADCNVCK_DIV32 | rADCCTL_fADACT | rADCCTL_fADCHSCN | putreg32(ADCCTL_ADCNVCK_DIV32 | ADCCTL_ADACT | ADCCTL_ADCHSCN |
1 /* 0,1 ch */, rADCCTL); 1 /* 0,1 ch */, ADCCTL);
putreg32(53, rADCSMPL); putreg32(53, ADCSMPL);
/* wait for adc done */ /* wait for adc done */
while ((getreg32(rADCSTS) & rADCSTS_fADCMPL) == 0) while ((getreg32(ADCSTS) & ADCSTS_ADCMPL) == 0)
; ;
val = getreg32(rADC0DT); val = getreg32(ADC0DT);
val1 = getreg32(rADC1DT); val1 = getreg32(ADC1DT);
_info("val = %d, val1 = %d\n", val, val1); _info("val = %d, val1 = %d\n", val, val1);
@ -399,21 +401,21 @@ static int check_forceusbboot(void)
/* check KEY0_AD_D key pressed */ /* check KEY0_AD_D key pressed */
if (val >= (0x3A << 2) && val < (0x57 << 2)) if (val >= (0x3a << 2) && val < (0x57 << 2))
{ {
return 1; return 1;
} }
/* check KEY0_AD_B key pressed */ /* check KEY0_AD_B key pressed */
if (val >= (0x0B << 2) && val < (0x20 << 2)) if (val >= (0x0b << 2) && val < (0x20 << 2))
{ {
return 1; return 1;
} }
/* check KEY1_AD_B key pressed */ /* check KEY1_AD_B key pressed */
if (val1 >= (0x0B << 2) && val1 < (0x20 << 2)) if (val1 >= (0x0b << 2) && val1 < (0x20 << 2))
{ {
return 1; return 1;
} }
@ -495,11 +497,11 @@ static void chg_disable(void)
/* I2C pinmux */ /* I2C pinmux */
modifyreg32(PMDCNT0, 0x0003C000, 0x00014000); modifyreg32(PMDCNT0, 0x0003c000, 0x00014000);
/* I2C drv : 4mA */ /* I2C drv : 4mA */
modifyreg32(PTDRVCNT0, 0x0003C000, 0x0003C000); modifyreg32(PTDRVCNT0, 0x0003c000, 0x0003c000);
/* Enable I2C controller */ /* Enable I2C controller */
@ -612,6 +614,7 @@ static int msc_enable(int forced)
_info("Install recovery\n"); _info("Install recovery\n");
/* clear old MBR */ /* clear old MBR */
memset(copybuf, 0, sizeof(copybuf)); memset(copybuf, 0, sizeof(copybuf));
set_config(0, copybuf); set_config(0, copybuf);
} }
@ -625,6 +628,7 @@ static int msc_enable(int forced)
sysreset(); sysreset();
/* not reached */ /* not reached */
return 0; return 0;
} }
#endif #endif
@ -749,7 +753,6 @@ int ipl2_main(int argc, char *argv[])
install_recovery("/mnt/sd0/UPG.IMG"); install_recovery("/mnt/sd0/UPG.IMG");
load_kernel("recovery", CONFIG_MTD_RECOVERY_DEVPATH); load_kernel("recovery", CONFIG_MTD_RECOVERY_DEVPATH);
} }
else else
{ {

10
arch/arm/src/lc823450/lc823450_irq.c
View File

@ -304,7 +304,7 @@ static void lc823450_extint_clr(int irq)
port = (irq & 0x70) >> 4; port = (irq & 0x70) >> 4;
pin = irq & 0xf; pin = irq & 0xf;
regaddr = INTC_REG(EXTINTnCLR_BASE, port); regaddr = INTC_REG(EXTINTCLR_BASE, port);
putreg32(1 << pin, regaddr); putreg32(1 << pin, regaddr);
return; return;
@ -330,12 +330,12 @@ static int lc823450_extint_isr(int irq, FAR void *context, FAR void *arg)
/* Read irq factor */ /* Read irq factor */
regaddr = INTC_REG(EXTINTn_BASE, port); regaddr = INTC_REG(EXTINT_BASE, port);
pending = getreg32(regaddr); pending = getreg32(regaddr);
/* Clear irq factor */ /* Clear irq factor */
regaddr = INTC_REG(EXTINTnCLR_BASE, port); regaddr = INTC_REG(EXTINTCLR_BASE, port);
putreg32(pending, regaddr); putreg32(pending, regaddr);
irq = LC823450_IRQ_GPIO00 + (port * 0x10); irq = LC823450_IRQ_GPIO00 + (port * 0x10);
@ -412,7 +412,7 @@ static int lc823450_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
{ {
int port = ((irq - LC823450_IRQ_GPIO00) & 0x70) >> 4; int port = ((irq - LC823450_IRQ_GPIO00) & 0x70) >> 4;
*regaddr = INTC_REG(EXTINTnM_BASE, port); *regaddr = INTC_REG(EXTINTM_BASE, port);
*bit = 1 << ((irq - LC823450_IRQ_GPIO00) & 0xf); *bit = 1 << ((irq - LC823450_IRQ_GPIO00) & 0xf);
} }
else if (irq >= LC823450_IRQ_INTERRUPTS) else if (irq >= LC823450_IRQ_INTERRUPTS)
@ -846,7 +846,7 @@ int lc823450_irq_srctype(int irq, enum lc823450_srctype_e srctype)
flags = spin_lock_irqsave(); flags = spin_lock_irqsave();
regaddr = INTC_REG(EXTINTnCND_BASE, port); regaddr = INTC_REG(EXTINTCND_BASE, port);
regval = getreg32(regaddr); regval = getreg32(regaddr);
regval &= ~(3 << gpio * 2); regval &= ~(3 << gpio * 2);

153
arch/arm/src/lc823450/lc823450_timer.c
View File

@ -84,48 +84,48 @@
/* #define CHECK_INTERVAL */ /* #define CHECK_INTERVAL */
#ifdef CONFIG_LC823450_MTM0_TICK #ifdef CONFIG_LC823450_MTM0_TICK
# define rMT00STS (LC823450_MTM0_REGBASE + LC823450_MTM_0STS) # define MT00STS (LC823450_MTM0_REGBASE + LC823450_MTM_0STS)
# define rMT00A (LC823450_MTM0_REGBASE + LC823450_MTM_0A) # define MT00A (LC823450_MTM0_REGBASE + LC823450_MTM_0A)
# define rMT00B (LC823450_MTM0_REGBASE + LC823450_MTM_0B) # define MT00B (LC823450_MTM0_REGBASE + LC823450_MTM_0B)
# define rMT00CTL (LC823450_MTM0_REGBASE + LC823450_MTM_0CTL) # define MT00CTL (LC823450_MTM0_REGBASE + LC823450_MTM_0CTL)
# define rMT00PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_0PSCL) # define MT00PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_0PSCL)
# define rMT00TIER (LC823450_MTM0_REGBASE + LC823450_MTM_0TIER) # define MT00TIER (LC823450_MTM0_REGBASE + LC823450_MTM_0TIER)
# define rMT00OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR) # define MT00OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR)
# define rMT00CNT (LC823450_MTM0_REGBASE + LC823450_MTM_0CNT) # define MT00CNT (LC823450_MTM0_REGBASE + LC823450_MTM_0CNT)
# define MTM_RELOAD (XT1OSC_CLK / (CLK_TCK * 10)) # define MTM_RELOAD (XT1OSC_CLK / (CLK_TCK * 10))
#endif #endif
#ifdef CONFIG_HRT_TIMER #ifdef CONFIG_HRT_TIMER
# define LC823450_MTM2_REGBASE 0x40045000 # define LC823450_MTM2_REGBASE 0x40045000
# define rMT20STS (LC823450_MTM2_REGBASE + LC823450_MTM_0STS) # define MT20STS (LC823450_MTM2_REGBASE + LC823450_MTM_0STS)
# define rMT20A (LC823450_MTM2_REGBASE + LC823450_MTM_0A) # define MT20A (LC823450_MTM2_REGBASE + LC823450_MTM_0A)
# define rMT20PSCL (LC823450_MTM2_REGBASE + LC823450_MTM_0PSCL) # define MT20PSCL (LC823450_MTM2_REGBASE + LC823450_MTM_0PSCL)
# define rMT20TIER (LC823450_MTM2_REGBASE + LC823450_MTM_0TIER) # define MT20TIER (LC823450_MTM2_REGBASE + LC823450_MTM_0TIER)
# define rMT2OPR (LC823450_MTM2_REGBASE + LC823450_MTM_OPR) # define MT2OPR (LC823450_MTM2_REGBASE + LC823450_MTM_OPR)
# define rMT20CNT (LC823450_MTM2_REGBASE + LC823450_MTM_0CNT) # define MT20CNT (LC823450_MTM2_REGBASE + LC823450_MTM_0CNT)
#endif /* CONFIG_HRT_TIMER */ #endif /* CONFIG_HRT_TIMER */
#ifdef CONFIG_PROFILE #ifdef CONFIG_PROFILE
# define LC823450_MTM3_REGBASE 0x40046000 # define LC823450_MTM3_REGBASE 0x40046000
# define rMT30STS (LC823450_MTM3_REGBASE + LC823450_MTM_0STS) # define MT30STS (LC823450_MTM3_REGBASE + LC823450_MTM_0STS)
# define rMT30A (LC823450_MTM3_REGBASE + LC823450_MTM_0A) # define MT30A (LC823450_MTM3_REGBASE + LC823450_MTM_0A)
# define rMT30B (LC823450_MTM3_REGBASE + LC823450_MTM_0B) # define MT30B (LC823450_MTM3_REGBASE + LC823450_MTM_0B)
# define rMT30CTL (LC823450_MTM3_REGBASE + LC823450_MTM_0CTL) # define MT30CTL (LC823450_MTM3_REGBASE + LC823450_MTM_0CTL)
# define rMT30PSCL (LC823450_MTM3_REGBASE + LC823450_MTM_0PSCL) # define MT30PSCL (LC823450_MTM3_REGBASE + LC823450_MTM_0PSCL)
# define rMT30TIER (LC823450_MTM3_REGBASE + LC823450_MTM_0TIER) # define MT30TIER (LC823450_MTM3_REGBASE + LC823450_MTM_0TIER)
# define rMT30OPR (LC823450_MTM3_REGBASE + LC823450_MTM_OPR) # define MT30OPR (LC823450_MTM3_REGBASE + LC823450_MTM_OPR)
# define rMT30CNT (LC823450_MTM3_REGBASE + LC823450_MTM_0CNT) # define MT30CNT (LC823450_MTM3_REGBASE + LC823450_MTM_0CNT)
#endif /* CONFIG_PROFILE */ #endif /* CONFIG_PROFILE */
#ifdef CONFIG_DVFS #ifdef CONFIG_DVFS
# define rMT01STS (LC823450_MTM0_REGBASE + LC823450_MTM_1STS) # define MT01STS (LC823450_MTM0_REGBASE + LC823450_MTM_1STS)
# define rMT01A (LC823450_MTM0_REGBASE + LC823450_MTM_1A) # define MT01A (LC823450_MTM0_REGBASE + LC823450_MTM_1A)
# define rMT01B (LC823450_MTM0_REGBASE + LC823450_MTM_1B) # define MT01B (LC823450_MTM0_REGBASE + LC823450_MTM_1B)
# define rMT01CTL (LC823450_MTM0_REGBASE + LC823450_MTM_1CTL) # define MT01CTL (LC823450_MTM0_REGBASE + LC823450_MTM_1CTL)
# define rMT01PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_1PSCL) # define MT01PSCL (LC823450_MTM0_REGBASE + LC823450_MTM_1PSCL)
# define rMT01TIER (LC823450_MTM0_REGBASE + LC823450_MTM_1TIER) # define MT01TIER (LC823450_MTM0_REGBASE + LC823450_MTM_1TIER)
# define rMT01CNT (LC823450_MTM0_REGBASE + LC823450_MTM_1CNT) # define MT01CNT (LC823450_MTM0_REGBASE + LC823450_MTM_1CNT)
# define rMT0OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR) # define MT0OPR (LC823450_MTM0_REGBASE + LC823450_MTM_OPR)
#endif #endif
#ifndef container_of #ifndef container_of
@ -200,7 +200,7 @@ static void hrt_queue_refresh(void)
irqstate_t flags; irqstate_t flags;
flags = spin_lock_irqsave(); flags = spin_lock_irqsave();
elapsed = (uint64_t)getreg32(rMT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK; elapsed = (uint64_t)getreg32(MT20CNT) * (1000 * 1000) * 10 / XT1OSC_CLK;
for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent)) for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent))
{ {
@ -209,6 +209,7 @@ static void hrt_queue_refresh(void)
} }
cont: cont:
/* serch for expired */ /* serch for expired */
for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent)) for (pent = hrt_timer_queue.head; pent; pent = dq_next(pent))
@ -267,12 +268,12 @@ static void hrt_usleep_setup(void)
count = 0x7fff; count = 0x7fff;
} }
putreg32(0, rMT20CNT); /* counter */ putreg32(0, MT20CNT); /* counter */
putreg32(count, rMT20A); /* AEVT counter */ putreg32(count, MT20A); /* AEVT counter */
/* Enable MTM2-Ch0 */ /* Enable MTM2-Ch0 */
putreg32(1, rMT2OPR); putreg32(1, MT2OPR);
spin_unlock_irqrestore(flags); spin_unlock_irqrestore(flags);
} }
#endif #endif
@ -286,11 +287,11 @@ static int hrt_interrupt(int irq, FAR void *context, FAR void *arg)
{ {
/* Disable MTM2-Ch0 */ /* Disable MTM2-Ch0 */
putreg32(0, rMT2OPR); putreg32(0, MT2OPR);
/* clear AEVT Interrupt */ /* clear AEVT Interrupt */
putreg32(1 << 0, rMT20STS); putreg32(1 << 0, MT20STS);
hrt_queue_refresh(); hrt_queue_refresh();
hrt_usleep_setup(); hrt_usleep_setup();
@ -308,7 +309,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
/* Disable MTM2-Ch0 */ /* Disable MTM2-Ch0 */
putreg32(0, rMT2OPR); putreg32(0, MT2OPR);
hrt_queue_refresh(); hrt_queue_refresh();
@ -324,6 +325,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
break; break;
} }
} }
if (pent) if (pent)
{ {
dq_addbefore(pent, &phrt->ent, &hrt_timer_queue); dq_addbefore(pent, &phrt->ent, &hrt_timer_queue);
@ -350,7 +352,7 @@ static void hrt_usleep_add(struct hrt_s *phrt)
#ifdef CONFIG_PROFILE #ifdef CONFIG_PROFILE
int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg) int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
{ {
putreg32(1 << 1, rMT30STS); putreg32(1 << 1, MT30STS);
if (profile_en) if (profile_en)
{ {
if (profile_ptr != CONFIG_PROFILE_SAMPLES) if (profile_ptr != CONFIG_PROFILE_SAMPLES)
@ -363,8 +365,8 @@ int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
profile_en = 0; profile_en = 0;
tmrinfo("PROFILING DONE\n"); tmrinfo("PROFILING DONE\n");
} }
} }
return 0; return 0;
} }
#endif /* CONFIG_PROFILE */ #endif /* CONFIG_PROFILE */
@ -375,7 +377,7 @@ int up_proftimerisr(int irq, uint32_t *regs, FAR void *arg)
int up_timerisr(int irq, uint32_t *regs, FAR void *arg) int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
{ {
/* Process timer interrupt */ /* Process timer interrupt */
#ifdef CONFIG_DVFS #ifdef CONFIG_DVFS
lc823450_dvfs_tick_callback(); lc823450_dvfs_tick_callback();
@ -384,7 +386,7 @@ int up_timerisr(int irq, uint32_t *regs, FAR void *arg)
#ifdef CONFIG_LC823450_MTM0_TICK #ifdef CONFIG_LC823450_MTM0_TICK
/* Clear the interrupt (BEVT) */ /* Clear the interrupt (BEVT) */
putreg32(1 << 1, rMT00STS); putreg32(1 << 1, MT00STS);
#endif #endif
nxsched_process_timer(); nxsched_process_timer();
@ -436,11 +438,11 @@ static uint64_t up_get_timer_fraction(void)
/* read the counter */ /* read the counter */
regval = getreg32(rMT00CNT); regval = getreg32(MT00CNT);
/* check if the timer interrupt is underway */ /* check if the timer interrupt is underway */
if (getreg32(rMT00STS) & 0x2 && regval < (MTM_RELOAD/10)) if (getreg32(MT00STS) & 0x2 && regval < (MTM_RELOAD / 10))
{ {
return NSEC_PER_TICK; return NSEC_PER_TICK;
} }
@ -457,9 +459,9 @@ static uint64_t up_get_timer_fraction(void)
/* check if the systick interrupt is pending or active */ /* check if the systick interrupt is pending or active */
if ((getreg32(0xE000ED04) & (1 << 26) || if ((getreg32(0xe000ed04) & (1 << 26) ||
getreg32(0xE000ED24) & (1 << 11)) getreg32(0xe000ed24) & (1 << 11))
&& (SYSTICK_RELOAD - cur) < (SYSTICK_RELOAD/10)) && (SYSTICK_RELOAD - cur) < (SYSTICK_RELOAD / 10))
{ {
return NSEC_PER_TICK; return NSEC_PER_TICK;
} }
@ -491,11 +493,11 @@ void up_timer_initialize(void)
/* Enable AEVT Interrupt */ /* Enable AEVT Interrupt */
putreg32(1 << 0, rMT20TIER); putreg32(1 << 0, MT20TIER);
/* Set prescaler to (1/10) */ /* Set prescaler to (1/10) */
putreg32(10 - 1, rMT20PSCL); putreg32(10 - 1, MT20PSCL);
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0); modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2C_CLKEN, 0);
modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0); modifyreg32(MCLKCNTEXT1, MCLKCNTEXT1_MTM2_CLKEN, 0);
@ -515,28 +517,29 @@ void up_timer_initialize(void)
modifyreg32(MRSTCNTEXT1, 0x0, MRSTCNTEXT1_MTM3_RSTB); modifyreg32(MRSTCNTEXT1, 0x0, MRSTCNTEXT1_MTM3_RSTB);
/* Input clock for the MTM3 is XT1 (i.e. 24M or 20M) */ /* Input clock for the MTM3 is XT1 (i.e. 24M or 20M)
/* then the clock will be set to 1/10 by the internal divider */ * then the clock will be set to 1/10 by the internal divider
/* To implement 10ms timer, ADT=0, BDT=MTM_RELOAD */ * To implement 10ms timer, ADT=0, BDT=MTM_RELOAD
*/
putreg32(0, rMT30A); /* AEVT counter */ putreg32(0, MT30A); /* AEVT counter */
putreg32((XT1OSC_CLK / 1010) - 1, rMT30B); /* BEVT counter */ putreg32((XT1OSC_CLK / 1010) - 1, MT30B); /* BEVT counter */
/* Clear the counter by BEVT */ /* Clear the counter by BEVT */
putreg32(0x80, rMT30CTL); putreg32(0x80, MT30CTL);
/* Set prescaler to 9 : (1/10) */ /* Set prescaler to 9 : (1/10) */
putreg32(9, rMT30PSCL); putreg32(9, MT30PSCL);
/* Enable BEVT Interrupt */ /* Enable BEVT Interrupt */
putreg32(1 << 1, rMT30TIER); putreg32(1 << 1, MT30TIER);
/* Enable MTM3-Ch0 */ /* Enable MTM3-Ch0 */
putreg32(1, rMT30OPR); putreg32(1, MT30OPR);
/* Attach the timer interrupt vector */ /* Attach the timer interrupt vector */
@ -559,28 +562,29 @@ void up_timer_initialize(void)
modifyreg32(MRSTCNTEXT1, 0x0, MRSTCNTEXT1_MTM0_RSTB); modifyreg32(MRSTCNTEXT1, 0x0, MRSTCNTEXT1_MTM0_RSTB);
/* Input clock for the MTM0 is XT1 (i.e. 24M or 20M) */ /* Input clock for the MTM0 is XT1 (i.e. 24M or 20M)
/* then the clock will be set to 1/10 by the internal divider */ * then the clock will be set to 1/10 by the internal divider
/* To implement the tick timer, ADT=0, BDT=MTM_RELOAD-1 */ * To implement the tick timer, ADT=0, BDT=MTM_RELOAD-1
*/
putreg32(0, rMT00A); /* AEVT counter */ putreg32(0, MT00A); /* AEVT counter */
putreg32(MTM_RELOAD - 1, rMT00B); /* BEVT counter */ putreg32(MTM_RELOAD - 1, MT00B); /* BEVT counter */
/* Clear the counter by BEVT */ /* Clear the counter by BEVT */
putreg32(0x80, rMT00CTL); putreg32(0x80, MT00CTL);
/* Set prescaler to 9 : (1/10) */ /* Set prescaler to 9 : (1/10) */
putreg32(9, rMT00PSCL); putreg32(9, MT00PSCL);
/* Enable BEVT Interrupt */ /* Enable BEVT Interrupt */
putreg32(1 << 1, rMT00TIER); putreg32(1 << 1, MT00TIER);
/* Enable MTM0-Ch0 */ /* Enable MTM0-Ch0 */
putreg32(1, rMT00OPR); putreg32(1, MT00OPR);
/* Attach the timer interrupt vector */ /* Attach the timer interrupt vector */
@ -655,25 +659,24 @@ void lc823450_mtm_start_oneshot(int msec)
r /= 10; /* 1ms */ r /= 10; /* 1ms */
r *= msec; r *= msec;
putreg32(0, rMT01A); /* AEVT counter */ putreg32(0, MT01A); /* AEVT counter */
putreg32(r - 1, rMT01B); /* BEVT counter */ putreg32(r - 1, MT01B); /* BEVT counter */
/* Clear the counter by BEVT */ /* Clear the counter by BEVT */
putreg32(0x80, rMT01CTL); putreg32(0x80, MT01CTL);
/* Set prescaler to 9 : (1/10) */ /* Set prescaler to 9 : (1/10) */
putreg32(9, rMT01PSCL); putreg32(9, MT01PSCL);
/* Enable BEVT Interrupt */ /* Enable BEVT Interrupt */
putreg32(1 << 1, rMT01TIER); putreg32(1 << 1, MT01TIER);
/* Enable MTM0-ch1 */ /* Enable MTM0-ch1 */
modifyreg32(rMT0OPR, 0, 1 << 1); modifyreg32(MT0OPR, 0, 1 << 1);
} }
#endif #endif
@ -686,11 +689,11 @@ void lc823450_mtm_stop_oneshot(void)
{ {
/* Clear the interrupt (BEVT) */ /* Clear the interrupt (BEVT) */
putreg32(1 << 1, rMT01STS); putreg32(1 << 1, MT01STS);
/* Disable MTM0-ch1 */ /* Disable MTM0-ch1 */
modifyreg32(rMT0OPR, 1 << 1, 0); modifyreg32(MT0OPR, 1 << 1, 0);
} }
#endif #endif