Progress integrating SD on STM32
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2275 42af7a65-404d-4744-a932-0658087f49c3
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@ -428,6 +428,11 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32 waitmask,
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sdio_eventset_t wkupevent)
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{
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irqstate_t flags;
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/* Save all of the data and set the new interrupt mask in one, atomic
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* operation.
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*/
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flags = irqsave();
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priv->waitevents = waitevents;
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priv->wkupevent = wkupevent;
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@ -1152,35 +1157,39 @@ static void stm32_widebus(FAR struct sdio_dev_s *dev, boolean wide)
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static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
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{
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uint32 clckr;
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uint32 enable = 1;
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switch (rate)
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{
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case CLOCK_SDIO_DISABLED: /* Clock is disabled */
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putreg32(0, SDIO_CLKCR_CLKEN_BB);
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break;
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default:
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case CLOCK_SDIO_DISABLED: /* Clock is disabled */
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clckr = STM32_CLCKCR_INIT;
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enable = 0;
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return;
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case CLOCK_IDMODE: /* Initial ID mode clocking (<400KHz) */
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clckr = STM32_CLCKCR_INIT;
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clckr = STM32_CLCKCR_INIT;
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break;
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case CLOCK_MMC_TRANSFER: /* MMC normal operation clocking */
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clckr = SDIO_CLKCR_MMCXFR;
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clckr = SDIO_CLKCR_MMCXFR;
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break;
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case CLOCK_SD_TRANSFER_1BIT: /* SD normal operation clocking (narrow 1-bit mode) */
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clckr = SDIO_CLCKR_SDXFR;
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clckr = SDIO_CLCKR_SDXFR;
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break;
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case CLOCK_SD_TRANSFER_4BIT: /* SD normal operation clocking (wide 4-bit mode) */
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clckr = SDIO_CLCKR_SDWIDEXFR;
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clckr = SDIO_CLCKR_SDWIDEXFR;
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break;
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};
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/* Set the new clock frequency and make sure that the clock is enabled */
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/* Set the new clock frequency and make sure that the clock is enabled or
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* disabled, whatever the case.
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*/
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stm32_setclkcr(STM32_CLCKCR_INIT);
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putreg32(1, SDIO_CLKCR_CLKEN_BB);
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stm32_setclkcr(clckr);
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putreg32(enable, SDIO_CLKCR_CLKEN_BB);
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}
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/****************************************************************************
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@ -1773,7 +1782,13 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
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sdio_eventset_t wkupevent = 0;
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int ret;
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DEBUGASSERT(priv->waitevents != 0);
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/* There is a race condition here... the event may have completed before
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* we get here. In this case waitevents will be zero, but wkupevents will
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* be non-zero (and, hopefully, the semaphore count will also be non-zero.
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*/
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DEBUGASSERT((priv->waitevents != 0 && priv->wkupevent == 0) ||
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(priv->waitevents == 0 && priv->wkupevent != 0));
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/* Check if the timeout event is specified in the event set */
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@ -1814,10 +1829,11 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev,
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stm32_takesem(priv);
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/* Check if the event has occurred. */
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/* Check if the event has occurred. When the event has occurred, then
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* evenset will be set to 0 and wkupevent will be set to a nonzero value.
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*/
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wkupevent = (ubyte)(priv->wkupevent & priv->waitevents);
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if (wkupevent != 0)
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if (priv->wkupevent != 0)
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{
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/* Yes... break out of the loop with wkupevent non-zero */
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@ -824,8 +824,6 @@ struct mmcsd_scr_s decoded;
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* SD_SECURITY 54:52 3-bit SD security support level
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* SD_BUS_WIDTHS 51:48 4-bit bus width indicator
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* Reserved 47:32 16-bit SD reserved space
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* usage.
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*
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*/
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priv->buswidth = (scr[0] >> 16) & 15;
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@ -839,9 +837,7 @@ struct mmcsd_scr_s decoded;
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#endif
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/* Word 1, bits 63:32
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* Reserved 31:0 32-bits reserved for manufacturing
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* usage.
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*
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* Reserved 31:0 32-bits reserved for manufacturing usage.
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*/
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#if defined(CONFIG_DEBUG) && defined (CONFIG_DEBUG_VERBOSE) && defined(CONFIG_DEBUG_FS)
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@ -1134,7 +1130,7 @@ static int mmcsd_setblocklen(FAR struct mmcsd_state_s *priv, uint32 blocklen)
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* block length is specified in the CSD.
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*/
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mmcsd_sendcmdpoll(priv, MMCSD_CMD16, priv->blocksize);
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mmcsd_sendcmdpoll(priv, MMCSD_CMD16, blocklen);
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ret = mmcsd_recvR1(priv, MMCSD_CMD16);
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if (ret == OK)
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{
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@ -2238,6 +2234,19 @@ static int mmcsd_sdinitialize(FAR struct mmcsd_state_s *priv)
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}
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mmcsd_decodeCSD(priv, csd);
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/* Send CMD7 with the argument == RCA in order to select the card.
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* Since we are supporting only a single card, we just leave the
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* card selected all of the time.
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*/
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mmcsd_sendcmdpoll(priv, MMCSD_CMD7S, priv->rca << 16);
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ret = mmcsd_recvR1(priv, MMCSD_CMD7S);
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if (ret != OK)
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{
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fdbg("ERROR: mmcsd_recvR1 for CMD7 failed: %d\n", ret);
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return ret;
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}
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/* Set the Driver Stage Register (DSR) if (1) a CONFIG_MMCSD_DSR has been
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* provided and (2) the card supports a DSR register. If no DSR value
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* the card default value (0x0404) will be used.
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