Add initialization logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2638 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
5db45464f7
commit
338bbcd45a
@ -116,17 +116,25 @@
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#define ENC_POLLTIMEOUT MSEC2TICK(50)
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/* Packet Memory ************************************************************/
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/* Packet memory layout */
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#define PKTMEM_TX_START 0x0000 /* Start TX buffer at 0 */
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#define PKTMEM_TX_ENDP1 0x0600 /* Allow TX buffer for one frame + */
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#define PKTMEM_RX_START PKTMEM_TX_ENDP1 /* Followed by RX buffer */
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#define PKTMEM_RX_END PKTMEM_END /* RX buffer goes to the end of SRAM */
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/* Misc. Helper Macros ******************************************************/
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#define enc_rdgreg(priv,ctrlreg) \
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enc_rdgreg2(priv, ENC_RCR | GETADDR(ctrlreg))
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#define enc_wdgreg(priv,ctrlreg,wrdata) \
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enc_wdgreg2(priv, ENC_WCR | GETADDR(ctrlreg), wrdata)
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#define enc_wrgreg(priv,ctrlreg,wrdata) \
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enc_wrgreg2(priv, ENC_WCR | GETADDR(ctrlreg), wrdata)
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#define enc_bfcgreg(priv,ctrlreg,clrbits) \
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enc_wdgreg2(priv, ENC_BFC | GETADDR(ctrlreg), clrbits)
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enc_wrgreg2(priv, ENC_BFC | GETADDR(ctrlreg), clrbits)
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#define enc_bfsgreg(priv,ctrlreg,setbits) \
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enc_wdgreg2(priv, ENC_BFS | GETADDR(ctrlreg), setbits)
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enc_wrgreg2(priv, ENC_BFS | GETADDR(ctrlreg), setbits)
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/* This is a helper pointer for accessing the contents of the Ethernet header */
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@ -175,6 +183,7 @@ struct enc_driver_s
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uint32_t txifs; /* TXIF completion events */
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uint32_t txabrts; /* TXIF completions with ESTAT.TXABRT */
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uint32_t txerifs; /* TXERIF error events */
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uint32_t txtimeouts; /* S/W detected TX timeouts */
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uint32_t rxerifs; /* RXERIF error evernts */
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#endif
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};
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@ -203,7 +212,7 @@ static void enc_deselect(FAR struct spi_dev_s *spi);
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/* SPI control register access */
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static uint8_t enc_rdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd);
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static void enc_wdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd,
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static void enc_wrgreg2(FAR struct enc_driver_s *priv, uint8_t cmd,
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uint8_t wrdata);
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static void enc_setbank(FAR struct enc_driver_s *priv, uint8_t bank);
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static uint8_t enc_rdbreg(FAR struct enc_driver_s *priv, uint8_t ctrlreg);
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@ -257,7 +266,7 @@ static int enc_txavail(struct uip_driver_s *dev);
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static void enc_pwrsave(FAR struct enc_driver_s *priv);
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static void enc_pwrfull(FAR struct enc_driver_s *priv);
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static void enc_setmacaddr(FAR struct enc_driver_s *priv);
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static void enc_reset(FAR struct enc_driver_s *priv);
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static int enc_reset(FAR struct enc_driver_s *priv);
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/****************************************************************************
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* Private Functions
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@ -383,7 +392,7 @@ static uint8_t enc_rdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd)
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}
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/****************************************************************************
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* Function: enc_wdgreg2
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* Function: enc_wrgreg2
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*
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* Description:
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* Write to a global register (EIE, EIR, ESTAT, ECON2, or ECON1). The cmd
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@ -391,7 +400,7 @@ static uint8_t enc_rdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd)
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*
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****************************************************************************/
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static void enc_wdgreg2(FAR struct enc_driver_s *priv, uint8_t cmd,
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static void enc_wrgreg2(FAR struct enc_driver_s *priv, uint8_t cmd,
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uint8_t wrdata)
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{
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FAR struct spi_dev_s *spi;
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@ -706,6 +715,7 @@ static void enc_wrphy(FAR struct enc_driver_s *priv, uint8_t phyaddr,
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static int enc_transmit(FAR struct enc_driver_s *priv)
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{
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/* Verify that the hardware is ready to send another packet */
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#warning "Missing logic"
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/* Increment statistics */
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@ -758,6 +768,7 @@ static int enc_uiptxpoll(struct uip_driver_s *dev)
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/* Check if there is room in the device to hold another packet. If not,
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* return a non-zero value to terminate the poll.
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*/
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#warning "Missing logic"
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}
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/* If zero is returned, the polling will continue until all connections have
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@ -1221,13 +1232,22 @@ static int enc_interrupt(int irq, FAR void *context)
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static void enc_txtimeout(int argc, uint32_t arg, ...)
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{
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FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)arg;
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int ret;
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/* Increment statistics and dump debug info */
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/* Then reset the hardware */
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#ifdef CONFIG_ENC28J60_STATS
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priv->txtimeouts++;
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#endif
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enc_reset(priv);
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enc_setmacaddr(priv);
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/* Then reset the hardware. Take the interface down, then bring it
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* back up
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*/
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ret = enc_ifdown(&priv->dev);
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DEBUGASSERT(ret == OK);
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ret = enc_ifup(&priv->dev);
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DEBUGASSERT(ret == OK);
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/* Then poll uIP for new XMIT data */
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@ -1286,6 +1306,7 @@ static void enc_polltimer(int argc, uint32_t arg, ...)
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static int enc_ifup(struct uip_driver_s *dev)
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{
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FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)dev->d_private;
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int ret;
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ndbg("Bringing up: %d.%d.%d.%d\n",
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dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
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@ -1295,7 +1316,9 @@ static int enc_ifup(struct uip_driver_s *dev)
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* the ENC28J80 is not in power save mode.
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*/
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enc_reset(priv);
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ret = enc_reset(priv);
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if (ret == OK)
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{
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enc_setmacaddr(priv);
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enc_pwrfull(priv);
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@ -1315,7 +1338,8 @@ static int enc_ifup(struct uip_driver_s *dev)
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priv->bifup = true;
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up_enable_irq(priv->irq);
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return OK;
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}
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return ret;
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}
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/****************************************************************************
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@ -1338,6 +1362,7 @@ static int enc_ifdown(struct uip_driver_s *dev)
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{
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FAR struct enc_driver_s *priv = (FAR struct enc_driver_s *)dev->d_private;
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irqstate_t flags;
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int ret;
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/* Disable the Ethernet interrupt */
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@ -1351,12 +1376,12 @@ static int enc_ifdown(struct uip_driver_s *dev)
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/* Reset the device and leave in the power save state */
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enc_reset(priv);
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ret = enc_reset(priv);
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enc_pwrsave(priv);
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priv->bifup = false;
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irqrestore(flags);
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return OK;
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return ret;
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}
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/****************************************************************************
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@ -1445,8 +1470,7 @@ static void enc_pwrsave(FAR struct enc_driver_s *priv)
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enc_waitbreg(priv, ENC_ECON1, ECON1_TXRTS, 0);
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/* 4. Set ECON2.VRPS (if not already set). */
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enc_bfsgreg(priv, ENC_ECON2, ECON2_VRPS);
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/* enc_bfsgreg(priv, ENC_ECON2, ECON2_VRPS); <-- Set in enc_reset() */
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/* 5. Enter Sleep by setting ECON2.PWRSV. */
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@ -1543,9 +1567,129 @@ static void enc_setmacaddr(FAR struct enc_driver_s *priv)
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*
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****************************************************************************/
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static void enc_reset(FAR struct enc_driver_s *priv)
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static int enc_reset(FAR struct enc_driver_s *priv)
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{
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#warning "Missing logic"
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uint8_t regval;
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ndbg("Entry\n");
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/* Configure SPI for the ENC28J60 */
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enc_configspi(priv->spi);
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/* Reset the ENC28J60 */
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enc_wrgreg(priv, ENC_SRC, ENC_SRC);
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/* Check CLKRDY bit to see when the reset is complete. There is an errata
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* that says the CLKRDY may be invalid. We'll wait a couple of msec to
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* workaround this condition.
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*/
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up_mdelay(2);
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/* while ((enc_rdgreg(priv, ENC_ESTAT) & ESTAT_CLKRDY) != 0); */
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/* Initialize ECON1: Clear ECON1 */
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enc_wrgreg(priv, ENC_ECON1, 0x00);
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/* Initialize ECON2: Enable address auto increment and voltage
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* regulator powersave.
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*/
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enc_wrgreg(priv, ENC_ECON2, ECON2_AUTOINC | ECON2_VRPS);
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/* Initialize receive buffer.
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* First, set the receive buffer start address.
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*/
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priv->nextpkt = PKTMEM_RX_START;
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enc_wrbreg(priv, ENC_ERXSTL, PKTMEM_RX_START & 0xff);
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enc_wrbreg(priv, ENC_ERXSTH, PKTMEM_RX_START >> 8);
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/* Set the receive data pointer */
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enc_wrbreg(priv, ENC_ERXRDPTL, PKTMEM_RX_START & 0xff);
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enc_wrbreg(priv, ENC_ERXRDPTH, PKTMEM_RX_START >> 8);
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/* Set the receive buffer end. */
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enc_wrbreg(priv, ENC_ERXNDL, PKTMEM_RX_END & 0xff);
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enc_wrbreg(priv, ENC_ERXNDH, PKTMEM_RX_END >> 8);
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/* Set transmit buffer start. */
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enc_wrbreg(priv, ENC_ETXSTL, PKTMEM_TX_START & 0xff);
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enc_wrbreg(priv, ENC_ETXSTH, PKTMEM_TX_START >> 8);
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/* Check if we are actually communicating with the ENC28J60. If its
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* 0x00 or 0xff, then we are probably not communicating correctly
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* via SPI.
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*/
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regval = enc_rdbreg(priv, ENC_EREVID);
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if (regval == 0x00 || regval == 0xff)
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{
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ndbg("Bad Rev ID: %0x\n", regval);
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return -ENODEV;
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}
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nvdbg("Rev ID: %02x\n", regval);
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/* Set filter mode: unicast OR broadcast AND crc valid */
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enc_wrbreg(priv, ENC_ERXFCON, ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
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/* Enable MAC receive */
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enc_wrbreg(priv, ENC_MACON1, MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
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/* Enable automatic padding and CRC operations */
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#ifdef CONFIG_ENC28J60_HALFDUPLEX
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enc_wrbreg(priv, ENC_MACON3, MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN);
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enc_wrbreg(priv, ENC_MACON4, MACON4_DEFER); /* Defer transmission enable */
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/* Set Non-Back-to-Back Inter-Packet Gap */
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enc_wrbreg(priv, ENC_MAIPGL, 0x12);
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enc_wrbreg(priv, ENC_MAIPGH, 0x0c);
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/* Set Back-to-Back Inter-Packet Gap */
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enc_wrbreg(priv, ENC_MABBIPG, 0x12);
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#else
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/* Set filter mode: unicast OR broadcast AND crc valid AND Full Duplex */
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enc_wrbreg(priv, ENC_MACON3,
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MACON3_PADCFG0 | MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX);
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/* set Non-Back-to-Back Inter-Packet Gap */
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enc_wrbreg(priv, ENC_MAIPGL, 0x12);
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/* set ack-to-Back Inter-Packet Gap */
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enc_wrbreg(priv, ENC_MABBIPG, 0x15);
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#endif
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/* Set the maximum packet size which the controller will accept */
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enc_wrbreg(priv, ENC_MAMXFLL, MAX_FRAMELEN & 0xff);
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enc_wrbreg(priv, ENC_MAMXFLH, MAX_FRAMELEN >> 8);
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/* Configure LEDs (No, just use the defaults for now) */
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/* enc_wrphy(priv, ENC_PHLCON, ??); */
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/* Setup up PHCON1 & 2 */
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#ifdef CONFIG_ENC28J60_HALFDUPLEX
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enc_wrphy(priv, ENC_PHCON1, 0x00);
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enc_wrphy(priv, ENC_PHCON2, PHCON2_HDLDIS);
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#else
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enc_wrphy(priv, ENC_PHCON1, PHCON1_PDPXMD);
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enc_wrphy(priv, ENC_PHCON2, 0x00);
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#endif
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return OK;
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}
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/****************************************************************************
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@ -1578,6 +1722,7 @@ static void enc_reset(FAR struct enc_driver_s *priv)
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int enc_initialize(FAR struct spi_dev_s *spi, unsigned int devno, unsigned int irq)
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{
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FAR struct enc_driver_s *priv ;
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int ret;
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DEBUGASSERT(devno < CONFIG_ENC28J60_NINTERFACES);
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priv = &g_enc28j60[devno];
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@ -1602,22 +1747,23 @@ int enc_initialize(FAR struct spi_dev_s *spi, unsigned int devno, unsigned int i
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* the MAC address before bringing the interface up.
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*/
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enc_ifdown(&priv->dev);
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ret = enc_ifdown(&priv->dev);
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if (ret == OK)
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{
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/* Attach the IRQ to the driver (but don't enable it yet) */
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if (irq_attach(irq, enc_interrupt))
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{
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/* We could not attach the ISR to the interrupt */
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return -EAGAIN;
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ret = -EAGAIN;
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}
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/* Register the device with the OS so that socket IOCTLs can be performed */
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(void)netdev_register(&priv->dev);
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return OK;
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}
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return ret;
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}
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#endif /* CONFIG_NET && CONFIG_ENC28J60_NET */
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@ -355,7 +355,7 @@
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#define ENC_PHCON2 (0x10) /* PHY Control Register 2 */
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#define ENC_PHSTAT2 (0x11) /* PHY Status 2 */
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#define ENC_PHIE (0x12) /* PHY Interrupt Enable Register */
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#define ENC_PHIR (0x13)
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#define ENC_PHIR (0x13) /* PHY Interrupt Request Register */
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#define ENC_PHLCON (0x14)
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/* PHY Control Register 1 Register Bit Definitions */
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@ -413,6 +413,18 @@
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#define PHLCON_LACFG2 (1 << 10) /* Bit 10: " " " " */
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#define PHLCON_LACFG3 (1 << 11) /* Bit 11: " " " " */
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/* Packet Memory ************************************************************/
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/* 8-Kbyte Transmit/Receive Packet Dual Port SRAM */
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#define PKTMEM_START 0x0000
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#define PKTMEM_END 0x1fff
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/* Ethernet frames are between 64 and 1518 bytes long */
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#define MIN_FRAMELEN 64
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#define MAX_FRAMELEN 1518
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/* Packet Control Bits Definitions ******************************************/
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#define PKTCTRL_POVERRIDE (1 << 0) /* Bit 0: Per Packet Override */
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