diff --git a/arch/arm/include/s32k1xx/s32k14x_irq.h b/arch/arm/include/s32k1xx/s32k14x_irq.h index ef92fd3d53..3182ca32a3 100644 --- a/arch/arm/include/s32k1xx/s32k14x_irq.h +++ b/arch/arm/include/s32k1xx/s32k14x_irq.h @@ -45,8 +45,6 @@ ************************************************************************************/ #include -#include -#include /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h b/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h index e72e25081f..c2453560fc 100644 --- a/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h +++ b/arch/arm/src/s32k1xx/hardware/s32k1xx_lmem.h @@ -86,14 +86,14 @@ # define LMEM_PCCLCR_CACHEADDR(n) ((uint32_t)(n) << LMEM_PCCLCR_CACHEADDR_SHIFT) #define LMEM_PCCLCR_WSEL (1 << 14) /* Bit 14: Way select */ # define LMEM_PCCLCR_WSEL_WAY0 (0) /* Way0 */ -# define LMEM_PCCLCR_WSEL_WAY0 (1 << 14) /* Way1 */ +# define LMEM_PCCLCR_WSEL_WAY1 (1 << 14) /* Way1 */ #define LMEM_PCCLCR_TDSEL (1 << 16) /* Bit 16: Tag/Data Select */ # define LMEM_PCCLCR_TDSEL_DATA (0) /* Data */ # define LMEM_PCCLCR_TDSEL_TAG (1 << 16) /* Tag */ #define LMEM_PCCLCR_LCIVB (1 << 20) /* Bit 20: Line Command Initial Valid Bit */ #define LMEM_PCCLCR_LCWAY (1 << 22) /* Bit 22: Line Command Way */ # define LMEM_PCCLCR_LCWAY_WAY0 (0) /* Way0 */ -# define LMEM_PCCLCR_LCWAY_WAY (1 << 22) /* Way1 */ +# define LMEM_PCCLCR_LCWAY_WAY1 (1 << 22) /* Way1 */ #define LMEM_PCCLCR_LCMD_SHIFT (24) /* Bits 24-25: Line Command */ #define LMEM_PCCLCR_LCMD_MASK (3 << LMEM_PCCLCR_LCMD_SHIFT) # define LMEM_PCCLCR_LCMD_SEARCH (0 << LMEM_PCCLCR_LCMD_SHIFT) /* Search and read or write */ diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c b/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c index e265a40348..407269f764 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_irq.c @@ -50,6 +50,7 @@ #include "up_arch.h" #include "up_internal.h" +#include "s32k1xx_pin.h" #include "s32k11x/s32k11x_irq.h" /**************************************************************************** @@ -201,8 +202,13 @@ void up_irqinitialize(void) s32k11x_dumpnvic("initial", NR_IRQS); -#ifndef CONFIG_SUPPRESS_INTERRUPTS +#ifdef CONFIG_S32K1XX_GPIOIRQ + /* Initialize GPIO PIN interrupts */ + s32k1xx_pinirq_initialize(); +#endif + +#ifndef CONFIG_SUPPRESS_INTERRUPTS /* And finally, enable interrupts */ up_irq_enable(); diff --git a/arch/arm/src/s32k1xx/s32k14x/Make.defs b/arch/arm/src/s32k1xx/s32k14x/Make.defs index 7d1a3b06b5..9fe8cd72ec 100644 --- a/arch/arm/src/s32k1xx/s32k14x/Make.defs +++ b/arch/arm/src/s32k1xx/s32k14x/Make.defs @@ -35,9 +35,7 @@ # Source files specific to the Cortex-M4F -HEAD_ASRC = - -CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S +CMN_ASRCS += up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S CMN_ASRCS += up_testset.S up_fetchadd.S vfork.S ifeq ($(CONFIG_ARCH_SETJMP_H),y) @@ -46,7 +44,7 @@ CMN_ASRCS += up_setjmp.S endif endif -CMN_CSRCS = up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c +CMN_CSRCS += up_assert.c up_blocktask.c up_copyfullstate.c up_createstack.c CMN_CSRCS += up_doirq.c up_hardfault.c up_initialstate.c up_memfault.c CMN_CSRCS += up_releasepending.c up_reprioritizertr.c up_schedulesigaction.c CMN_CSRCS += up_sigdeliver.c up_svcall.c up_trigger_irq.c up_unblocktask.c @@ -74,8 +72,8 @@ endif # Source file specific to the S32k11x family -CHIP_ASRCS = -CHIP_CSRCS = s32k14x_irq.c s32k14x_clrpend.c s32k14x_clockmapping.c +CHIP_CSRCS += s32k14x_irq.c s32k14x_clrpend.c s32k14x_clockmapping.c +CHIP_CSRCS += s32k14x_periphfeatures.c # Configuration-dependent S32k14x files diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c index b8ba7cf5eb..6b74f014d9 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clrpend.c @@ -68,9 +68,9 @@ void s32k14x_clrpend(int irq) { /* Check for external interrupt */ - if (irq >= S32K1XX_IRQ_EXTINT) + if (irq >= S32K1XX_IRQ_INTERRUPT) { - irq -= S32K1XX_IRQ_EXTINT; + irq -= S32K1XX_IRQ_INTERRUPT; if (irq < 32) { putreg32(1 << irq , NVIC_IRQ0_31_CLRPEND); diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c index b3ecd5c658..3e0620dcb0 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_irq.c @@ -53,7 +53,7 @@ #include "up_arch.h" #include "up_internal.h" -#include "s32k14x_gpio.h" +#include "s32k1xx_pin.h" #include "s32k14x/s32k14x_irq.h" /**************************************************************************** @@ -265,9 +265,9 @@ static int s32k14x_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, /* Check for external interrupt */ - if (irq >= S32K1XX_IRQ_EXTINT) + if (irq >= S32K1XX_IRQ_INTERRUPT) { - n = irq - S32K1XX_IRQ_EXTINT; + n = irq - S32K1XX_IRQ_INTERRUPT; *regaddr = NVIC_IRQ_ENABLE(n) + offset; *bit = (uint32_t)1 << (n & 0x1f); } @@ -435,9 +435,9 @@ void up_irqinitialize(void) #endif #ifdef CONFIG_S32K1XX_GPIOIRQ - /* Initialize GPIO interrupts */ + /* Initialize GPIO PIN interrupts */ - s32k14x_gpio_irqinitialize(); + s32k1xx_pinirq_initialize(); #endif #ifndef CONFIG_SUPPRESS_INTERRUPTS @@ -469,7 +469,7 @@ void up_disable_irq(int irq) * clear the bit in the System Handler Control and State Register. */ - if (irq >= S32K1XX_IRQ_EXTINT) + if (irq >= S32K1XX_IRQ_INTERRUPT) { putreg32(bit, regaddr); } @@ -506,7 +506,7 @@ void up_enable_irq(int irq) * set the bit in the System Handler Control and State Register. */ - if (irq >= S32K1XX_IRQ_EXTINT) + if (irq >= S32K1XX_IRQ_INTERRUPT) { putreg32(bit, regaddr); } @@ -555,7 +555,7 @@ int up_prioritize_irq(int irq, int priority) DEBUGASSERT(irq >= S32K1XX_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); - if (irq < S32K1XX_IRQ_EXTINT) + if (irq < S32K1XX_IRQ_INTERRUPT) { /* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority * registers (0-3 are invalid) @@ -568,7 +568,7 @@ int up_prioritize_irq(int irq, int priority) { /* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */ - irq -= S32K1XX_IRQ_EXTINT; + irq -= S32K1XX_IRQ_INTERRUPT; regaddr = NVIC_IRQ_PRIORITY(irq); } diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c b/arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c index 7a96326713..d175b45b89 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_timerisr.c @@ -111,7 +111,6 @@ void arm_timer_initialize(void) { uint32_t coreclk; uint32_t reload; - uint32_t regval; /* Make sure that the SYSTICK clock source is set to use the SysTick * function clock (CLKSOURCE==1). diff --git a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c index 344f2428e1..9207c0fb60 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c +++ b/arch/arm/src/s32k1xx/s32k1xx_clockconfig.c @@ -390,7 +390,6 @@ static uint32_t s32k1xx_get_spllfreq(void) uint32_t regval; uint32_t prediv; uint32_t mult; - uint32_t ret; /* Check if the SPLL is valid */ @@ -548,8 +547,8 @@ static int s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, #ifdef CONFIG_S32K1XX_HAVE_HSRUN case SCG_SYSTEM_CLOCK_MODE_HSRUN: /*!< High Speed Run mode. */ - DEVBUGASSERT(SCG_SYSTEM_CLOCK_SRC_FIRC == config->src || - SCG_SYSTEM_CLOCK_SRC_SYS_PLL == config->src); + DEBUGASSERT(SCG_SYSTEM_CLOCK_SRC_FIRC == config->src || + SCG_SYSTEM_CLOCK_SRC_SYS_PLL == config->src); /* Verify the frequencies of sys, bus and slow clocks. */ @@ -566,10 +565,11 @@ static int s32k1xx_set_sysclk_configuration(enum scg_system_clock_mode_e mode, } else { - SCG_SetHsrunClockControl((uint32_t)config->src, - (uint32_t)config->divcore, - (uint32_t)config->divbus, - (uint32_t)config->divslow); + regval = (((uint32_t)config->src << SCG_HCCR_SCS_SHIFT) | + SCG_HCCR_DIVCORE(config->divcore) | + SCG_HCCR_DIVBUS(config->divbus) | + SCG_HCCR_DIVSLOW(config->divslow)); + putreg32(regval, S32K1XX_SCG_HCCR); } break; #endif @@ -1022,7 +1022,7 @@ static int s32k1xx_spll_config(bool enable, uint32_t timeout; int ret = OK; - DEBUASSERT(spllcfg != NULL); + DEBUGASSERT(spllcfg != NULL); /* If clock is used by system, return error. */ @@ -1074,9 +1074,9 @@ static int s32k1xx_spll_config(bool enable, /* Step 3. Enable clock, configure monitor, lock register. */ - regval = SCG_SPLLCSR_SPLLEN | sosccfg->locked ? SCG_SOSCCSR_LK : 0; + regval = SCG_SPLLCSR_SPLLEN | spllcfg->locked ? SCG_SPLLCSR_LK : 0; - switch (spllcfg->monitorMode) + switch (spllcfg->mode) { case SCG_SPLL_MONITOR_DISABLE: { @@ -1686,7 +1686,7 @@ uint32_t s32k1xx_get_coreclk(void) break; #ifdef CONFIG_S32K1XX_HAVE_SPLL - case 0x6SCG_CSR_SPLL_FIRC: /* System PLL */ + case SCG_CSR_SPLL_FIRC: /* System PLL */ /* Coreclock = Fxtal * mult / (2 * prediv) */ regval = getreg32(S32K1XX_SCG_SPLLCFG); diff --git a/arch/arm/src/s32k1xx/s32k1xx_pin.h b/arch/arm/src/s32k1xx/s32k1xx_pin.h index 771b3b0630..2b2be76cb8 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pin.h +++ b/arch/arm/src/s32k1xx/s32k1xx_pin.h @@ -357,7 +357,7 @@ void s32k1xx_gpiowrite(uint32_t pinset, bool value); bool s32k1xx_gpioread(uint32_t pinset); /************************************************************************************ - * Name: s32k1xx_pinirqi_nitialize + * Name: s32k1xx_pinirq_initialize * * Description: * Initialize logic to support a second level of interrupt decoding for GPIO pins. @@ -365,9 +365,9 @@ bool s32k1xx_gpioread(uint32_t pinset); ************************************************************************************/ #ifdef CONFIG_S32K1XX_GPIOIRQ -void s32k1xx_pinirqi_nitialize(void); +void s32k1xx_pinirq_initialize(void); #else -# define s32k1xx_pinirqi_nitialize() +# define s32k1xx_pinirq_initialize() #endif /************************************************************************************ diff --git a/arch/arm/src/s32k1xx/s32k1xx_pinirq.c b/arch/arm/src/s32k1xx/s32k1xx_pinirq.c index c3194cafa2..045b7336f7 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_pinirq.c +++ b/arch/arm/src/s32k1xx/s32k1xx_pinirq.c @@ -217,7 +217,7 @@ static int s32k1xx_porteinterrupt(int irq, FAR void *context, FAR void *arg) ****************************************************************************/ /**************************************************************************** - * Name: s32k1xx_pinirqinitialize + * Name: s32k1xx_pinirq_initialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -225,7 +225,7 @@ static int s32k1xx_porteinterrupt(int irq, FAR void *context, FAR void *arg) * ****************************************************************************/ -void s32k1xx_pinirqinitialize(void) +void s32k1xx_pinirq_initialize(void) { #ifdef CONFIG_S32K1XX_PORTAINTS (void)irq_attach(S32K1XX_IRQ_PORTA, s32k1xx_portainterrupt, NULL); diff --git a/arch/arm/src/s32k1xx/s32k1xx_start.c b/arch/arm/src/s32k1xx/s32k1xx_start.c index de1d73a6ed..6ba9d9f1b1 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_start.c +++ b/arch/arm/src/s32k1xx/s32k1xx_start.c @@ -213,6 +213,27 @@ static inline void s32k1xx_fpu_config(void) # define s32k1xx_fpu_config() #endif +/**************************************************************************** + * Name: s32k1xx_cache_config + * + * Description: + * IInvalidate and enable code cache. + * + ****************************************************************************/ + +#ifdef CONFIG_S32K1XX_HAVE_LMEM +static inline void s32k1xx_cache_config(void) +{ + uint32_t regval; + + /* Invalidate and enable code cache */ + + regval = (LMEM_PCCCR_ENCACHE | LMEM_PCCCR_INVW0 | LMEM_PCCCR_INVW1 | + LMEM_PCCCR_GO); + putreg32(regval, S32K1XX_LMEM_PCCCR); +} +#endif + /**************************************************************************** * Name: s32k1xx_mpu_config * diff --git a/boards/arm/s32k1xx/s32k146evb/README.txt b/boards/arm/s32k1xx/s32k146evb/README.txt index 97ca7b1a83..b9b5873e28 100644 --- a/boards/arm/s32k1xx/s32k146evb/README.txt +++ b/boards/arm/s32k1xx/s32k146evb/README.txt @@ -16,9 +16,10 @@ Status 2019-08-148 Configuration created but entirely untested. This configuration is intended, initially, to verify s32k14x architecture - support. This is VERY much a work in progress and you should not - use this configuration unless you are interested in assisting with - the bring-up. + support. The configuration builds and linkes without error but has + not yet been tested. This is VERY much a work in progress and you + should not use this configuration unless you are interested in + assisting with the bring-up. Serial Console ============== diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c b/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c index 4f0e6e2c82..1dd36c21df 100644 --- a/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k146_clockconfig.c @@ -114,11 +114,11 @@ const struct clock_configuration_s g_initial_clkconfig = }, .spll = { - .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ - .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ - .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ - .prediv = SCG_SPLL_CLOCK_PREDIV_BY_1, /* PREDIV */ - .mult = SCG_SPLL_CLOCK_MULTIPLY_BY_28, /* MULT */ + .mode = SCG_SPLL_MONITOR_DISABLE, /* SPLLCM */ + .div1 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV1 */ + .div2 = SCG_ASYNC_CLOCK_DIV_BY_1, /* SPLLDIV2 */ + .prediv = 1, /* PREDIV */ + .mult = 28, /* MULT */ .src = 0, /* SOURCE */ .initialize = true, /* Initialize */ .stopmode = false, /* */ diff --git a/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c b/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c index 0da1f0cd4b..450454a8fc 100644 --- a/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c +++ b/boards/arm/s32k1xx/s32k146evb/src/s32k146_periphclocks.c @@ -80,77 +80,77 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = { { - .clkname = PCC_ADC0_CLOCK, + .clkname = ADC0_CLK, .clkgate = true, .clksrc = CLK_SRC_FIRC, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_ADC1_CLOCK, + .clkname = ADC1_CLK, .clkgate = true, .clksrc = CLK_SRC_FIRC, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_LPTMR0_CLOCK, + .clkname = LPTMR0_CLK, .clkgate = true, .clksrc = CLK_SRC_SIRC, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_LPUART0_CLOCK, + .clkname = LPUART0_CLK, .clkgate = true, .clksrc = CLK_SRC_SIRC, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_LPUART1_CLOCK, + .clkname = LPUART1_CLK, .clkgate = true, .clksrc = CLK_SRC_SIRC, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_LPUART2_CLOCK, + .clkname = LPUART2_CLK, .clkgate = true, .clksrc = CLK_SRC_SIRC, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_PORTA_CLOCK, + .clkname = PORTA_CLK, .clkgate = true, .clksrc = CLK_SRC_OFF, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_PORTB_CLOCK, + .clkname = PORTB_CLK, .clkgate = true, .clksrc = CLK_SRC_OFF, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_PORTC_CLOCK, + .clkname = PORTC_CLK, .clkgate = true, .clksrc = CLK_SRC_OFF, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_PORTD_CLOCK, + .clkname = PORTD_CLK, .clkgate = true, .clksrc = CLK_SRC_OFF, .frac = MULTIPLY_BY_ONE, .divider = DIVIDE_BY_ONE, }, { - .clkname = PCC_PORTE_CLOCK, + .clkname = PORTE_CLK, .clkgate = true, .clksrc = CLK_SRC_OFF, .frac = MULTIPLY_BY_ONE,