Make sure that there is one space between while and condition

arch/arm/src/common/up_lowputs.c

@@ -67,7 +67,7 @@
 
 void up_lowputs(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_lowputc(*str++);
     }

arch/arm/src/sama5/sam_nand.c

@@ -1738,7 +1738,7 @@ static int nand_read_pmecc(struct sam_nandcs_s *priv, off_t block,
 
   /* Wait until the kernel of the PMECC is not busy */
 
-  while((nand_getreg(SAM_HSMC_PMECCSR) & HSMC_PMECCSR_BUSY) != 0);
+  while ((nand_getreg(SAM_HSMC_PMECCSR) & HSMC_PMECCSR_BUSY) != 0);
   return OK;
 }
 #endif

arch/arm/src/stm32/stm32_flash.c

@@ -148,7 +148,7 @@ int up_progmem_erasepage(uint16_t page)
   putreg32(page * STM32_FLASH_PAGESIZE, STM32_FLASH_AR);
   modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_STRT);
 
-  while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
+  while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
 
   modifyreg32(STM32_FLASH_CR, FLASH_CR_PER, 0);
 
@@ -232,7 +232,7 @@ int up_progmem_write(uint32_t addr, const void *buf, size_t count)
 
       putreg16(*hword, addr);
 
-      while(getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
+      while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
 
       /* Verify */
 

arch/arm/src/stm32/stm32_pwr.c

@@ -129,14 +129,14 @@ void stm32_pwr_setvos(uint16_t vos)
    * 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0.
    */
 
-  while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
+  while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
 
   regval  = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
   regval &= ~PWR_CR_VOS_MASK;
   regval |= (vos & PWR_CR_VOS_MASK);
   stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
 
-  while((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
+  while ((stm32_pwr_getreg(STM32_PWR_CSR_OFFSET) & PWR_CSR_VOSF) != 0);
 }
 #endif
 

arch/arm/src/stm32/stm32f10xxx_rcc.c

@@ -548,7 +548,7 @@ static void stm32_stdclockconfig(void)
 
   /* Wait for PLL2 ready */
 
-  while((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
 
   /* Setup PLL3 for MII/RMII clock on MCO */
 

arch/arm/src/stm32/stm32f30xxx_rcc.c

@@ -457,7 +457,7 @@ static void stm32_stdclockconfig(void)
 
   /* Wait for PLL2 ready */
 
-  while((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
+  while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0);
 
   /* Setup PLL3 for MII/RMII clock on MCO */
 

arch/arm/src/stm32/stm32f40xxx_rcc.c

@@ -686,14 +686,14 @@ static void stm32_stdclockconfig(void)
       regval  = getreg32(STM32_PWR_CR);
       regval |= PWR_CR_ODEN;
       putreg32(regval, STM32_PWR_CR);
-      while((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
+      while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODRDY) == 0)
         {
         }
 
       regval = getreg32(STM32_PWR_CR);
       regval |= PWR_CR_ODSWEN;
       putreg32(regval, STM32_PWR_CR);
-      while((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
+      while ((getreg32(STM32_PWR_CSR) & PWR_CSR_ODSWRDY) == 0)
         {
         }
 

arch/arm/src/tiva/tiva_flash.c

@@ -217,7 +217,7 @@ static ssize_t tiva_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t n
 
       /* wait until write has finished */
 
-      while(getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
+      while (getreg32(TIVA_FLASH_FMC) & FLASH_FMC_WRITE);
     }
 
   return nblocks;

arch/avr/src/common/up_lowputs.c

@@ -67,7 +67,7 @@
 
 void up_lowputs(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_lowputc(*str++);
     }

arch/avr/src/common/up_puts.c

@@ -68,7 +68,7 @@
 
 void up_puts(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_putc(*str++);
     }

arch/hc/src/common/up_puts.c

@@ -69,7 +69,7 @@
 
 void up_puts(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_putc(*str++);
     }

arch/mips/src/common/up_lowputs.c

@@ -67,7 +67,7 @@
 
 void up_lowputs(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_lowputc(*str++);
     }

arch/mips/src/common/up_puts.c

@@ -68,7 +68,7 @@
 
 void up_puts(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_putc(*str++);
     }

arch/mips/src/pic32mx/pic32mx-lowinit.c

@@ -125,11 +125,12 @@ static inline void pic32mx_waitstates(void)
   residual = BOARD_CPU_CLOCK;
   nwaits   = 0;
 
-  while(residual > MAX_FLASH_HZ)
+  while (residual > MAX_FLASH_HZ)
     {
       nwaits++;
       residual -= MAX_FLASH_HZ;
     }
+
   DEBUGASSERT(nwaits < 8);
 
   /* Set the FLASH wait states -- clearing all other bits! */

arch/rgmp/src/rgmp.c

@@ -151,9 +151,10 @@ void rtos_stop_running(void)
 
     nuttx_arch_exit();
 
-    while(1) {
-		arch_hlt();
-    }
+    while (1)
+      {
+	arch_hlt();
+      }
 }
 
 int rtos_vnet_init(struct rgmp_vnet *vnet)

arch/sh/src/common/up_lowputs.c

@@ -67,7 +67,7 @@
 
 void up_lowputs(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_lowputc(*str++);
     }

arch/sh/src/common/up_puts.c

@@ -68,7 +68,7 @@
 
 void up_puts(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_putc(*str++);
     }

arch/x86/src/common/up_lowputs.c

@@ -67,7 +67,7 @@
 
 void up_lowputs(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_lowputc(*str++);
     }

arch/x86/src/common/up_puts.c

@@ -68,7 +68,7 @@
 
 void up_puts(const char *str)
 {
-  while(*str)
+  while (*str)
     {
       up_putc(*str++);
     }