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arch/risc-v: Correct epc adjustment with C ISA

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Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi 2021-12-30 18:08:20 +08:00 committed by Masayuki Ishikawa
parent 1f53a058fa
commit 33df35f003
3 changed files with 3 additions and 3 deletions
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2
arch/risc-v/src/bl602/bl602_irq_dispatch.c
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@ -67,7 +67,7 @@ void *bl602_dispatch_irq(uint32_t vector, uint32_t *regs)
if (BL602_IRQ_ECALLM == irq)
{
*mepc += 4;
*mepc += 2;
}
/* Acknowledge the interrupt */

2
arch/risc-v/src/fe310/fe310_irq_dispatch.c
View File

@ -72,7 +72,7 @@ void *fe310_dispatch_irq(uint32_t vector, uint32_t *regs)
if (FE310_IRQ_ECALLM == irq)
{
*mepc += 4;
*mepc += 2;
}
/* Acknowledge the interrupt */

2
arch/risc-v/src/rv32m1/rv32m1_irq_dispatch.c
View File

@ -65,7 +65,7 @@ void *rv32m1_dispatch_irq(uint32_t vector, uint32_t *regs)
if (RV32M1_IRQ_ECALL_M == irq)
{
*mepc += 4;
*mepc += 2;
}
if (RV32M1_IRQ_INTMUX0 <= irq)