Rename sam_wdt.h to samd_wdt.h; Add saml_wdt.h for SAML21
This commit is contained in:
Gregory Nutt
parent
2f53158588
commit
3421f6ebb3
@ -1,7 +1,7 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/sam_wdt.h
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* arch/arm/src/samdl/chip/samd_wdt.h
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*
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* Copyright (C) 2014 Gregory Nutt. All rights reserved.
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* Copyright (C) 2014-2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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@ -49,6 +49,8 @@
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD20
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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@ -80,8 +82,8 @@
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#define WDT_CTRL_ENABLE (1 << 1) /* Bit 1: Enable */
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#define WDT_CTRL_WEN (1 << 2) /* Bit 2: Watchdog Timer Window Mode Enable */
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#define WDT_CTRL_ALWAYSON (1 << 7) /* Bit 7: Always-On
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*/
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#define WDT_CTRL_ALWAYSON (1 << 7) /* Bit 7: Always-On */
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/* Configuration register */
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#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
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@ -157,4 +159,5 @@
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAM_WDT_H */
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@ -37,8 +37,8 @@
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAM_RSTC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAM_RSTC_H
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_RSTC_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_RSTC_H
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/********************************************************************************************
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* Included Files
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@ -47,7 +47,8 @@
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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@ -140,4 +141,5 @@
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* Public Functions
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********************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAM_RSTC_H */
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#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_RSTC_H */
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166
arch/arm/src/samdl/chip/saml_wdt.h
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166
arch/arm/src/samdl/chip/saml_wdt.h
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@ -0,0 +1,166 @@
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/********************************************************************************************
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* arch/arm/src/samdl/chip/saml_wdt.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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* "Atmel SAM L21E / SAM L21G / SAM L21J Smart ARM-Based Microcontroller
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* Datasheet", Atmel-42385C-SAML21_Datasheet_Preliminary-03/20/15
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMDL_CHIP_SAML_WDT_H
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#define __ARCH_ARM_SRC_SAMDL_CHIP_SAML_WDT_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_sercom.h"
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#ifdef CONFIG_ARCH_FAMILY_SAML21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* WDT register offsets *********************************************************************/
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#define SAM_WDT_CTRLA_OFFSET 0x0000 /* Control A register */
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#define SAM_WDT_CONFIG_OFFSET 0x0001 /* Configuration register */
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#define SAM_WDT_EWCTRL_OFFSET 0x0002 /* Early warning interrupt control register */
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#define SAM_WDT_INTENCLR_OFFSET 0x0004 /* Interrupt enable clear register */
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#define SAM_WDT_INTENSET_OFFSET 0x0005 /* Interrupt enable set register */
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#define SAM_WDT_INTFLAG_OFFSET 0x0006 /* Interrupt flag and status clear register */
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#define SAM_WDT_SYNCBUSY_OFFSET 0x0008 /* Synchronization busy register */
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#define SAM_WDT_CLEAR_OFFSET 0x000c /* Clear register */
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/* WDT register addresses *******************************************************************/
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#define SAM_WDT_CTRLA (SAM_WDT_BASE+SAM_WDT_CTRLA_OFFSET)
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#define SAM_WDT_CONFIG (SAM_WDT_BASE+SAM_WDT_CONFIG_OFFSET)
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#define SAM_WDT_EWCTRL (SAM_WDT_BASE+SAM_WDT_EWCTRL_OFFSET)
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#define SAM_WDT_INTENCLR (SAM_WDT_BASE+SAM_WDT_INTENCLR_OFFSET)
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#define SAM_WDT_INTENSET (SAM_WDT_BASE+SAM_WDT_INTENSET_OFFSET)
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#define SAM_WDT_INTFLAG (SAM_WDT_BASE+SAM_WDT_INTFLAG_OFFSET)
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#define SAM_WDT_SYNCBUSY (SAM_WDT_BASE+SAM_WDT_SYNCBUSY_OFFSET)
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#define SAM_WDT_CLEAR (SAM_WDT_BASE+SAM_WDT_CLEAR_OFFSET)
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/* WDT register bit definitions *************************************************************/
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/* Control register */
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#define WDT_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable */
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#define WDT_CTRLA_WEN (1 << 2) /* Bit 2: Watchdog Timer Window Mode Enable */
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#define WDT_CTRLA_ALWAYSON (1 << 7) /* Bit 7: Always-On */
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/* Configuration register */
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#define WDT_CONFIG_PER_SHIFT (0) /* Bits 0–3: Time-Out Period */
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#define WDT_CONFIG_PER_MASK (15 << WDT_CONFIG_PER_SHIFT)
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# define WDT_CONFIG_PER_8 (0 << WDT_CONFIG_PER_SHIFT) /* 8 clock cycles */
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# define WDT_CONFIG_PER_16 (1 << WDT_CONFIG_PER_SHIFT) /* 16 clock cycles */
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# define WDT_CONFIG_PER_32 (2 << WDT_CONFIG_PER_SHIFT) /* 32 clock cycles */
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# define WDT_CONFIG_PER_64 (3 << WDT_CONFIG_PER_SHIFT) /* 64 clock cycles */
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# define WDT_CONFIG_PER_128 (4 << WDT_CONFIG_PER_SHIFT) /* 128 clock cycles */
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# define WDT_CONFIG_PER_256 (5 << WDT_CONFIG_PER_SHIFT) /* 256 clocks cycles */
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# define WDT_CONFIG_PER_512 (6 << WDT_CONFIG_PER_SHIFT) /* 512 clocks cycles */
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# define WDT_CONFIG_PER_1K (7 << WDT_CONFIG_PER_SHIFT) /* 1024 clock cycles */
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# define WDT_CONFIG_PER_2K (8 << WDT_CONFIG_PER_SHIFT) /* 2048 clock cycles */
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# define WDT_CONFIG_PER_4K (9 << WDT_CONFIG_PER_SHIFT) /* 4096 clock cycles */
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# define WDT_CONFIG_PER_8k (10 << WDT_CONFIG_PER_SHIFT) /* 8192 clock cycles */
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# define WDT_CONFIG_PER_16K (11 << WDT_CONFIG_PER_SHIFT) /* 16384 clock cycles */
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#define WDT_CONFIG_WINDOW_SHIFT (4) /* Bits 4-7: Window Mode Time-Out Period */
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#define WDT_CONFIG_WINDOW_MASK (15 << WDT_CONFIG_WINDOW_SHIFT)
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# define WDT_CONFIG_WINDOW_8 (0 << WDT_CONFIG_WINDOW_SHIFT) /* 8 clock cycles */
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# define WDT_CONFIG_WINDOW_16 (1 << WDT_CONFIG_WINDOW_SHIFT) /* 16 clock cycles */
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# define WDT_CONFIG_WINDOW_32 (2 << WDT_CONFIG_WINDOW_SHIFT) /* 32 clock cycles */
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# define WDT_CONFIG_WINDOW_64 (3 << WDT_CONFIG_WINDOW_SHIFT) /* 64 clock cycles */
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# define WDT_CONFIG_WINDOW_128 (4 << WDT_CONFIG_WINDOW_SHIFT) /* 128 clock cycles */
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# define WDT_CONFIG_WINDOW_256 (5 << WDT_CONFIG_WINDOW_SHIFT) /* 256 clocks cycles */
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# define WDT_CONFIG_WINDOW_512 (6 << WDT_CONFIG_WINDOW_SHIFT) /* 512 clocks cycles */
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# define WDT_CONFIG_WINDOW_1K (7 << WDT_CONFIG_WINDOW_SHIFT) /* 1024 clock cycles */
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# define WDT_CONFIG_WINDOW_2K (8 << WDT_CONFIG_WINDOW_SHIFT) /* 2048 clock cycles */
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# define WDT_CONFIG_WINDOW_4K (9 << WDT_CONFIG_WINDOW_SHIFT) /* 4096 clock cycles */
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# define WDT_CONFIG_WINDOW_8k (10 << WDT_CONFIG_WINDOW_SHIFT) /* 8192 clock cycles */
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# define WDT_CONFIG_WINDOW_16K (11 << WDT_CONFIG_WINDOW_SHIFT) /* 16384 clock cycles */
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/* Early warning interrupt control register */
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#define WDT_EWCTRL_EWOFFSET_SHIFT (0) /* Bits 0-3: Early warning interrupt time offset */
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#define WDT_EWCTRL_EWOFFSET_MASK (15 << WDT_EWCTRL_EWOFFSET_SHIFT)
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# define WDT_EWCTRL_EWOFFSET_8 (0 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_16 (1 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_32 (2 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 32 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_64 (3 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 64 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_128 (4 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 128 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_256 (5 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 256 clocks cycles */
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# define WDT_EWCTRL_EWOFFSET_512 (6 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 512 clocks cycles */
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# define WDT_EWCTRL_EWOFFSET_1K (7 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 1024 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_2K (8 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 2048 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_4K (9 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 4096 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_8k (10 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 8192 clock cycles */
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# define WDT_EWCTRL_EWOFFSET_16K (11 << WDT_EWCTRL_EWOFFSET_SHIFT) /* 16384 clock cycles */
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/* Interrupt enable clear, interrupt enable set register, interrupt flag status and clear registers */
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#define WDT_INT_EW (1 << 0) /* Bit 0: Early warning interrupt */
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#define WDT_INT_All (0x01)
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/* Synchronization busy register */
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#define WDT_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: Enable syncrhonization busy */
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#define WDT_SYNCBUSY_WEN (1 << 2) /* Bit 2: Window enable synchronization busy */
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#define WDT_SYNCBUSY_ALWAYSON (1 << 3) /* Bit 3: Always-on synchronization busy */
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#define WDT_SYNCBUSY_CLEAR (1 << 4) /* Bit 4: Clear syncrhonization busy */
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/* Clear register */
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#define WDT_CLEAR_CLEAR_SHIFT (0) /* Bits 0-7: Watchdog clear */
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#define WDT_CLEAR_CLEAR_MASK (0xff << WDT_CLEAR_CLEAR_SHIFT)
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# define WDT_CLEAR_CLEAR (0xa5 << WDT_CLEAR_CLEAR_SHIFT)
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAML21 */
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#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAML_WDT_H */
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