diff --git a/arch/arm/src/xmc4/xmc4_clockconfig.c b/arch/arm/src/xmc4/xmc4_clockconfig.c
index a28cf7fd51..519276f2cd 100644
--- a/arch/arm/src/xmc4/xmc4_clockconfig.c
+++ b/arch/arm/src/xmc4/xmc4_clockconfig.c
@@ -105,13 +105,18 @@
 #define CLKSET_VALUE      (0x00000000)
 #define SYSCLKCR_VALUE    (0x00010001)
 #define CPUCLKCR_VALUE    (0x00000000)
-#define PBCLKCR_VALUE     (0x00000000)
 #define CCUCLKCR_VALUE    (0x00000000)
 #define WDTCLKCR_VALUE    (0x00000000)
 #define EBUCLKCR_VALUE    (0x00000003)
 #define USBCLKCR_VALUE    (0x00010000)
 #define EXTCLKCR_VALUE    (0x01200003)
 
+#if BOARD_PBDIV == 1
+#  define PBCLKCR_VALUE   SCU_PBCLKCR_PBDIV_FCPU
+#else /* BOARD_PBDIV == 2 */
+#  define PBCLKCR_VALUE   SCU_PBCLKCR_PBDIV_DIV2
+#endif
+
 #if ((USBCLKCR_VALUE & SCU_USBCLKCR_USBSEL) == SCU_USBCLKCR_USBSEL_USBPLL)
 #  define USB_DIV         3
 #else
@@ -387,7 +392,7 @@ void xmc4_clock_configure(void)
   /* Before scaling to final frequency we need to setup the clock dividers */
 
   putreg32(SYSCLKCR_VALUE, XMC4_SCU_SYSCLKCR);
-  putreg32(PBCLKCR_VALUE, XMC4_SCU_PBCLKCR);
+  putreg32(PBCLKCR_VALUE,  XMC4_SCU_PBCLKCR);
   putreg32(CPUCLKCR_VALUE, XMC4_SCU_CPUCLKCR);
   putreg32(CCUCLKCR_VALUE, XMC4_SCU_CCUCLKCR);
   putreg32(WDTCLKCR_VALUE, XMC4_SCU_WDTCLKCR);
diff --git a/arch/arm/src/xmc4/xmc4_usic.c b/arch/arm/src/xmc4/xmc4_usic.c
index e22434a637..925c9c0f41 100644
--- a/arch/arm/src/xmc4/xmc4_usic.c
+++ b/arch/arm/src/xmc4/xmc4_usic.c
@@ -448,14 +448,14 @@ int xmc4_usic_baudrate(enum usic_channel_e channel, uint32_t baud,
 
       /* Select and setup the fractional divider */
 
-      regval = USIC_FDR_DM_FRACTIONAL |  (clkdiv_min << USIC_FDR_STEP_SHIFT);
+      regval = USIC_FDR_DM_FRACTIONAL | USIC_FDR_STEP(clkdiv_min);
       putreg32(regval, base + XMC4_USIC_FDR_OFFSET);
 
       /* Setup and enable the baud rate generator */
 
       regval  = getreg32(base + XMC4_USIC_BRG_OFFSET);
       regval &=  ~(USIC_BRG_DCTQ_MASK | USIC_BRG_PDIV_MASK | USIC_BRG_PCTQ_MASK | USIC_BRG_PPPEN);
-      regval |= (USIC_BRG_DCTQ(oversampling - 1) |  USIC_BRG_PDIV(pdiv_int_min - 1));
+      regval |= (USIC_BRG_DCTQ(oversampling - 1) | USIC_BRG_PDIV(pdiv_int_min - 1));
       putreg32(regval, base + XMC4_USIC_BRG_OFFSET);
 
       ret = OK;
diff --git a/configs/xmc4500-relax/include/board.h b/configs/xmc4500-relax/include/board.h
index 9c3121a4b6..f45120a0f2 100644
--- a/configs/xmc4500-relax/include/board.h
+++ b/configs/xmc4500-relax/include/board.h
@@ -53,10 +53,10 @@
 
 /* Clocking *************************************************************************/
 /* Default clock initialization
- * fPLL = 288MHz => fSYS = 288MHz => fCPU = 144MHz
- *                                => fPB  = 144MHz
- *                                => fCCU = 144MHz
- *                                => fETH = 72MHz
+ * fPLL = 288MHz => fSYS = 288MHz => fCPU     = 144MHz
+ *                                => fPERIPH  = 144MHz
+ *                                => fCCU     = 144MHz
+ *                                => fETH     = 72MHz
  *               => fUSB = 48MHz
  *               => fEBU = 72MHz
  *
@@ -79,7 +79,7 @@
 /* Select the external crystal as the PLL clock source */
 
 #define BOARD_PLL_CLOCKSRC_XTAL   1        /* PLL Clock source == extnernal crystal */
-#undef BOARD_PLL_CLOCKSRC_OFI              /* PLL Clock source != internal fast oscillator */
+#undef  BOARD_PLL_CLOCKSRC_OFI             /* PLL Clock source != internal fast oscillator */
 
 /* PLL Configuration:
  *
@@ -95,16 +95,21 @@
 #define BOARD_PLL_K2DIV           1
 #define BOARD_PLL_FREQUENCY       288000000
 
-/* System frequency is divided down from PLL output */
+/* System frequency, fSYS, is divided down from PLL output */
 
 #define BOARD_SYSDIV              1        /* PLL Output divider to get fSYS */
 #define BOARD_SYS_FREQUENCY       288000000
 
-/* CPU frequency may be divided down from system frequency */
+/* CPU frequency, fCPU, may be divided down from system frequency */
 
 #define BOARD_CPUDIV_ENABLE       1        /* Enable PLL dive by 2 for fCPU */
 #define BOARD_CPU_FREQUENCY       144000000
 
+/* The peripheral clock, fPERIPH, derives from fCPU with no division */
+
+#define BOARD_PBDIV               1        /* No division */
+#define BOARD_PERIPH_FREQUENCY    144000000
+
 /* Standby clock source selection
  *
  * BOARD_STDBY_CLOCKSRC_OSI    - Internal 32.768KHz slow oscillator
@@ -112,7 +117,7 @@
  */
 
 #define BOARD_STDBY_CLOCKSRC_OSI   1
-#undef BOARD_STDBY_CLOCKSRC_OSCULP
+#undef  BOARD_STDBY_CLOCKSRC_OSCULP
 #define BOARD_STDBY_FREQUENCY     32768
 
 /* USB PLL settings.