From 34467249b5782d77da65bc6476f3982df2afe3b4 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 19 Mar 2014 07:16:44 -0600 Subject: [PATCH] Improved description of CONFIG_ARMV7M_USEBASEPRI from Vijay Kumar --- ChangeLog | 2 ++ arch/arm/Kconfig | 12 +++++++----- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/ChangeLog b/ChangeLog index 3d1ed0b810..e82906f366 100644 --- a/ChangeLog +++ b/ChangeLog @@ -7009,4 +7009,6 @@ driver (UDP) for the SAM4E (2014-3-17). * Documentation/NuttxPortingGuide.html: Typo fixes from Vijay Kumar (2014-3-18). + * arch/arm/Kconfig: Improved documentation of the use of the + BASEPRI register from Vijay Kumar (2014-3-19). diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 87242b2afe..8ad5794b1d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -248,11 +248,13 @@ config ARMV7M_USEBASEPRI default n depends on ARCH_CORTEXM3 || ARCH_CORTEXM4 ---help--- - Use the BASEPRI register to enable and disable able interrupts. By - default, the PRIMASK register is used for this purpose. This - usually results in hardfaults that are properly handling by the - RTOS. Using the BASEPRI register will avoid these hardfault. - That is needed primarily for integration with some toolchains. + Use the BASEPRI register to enable and disable interrupts. By + default, the PRIMASK register is used for this purpose. This + usually results in hardfaults when supervisor calls are made. + Though, these hardfaults are properly handled by the RTOS, the + hardfaults can confuse some debuggers. With the BASEPRI + register, these hardfaults, will be avoided. For more details see + http://www.nuttx.org/doku.php?id=wiki:nxinternal:svcall config ARCH_HAVE_CMNVECTOR bool