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arch/arm/src/samd5e5: Updates to clock configuration from initial testing. Still does not boot correctly.

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This commit is contained in:
Gregory Nutt 2018-08-31 07:38:52 -06:00
parent 7bea6854e5
commit 345d088661
4 changed files with 32 additions and 24 deletions
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12
arch/arm/src/samd5e5/chip/sam_oscctrl.h
View File

@ -307,15 +307,15 @@
#define OSCCTRL_DPLLCTRLB_DIV_MASK (0x7ff << OSCCTRL_DPLLCTRLB_DIV_SHIFT)
# define OSCCTRL_DPLLCTRLB_DIV(n) ((uint32_t)(n) << OSCCTRL_DPLLCTRLB_DIV_SHIFT)
/* DPLL0 synchronization busy */
/* DPLL0/1 synchronization busy */
#define OSCCTRL_DPLL0STATUS_ENABLE (1 << 1) /* Bit 1: DPLL enable synchronization status */
#define OSCCTRL_DPLL0STATUS_DPLLRATIO (1 << 2) /* Bit 2: DPLL loop divider ratio synchronization status */
#define OSCCTRL_DPLLSYNCBUSY_ENABLE (1 << 1) /* Bit 1: DPLL enable synchronization status */
#define OSCCTRL_DPLLSYNCBUSY_DPLLRATIO (1 << 2) /* Bit 2: DPLL loop divider ratio synchronization status */
/* DPLL0 status */
/* DPLL0/1 status */
#define OSCCTRL_DPLL0STATUS_LOCK (1 << 0) /* Bit 0: DPLL lock status */
#define OSCCTRL_DPLL0STATUS_CLKRDY (1 << 1) /* Bit 1: Output clock ready */
#define OSCCTRL_DPLLSTATUS_LOCK (1 << 0) /* Bit 0: DPLL lock status */
#define OSCCTRL_DPLLSTATUS_CLKRDY (1 << 1) /* Bit 1: Output clock ready */
/********************************************************************************************
* Public Types

24
arch/arm/src/samd5e5/sam_clockconfig.c
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@ -710,10 +710,10 @@ static void sam_dfll_configure(const struct sam_dfll_config_s *config)
/* Set GCLK0 source to OSCULP32K (temporarily) */
regval32 = getreg32(SAM_GCLK_GENCTRL_OFFSET(0));
regval32 &= GCLK_GENCTRL_SRC_MASK;
regval32 = getreg32(SAM_GCLK_GENCTRL(0));
regval32 &= ~GCLK_GENCTRL_SRC_MASK;
regval32 |= GCLK_GENCTRL_SRC_OSCULP32K;
putreg32(regval32, SAM_GCLK_GENCTRL_OFFSET(0));
putreg32(regval32, SAM_GCLK_GENCTRL(0));
/* Disable the DFLL */
@ -907,10 +907,10 @@ static void sam_dfll_gclkready(const struct sam_dfll_config_s *config)
/* Set the source of GLCK0 to to the configured source. */
regval32 = getreg32(SAM_GCLK_GENCTRL_OFFSET(0));
regval32 &= GCLK_GENCTRL_SRC_MASK;
regval32 = getreg32(SAM_GCLK_GENCTRL(0));
regval32 &= ~GCLK_GENCTRL_SRC_MASK;
regval32 |= GCLK_GENCTRL_SRC(config->gclk);
putreg32(regval32, SAM_GCLK_GENCTRL_OFFSET(0));
putreg32(regval32, SAM_GCLK_GENCTRL(0));
}
/****************************************************************************
@ -924,9 +924,11 @@ static void sam_dfll_gclkready(const struct sam_dfll_config_s *config)
static void sam_dpll_gclkchannel(uint8_t chan,
const struct sam_dpll_config_s *config)
{
/* Check if we are using a dedicated GCLK as the reference clock */
/* Check if we are using a dedicated GCLK as the reference clock (vs. the
* common GCLK0).
*/
if (config->refclk == 0)
if (config->refclk != 0)
{
/* Yes.. configure the GCLK channel */
@ -998,11 +1000,11 @@ static void sam_dpll_ready(uintptr_t base,
if (config->enable)
{
uint32_t lockready = (OSCCTRL_DPLL0STATUS_LOCK |
OSCCTRL_DPLL0STATUS_CLKRDY);
uint32_t lockready = (OSCCTRL_DPLLSTATUS_LOCK |
OSCCTRL_DPLLSTATUS_CLKRDY);
do
{
regval = getreg32(base + SAM_OSCCTRL_DPLLSTATUS_OFFSET);
regval = getreg32(base + SAM_OSCCTRL_DPLLSTATUS_OFFSET);
regval &= lockready;
}
while (regval != lockready);

7
arch/arm/src/samd5e5/sam_gclk.c
View File

@ -249,7 +249,7 @@ void sam_gclk_chan_enable(uint8_t channel, uint8_t srcgen, bool wrlock)
/* Wait for clock synchronization */
while ((getreg32(regaddr) &GCLK_PCHCTRL_CHEN) == 0)
while ((getreg32(regaddr) & GCLK_PCHCTRL_CHEN) == 0)
{
}
@ -289,6 +289,9 @@ void sam_gclk_chan_disable(uint8_t channel)
/* Wait for clock synchronization */
while ((getreg32(regaddr) &GCLK_PCHCTRL_CHEN) != 0);
while ((getreg32(regaddr) & GCLK_PCHCTRL_CHEN) != 0)
{
}
leave_critical_section(flags);
}

13
configs/metro-m4/README.txt
View File

@ -25,7 +25,7 @@ Contents
o Unlocking FLASH
o Serial Console
o LEDs
o Run from FLASH
o Run from SRAM
o Configurations
STATUS
@ -60,10 +60,13 @@ STATUS
debugging in the future, I will put an infinite loop, branch-on-self
at the code startup up (__start) so that I can attached the debugger
and step through the initial configuration.
2019-08-03: Added a configuration option to run out of SRAM vs FLASH.
2018-08-03: Added a configuration option to run out of SRAM vs FLASH.
This should be a safer way to do the initial board bring-up since
it does not modify the FLASH image nor does it require unlocking
the FLASH pages.
2018-08-31: I finally have a new Metro M4 and have been successfully
debugging from SRAM. Several errors in clock configuration logic
have been corrected but it still hangs in the clock configuration.
Unlocking FLASH
===============
@ -192,8 +195,8 @@ LEDs
------ ----------------- -----------
D13 PA16 GPIO output
Run from FLASH
==============
Run from SRAM
=============
I bricked my first Metro M4 board because there were problems in the
bring-up logic. These problems left the chip in a bad state that was
@ -216,7 +219,7 @@ Run from FLASH
gdb> mon memu32 0x20000000 << Get the address of initial stack
gdb> mon reg sp 0x200161c4 << Set the initial stack pointer using this address
gdb> mon memu32 0x20000004 << Get the address of __start entry point
gdb> mon reg pc 0x20000264 << Set the PC using this address
gdb> mon reg pc 0x20000264 << Set the PC using this address (without bit 0 set)
gdb> si << Step in just to make sure everything is okay
gdb> [ set breakpoints ]
gdb> c << Then continue until you hit a breakpoint