diff --git a/configs/viewtool-stm32f107/include/board-stm32f103vct6.h b/configs/viewtool-stm32f107/include/board-stm32f103vct6.h
index 04d3c0d00a..54731ecf72 100644
--- a/configs/viewtool-stm32f107/include/board-stm32f103vct6.h
+++ b/configs/viewtool-stm32f107/include/board-stm32f103vct6.h
@@ -110,7 +110,7 @@
 #define STM32_CFGR_USBPRE       0
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
- * otherwise frequency is 2xAPBx. 
+ * otherwise frequency is 2xAPBx.
  * Note: TIM1,8 are on APB2, others on APB1 */
 
 #define STM32_TIM18_FREQUENCY   STM32_HCLK_FREQUENCY
diff --git a/configs/viewtool-stm32f107/include/board-stm32f107vct6.h b/configs/viewtool-stm32f107/include/board-stm32f107vct6.h
index a25955f1e7..1c200a133e 100644
--- a/configs/viewtool-stm32f107/include/board-stm32f107vct6.h
+++ b/configs/viewtool-stm32f107/include/board-stm32f107vct6.h
@@ -111,7 +111,7 @@
  * USB clock = PLLOUT / 1.5 = 72MHz / 1.5 = 48MHz
  */
 
-#define STM32_CFGR_USBPRE       0
+#define STM32_CFGR_OTGFSPRE     0
 
 /* MCO output driven by PLL3. From above, we already have PLL3 input frequency as:
  *
@@ -120,7 +120,7 @@
  * NOTE: The Viewtool DP83848C module has its on, on-board 50MHz clock.  No
  * MCO clock need be provided on that board.
  */
- 
+
 #if defined(CONFIG_STM32_MII_MCO) || defined(CONFIG_STM32_RMII_MCO)
 #  define BOARD_CFGR_MCO_SOURCE RCC_CFGR_PLL3CLK      /* Source: PLL3 */
 #  define STM32_PLL_PLL3MUL     RCC_CFGR2_PLL3MULx10  /* MCO 5MHz * 10 = 50MHz */