SAMV7: Add QSPI Register Definition Header File
This commit is contained in:
Gregory Nutt
parent
150f79a198
commit
348060f5d2
@ -86,7 +86,7 @@
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# define SAMV7_NTCCHIO 36 /* 12 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 5 /* 1 Quad SPI */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 2 /* 2 SPI, SPI0-1 */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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@ -142,7 +142,7 @@
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# define SAMV7_NTCCHIO 9 /* 12 Timer/counter channels I/O */
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# define SAMV7_NUSART 3 /* 3 USARTs */
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# define SAMV7_NUART 5 /* 5 UARTs */
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# define SAMV7_NQSPI 5 /* 1 Quad SPI */
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# define SAMV7_NQSPI 1 /* 1 Quad SPI */
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# define SAMV7_NSPI 1 /* 1 SPI, SPI0 */
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# define SAMV7_NTWIHS 3 /* 3 TWIHS */
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# define SAMV7_NHSMCI4 1 /* 1 4-bit HSMCI port */
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269
arch/arm/src/samv7/chip/sam_qspi.h
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269
arch/arm/src/samv7/chip/sam_qspi.h
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@ -0,0 +1,269 @@
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sam_qspi.h
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* Quad SPI (QSPI) definitions for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/samv7/chip.h>
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#include "chip/sam_memorymap.h"
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#if SAMV7_NQSPI > 0
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* QSPI register offsets *****************************************************************/
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#define SAM_QSPI_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_QSPI_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_QSPI_RDR_OFFSET 0x0008 /* Receive Data Register */
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#define SAM_QSPI_TDR_OFFSET 0x000c /* Transmit Data Register */
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#define SAM_QSPI_SR_OFFSET 0x0010 /* Status Register */
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#define SAM_QSPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */
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#define SAM_QSPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */
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#define SAM_QSPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */
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#define SAM_QSPI_SCR_OFFSET 0x0020 /* Serial Clock Register */
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#define SAM_QSPI_IAR_OFFSET 0x0030 /* Instruction Address Register */
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#define SAM_QSPI_ICR_OFFSET 0x0034 /* Instruction Code Register */
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#define SAM_QSPI_IFR_OFFSET 0x0038 /* Instruction Frame Register */
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/* 0x003c Reserved */
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#define SAM_QSPI_SMR_OFFSET 0x0040 /* Scrambling Mode Register */
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#define SAM_QSPI_SKR_OFFSET 0x0044 /* Scrambling Key Register */
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/* 0x0048–0x00e0 Reserved */
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#define SAM_QSPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
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#define SAM_QSPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
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/* 0xec-0xfc: Reserved */
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/* QSPI register addresses ***************************************************************/
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#define SAM_QSPI0_CR (SAM_QSPI0_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
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#define SAM_QSPI0_MR (SAM_QSPI0_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
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#define SAM_QSPI0_RDR (SAM_QSPI0_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
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#define SAM_QSPI0_TDR (SAM_QSPI0_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
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#define SAM_QSPI0_SR (SAM_QSPI0_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
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#define SAM_QSPI0_IER (SAM_QSPI0_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
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#define SAM_QSPI0_IDR (SAM_QSPI0_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
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#define SAM_QSPI0_IMR (SAM_QSPI0_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
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#define SAM_QSPI0_SCR (SAM_QSPI0_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
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#define SAM_QSPI0_IAR (SAM_QSPI0_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
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#define SAM_QSPI0_ICR (SAM_QSPI0_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
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#define SAM_QSPI0_IFR (SAM_QSPI0_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
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#define SAM_QSPI0_SMR (SAM_QSPI0_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
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#define SAM_QSPI0_SKR (SAM_QSPI0_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
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#define SAM_QSPI0_WPCR (SAM_QSPI0_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
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#define SAM_QSPI0_WPSR (SAM_QSPI0_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
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#if SAMV7_NQSPI > 1
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# define SAM_QSPI1_CR (SAM_QSPI1_BASE+SAM_QSPI_CR_OFFSET) /* Control Register */
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# define SAM_QSPI1_MR (SAM_QSPI1_BASE+SAM_QSPI_MR_OFFSET) /* Mode Register */
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# define SAM_QSPI1_RDR (SAM_QSPI1_BASE+SAM_QSPI_RDR_OFFSET) /* Receive Data Register */
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# define SAM_QSPI1_TDR (SAM_QSPI1_BASE+SAM_QSPI_TDR_OFFSET) /* Transmit Data Register */
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# define SAM_QSPI1_SR (SAM_QSPI1_BASE+SAM_QSPI_SR_OFFSET) /* Status Register */
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# define SAM_QSPI1_IER (SAM_QSPI1_BASE+SAM_QSPI_IER_OFFSET) /* Interrupt Enable Register */
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# define SAM_QSPI1_IDR (SAM_QSPI1_BASE+SAM_QSPI_IDR_OFFSET) /* Interrupt Disable Register */
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# define SAM_QSPI1_IMR (SAM_QSPI1_BASE+SAM_QSPI_IMR_OFFSET) /* Interrupt Mask Register */
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# define SAM_QSPI1_SCR (SAM_QSPI1_BASE+SAM_QSPI_SCR_OFFSET) /* Serial Clock Register */
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# define SAM_QSPI1_IAR (SAM_QSPI1_BASE+SAM_QSPI_IAR_OFFSET) /* Instruction Address Register */
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# define SAM_QSPI1_ICR (SAM_QSPI1_BASE+SAM_QSPI_ICR_OFFSET) /* Instruction Code Register */
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# define SAM_QSPI1_IFR (SAM_QSPI1_BASE+SAM_QSPI_IFR_OFFSET) /* Instruction Frame Register */
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# define SAM_QSPI1_SMR (SAM_QSPI1_BASE+SAM_QSPI_SMR_OFFSET) /* Scrambling Mode Register */
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# define SAM_QSPI1_SKR (SAM_QSPI1_BASE+SAM_QSPI_SKR_OFFSET) /* Scrambling Key Register */
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# define SAM_QSPI1_WPCR (SAM_QSPI1_BASE+SAM_QSPI_WPCR_OFFSET) /* Write Protection Control Register */
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# define SAM_QSPI1_WPSR (SAM_QSPI1_BASE+SAM_QSPI_WPSR_OFFSET) /* Write Protection Status Register */
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#endif
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/* QSPI register bit definitions *********************************************************/
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/* QSPI Control Register */
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#define QSPI_CR_QSPIEN (1 << 0) /* Bit 0: QSPI Enable */
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#define QSPI_CR_QSPIDIS (1 << 1) /* Bit 1: QSPI Disable */
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#define QSPI_CR_SWRST (1 << 7) /* Bit 7: QSPI Software Reset */
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#define QSPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* QSPI Mode Register */
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#define QSPI_MR_SMM (1 << 0) /* Bit 0: Serial Memory Mode */
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#define QSPI_MR_LLB (1 << 1) /* Bit 1: Local Loopback Enable */
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#define QSPI_MR_WDRBT (1 << 2) /* Bit 2: Wait Data Read Before Transfer */
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#define QSPI_MR_CSMODE_SHIFT (4) /* Bits 4-5: Chip Select Mode */
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#define QSPI_MR_CSMODE_MASK (3 << QSPI_MR_PCS_SHIFT)
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# define QSPI_MR_CSMODE_NRELOAD (0 << QSPI_MR_PCS_SHIFT) /* CS deasserted if TD not reloaded */
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# define QSPI_MR_CSMODE_LASTXFER (1 << QSPI_MR_PCS_SHIFT) /* CS deasserted when LASTXFER transferred */
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# define QSPI_MR_CSMODE_SYSTEM (2 << QSPI_MR_PCS_SHIFT) /* CS deasserted after each transfer */
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#define QSPI_MR_NBBITS_SHIFT (8) /* Bits 8-11: Number Of Bits Per Transfer */
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#define QSPI_MR_NBBITS_MASK (15 << QSPI_MR_NBBITS_SHIFT)
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# define QSPI_MR_NBBITS(n) ((uint32_t)((n)-8) << QSPI_MR_NBBITS_SHIFT)
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# define QSPI_MR_NBBITS_8BIT (0 << QSPI_MR_NBBITS_SHIFT) /* 8 bits for transfer */
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# define QSPI_MR_NBBITS_9BIT (1 << QSPI_MR_NBBITS_SHIFT) /* 9 bits for transfer */
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# define QSPI_MR_NBBITS_10BIT (2 << QSPI_MR_NBBITS_SHIFT) /* 10 bits for transfer */
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# define QSPI_MR_NBBITS_11BIT (3 << QSPI_MR_NBBITS_SHIFT) /* 11 bits for transfer */
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# define QSPI_MR_NBBITS_12BIT (4 << QSPI_MR_NBBITS_SHIFT) /* 12 bits for transfer */
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# define QSPI_MR_NBBITS_13BIT (5 << QSPI_MR_NBBITS_SHIFT) /* 13 bits for transfer */
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# define QSPI_MR_NBBITS_14BIT (6 << QSPI_MR_NBBITS_SHIFT) /* 14 bits for transfer */
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# define QSPI_MR_NBBITS_15BIT (7 << QSPI_MR_NBBITS_SHIFT) /* 15 bits for transfer */
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# define QSPI_MR_NBBITS_16BIT (8 << QSPI_MR_NBBITS_SHIFT) /* 16 bits for transfer */
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#define QSPI_MR_DLYBCT_SHIFT (16) /* Bits 16-23: Delay Between Consecutive Transfers */
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#define QSPI_MR_DLYBCT_MASK (0xff << QSPI_MR_DLYBCT_SHIFT)
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# define QSPI_MR_DLYBCT(n) ((uint32_t)(n) << QSPI_MR_DLYBCT_SHIFT)
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#define QSPI_MR_DLYCS_SHIFT (24) /* Bits 24-31: Minimum Inactive QCS Delay */
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#define QSPI_MR_DLYCS_MASK (0xff << QSPI_MR_DLYCS_SHIFT)
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# define QSPI_MR_DLYCS(n) ((uint32_t)(n) << QSPI_MR_DLYCS_SHIFT)
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/* QSPI Receive Data Register */
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#define QSPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
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#define QSPI_RDR_RD_MASK (0xffff << QSPI_RDR_RD_SHIFT)
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/* QSPI Transmit Data Register */
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#define QSPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
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#define QSPI_TDR_TD_MASK (0xffff << QSPI_TDR_TD_SHIFT)
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/* QSPI Status Register, QSPI Interrupt Enable Register, QSPI Interrupt Disable Register,
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* and QSPI Interrupt Mask Register (common bit fields)
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*/
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#define QSPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
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#define QSPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
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#define QSPI_INT_TXEMPTY (1 << 2) /* Bit 2: Transmission Registers Empty Interrupt */
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#define QSPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
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#define QSPI_INT_CSR (1 << 8) /* Bit 8: Chip Select Rise Interrupt */
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#define QSPI_SR_CSS (1 << 9) /* Bit 9: Chip Select Status Interrupt */
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#define QSPI_SR_INTSTRE (1 << 10) /* Bit 10: Instruction End Status Interrupt */
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#define QSPI_SR_QSPIENS (1 << 24) /* Bit 24: QSPI Enable Status (SR only) */
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#define QSPI_INT_ALL (0x0000070f)
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/* Serial Clock Register */
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#define QSPI_SCR_
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#define QSPI_SCR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
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#define QSPI_SCR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
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#define QSPI_SCR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
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#define QSPI_SCR_SCBR_MASK (0xff << QSPI_SCR_SCBR_SHIFT)
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# define QSPI_SCR_SCBR(n) ((uint32_t)(n) << QSPI_SCR_SCBR_SHIFT)
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#define QSPI_SCR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before QSCK */
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#define QSPI_SCR_DLYBS_MASK (0xff << QSPI_SCR_DLYBS_SHIFT)
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# define QSPI_SCR_DLYBS(n) ((uint32_t)(n) << QSPI_SCR_DLYBS_SHIFT)
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/* Instruction Address Register (32-bit value) */
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/* Instruction Code Register */
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#define QSPI_ICR_INST_SHIFT (0) /* Bits 0-7: Instruction Code */
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#define QSPI_ICR_INST_MASK (0xff << QSPI_ICR_INST_SHIFT)
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# define QSPI_ICR_INST(n) ((uint32_t)(n) << QSPI_ICR_INST_SHIFT)
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#define QSPI_ICR_OPT_SHIFT (16) /* Bits 16-23: Option Code */
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#define QSPI_ICR_OPT_MASK (0xff << QSPI_ICR_OPT_SHIFT)
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# define QSPI_ICR_OPT(n) ((uint32_t)(n) << QSPI_ICR_OPT_SHIFT)
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/* Instruction Frame Register */
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#define QSPI_IFR_WIDTH_SHIFT (0) /* Bits 0-2: Width of Instruction Code,
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* Address, Option Code and Data */
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#define QSPI_IFR_WIDTH_MASK (7 << QSPI_IFR_WIDTH_SHIFT)
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/* Instruction Address-Option Data */
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# define QSPI_IFR_WIDTH_SINGLE (0 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Single-bit */
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# define QSPI_IFR_WIDTH_DUALOUT (1 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Dual */
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# define QSPI_IFR_WIDTH_QUADOUT (2 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Single-bit Quad */
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# define QSPI_IFR_WIDTH_DUALIO (3 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Dual Dual */
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# define QSPI_IFR_WIDTH_QUADIO (4 << QSPI_IFR_WIDTH_SHIFT) /* Single-bit Quad Quad */
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# define QSPI_IFR_WIDTH_DUALCMD (5 << QSPI_IFR_WIDTH_SHIFT) /* Dual Dual Dual */
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# define QSPI_IFR_WIDTH_QUADCMD (6 << QSPI_IFR_WIDTH_SHIFT) /* Quad Quad Quad */
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#define QSPI_IFR_INSTEN (1 << 4) /* Bit 4: Instruction Enable */
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#define QSPI_IFR_ADDREN (1 << 5) /* Bit 5: Address Enable */
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#define QSPI_IFR_OPTEN (1 << 6) /* Bit 6: Option Enable */
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#define QSPI_IFR_DATAEN (1 << 7) /* Bit 7: Data Enable */
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#define QSPI_IFR_OPTL_SHIFT (8) /* Bits 8-9: Option Code Length */
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#define QSPI_IFR_OPTL_MASK (3 << QSPI_IFR_OPTL_SHIFT)
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# define QSPI_IFR_OPTL_1BIT (0 << QSPI_IFR_OPTL_SHIFT) /* Option is 1 bit */
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# define QSPI_IFR_OPTL_2BIT (1 << QSPI_IFR_OPTL_SHIFT) /* Option is 2 bits */
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# define QSPI_IFR_OPTL_4BIT (2 << QSPI_IFR_OPTL_SHIFT) /* Option is 4 bits */
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# define QSPI_IFR_OPTL_8BIT (3 << QSPI_IFR_OPTL_SHIFT) /* Option is 8 bits */
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#define QSPI_IFR_ADDRL (1 << 10) /* Bit 10: Address Length */
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#define QSPI_IFR_TFRTYP_SHIFT (12) /* Bits 12-13: Data Transfer Type */
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#define QSPI_IFR_TFRTYP_MASK (3 << QSPI_IFR_TFRTYP_SHIFT)
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# define QSPI_IFR_TFRTYP_READ (0 << QSPI_IFR_TFRTYP_SHIFT) /* Read transfer from serial memory */
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# define QSPI_IFR_TFRTYP_RDMEM (1 << QSPI_IFR_TFRTYP_SHIFT) /* Read data transfer from serial memory */
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# define QSPI_IFR_TFRTYP_WRITE (2 << QSPI_IFR_TFRTYP_SHIFT) /* Write transfer into serial memory */
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# define QSPI_IFR_TFRTYP_WRMEM (3 << QSPI_IFR_TFRTYP_SHIFT) /* Write data transfer the serial memory */
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#define QSPI_IFR_CRM (1 << 14) /* Bit 14: Continuous Read Mode */
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#define QSPI_IFR_NBDUM_SHIFT (16) /* Bits 16-20: Number Of Dummy Cycles */
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#define QSPI_IFR_NBDUM_MASK (31 << QSPI_IFR_NBDUM_SHIFT)
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# define QSPI_IFR_NBDUM(n) ((uint32_t)(n) << QSPI_IFR_NBDUM_SHIFT)
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/* Scrambling Mode Register */
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#define QSPI_SMR_SCREN (1 << 0) /* Bit 0: Scrambling/Unscrambling Enable */
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#define QSPI_SMR_RVDIS (1 << 1) /* Bit 1: Scrambling/Unscrambling Random Value Disable */
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/* Scrambling Key Register (32-bit value) */
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/* QSPI Write Protection Control Register */
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#define QSPI_WPCR_WPEN (1 << 0) /* Bit 0: QSPI Write Protection Enable */
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#define QSPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: QSPI Write Protection Key Password */
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#define QSPI_WPCR_WPKEY_MASK (0x00ffffff << QSPI_WPCR_WPKEY_SHIFT)
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# define QSPI_WPCR_WPKEY (0x00515350 << QSPI_WPCR_WPKEY_SHIFT)
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/* QSPI Write Protection Status Register */
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#define QSPI_WPSR_WPVS (1 << 0) /* Bit 0: QSPI Write Protection Violation Status */
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#define QSPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: QSPI Write Protection Violation Source */
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#define QSPI_WPSR_WPVSRC_MASK (0xff << QSPI_WPSR_WPVSRC_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* SAMV7_NQSPI > 0 */
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_QSPI_H */
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