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arch/arm: The last big change that unified the cache interfaces had a bad side-effect: It also removed the memory barrier definitions that were also in the removed architecture-specific cache.h header files. Fixed by adding a new barriers.h header file that provides these definitions.

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This commit is contained in:
Gregory Nutt 2019-03-19 13:12:19 -06:00
parent 0e4051a6b6
commit 348a03287d
16 changed files with 86 additions and 61 deletions
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57
arch/arm/src/armv7-m/barriers.h Normal file
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@ -0,0 +1,57 @@
/************************************************************************************
* arch/arm/src/armv7-m/barriers.h
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_COMMON_ARMV7_M_BARRIERS_H
#define __ARCH_ARM_SRC_COMMON_ARMV7_M_BARRIERS_H
/************************************************************************************
* Included Files
************************************************************************************/
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* ARMv7-M memory barriers */
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
#endif /* __ARCH_ARM_SRC_COMMON_ARMV7_M_BARRIERS_H */

13
arch/arm/src/armv7-m/up_cache.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_cache.c
*
* Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2018-2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Bob Feretich <bob.feretich@rafresearch.com>
*
@ -47,6 +47,7 @@
#include <nuttx/cache.h>
#include "up_arch.h"
#include "barriers.h"
#include "nvic.h"
/****************************************************************************
@ -71,16 +72,6 @@
#define CCSIDR_LSSHIFT(n) \
(((n) & NVIC_CCSIDR_LINESIZE_MASK) >> NVIC_CCSIDR_LINESIZE_SHIFT)
/* intrinsics are used in these inline functions */
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
/****************************************************************************
* Inline Functions
****************************************************************************/

2
arch/arm/src/imxrt/imxrt_mpuinit.c
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@ -44,6 +44,8 @@
#include <nuttx/userspace.h>
#include "mpu.h"
#include "barriers.h"
#include "chip/imxrt_memorymap.h"
#include "imxrt_mpuinit.h"

3
arch/arm/src/imxrt/imxrt_start.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/imxrt/imxrt_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -49,6 +49,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "barriers.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"

2
arch/arm/src/nrf52/nrf52_nvmc.c
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@ -45,6 +45,8 @@
#include <nuttx/config.h>
#include <stdbool.h>
#include "barriers.h"
#include "chip/nrf52_ficr.h"
#include "chip/nrf52_nvmc.h"
#include "nrf52_nvmc.h"

2
arch/arm/src/samv7/sam_mpuinit.c
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@ -44,6 +44,8 @@
#include <nuttx/userspace.h>
#include "mpu.h"
#include "barriers.h"
#include "chip/sam_memorymap.h"
#include "sam_mpuinit.h"

2
arch/arm/src/samv7/sam_progmem.c
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@ -47,6 +47,8 @@
#include <arch/samv7/chip.h>
#include "up_arch.h"
#include "barriers.h"
#include "chip/sam_memorymap.h"
#include "sam_progmem.h"

3
arch/arm/src/samv7/sam_qspi.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam_qspi.c
*
* Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2017, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -60,6 +60,7 @@
#include "up_internal.h"
#include "up_arch.h"
#include "barriers.h"
#include "sam_gpio.h"
#include "sam_xdmac.h"

3
arch/arm/src/samv7/sam_start.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam_start.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -49,6 +49,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "barriers.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"

3
arch/arm/src/samv7/sam_usbdevhs.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/samv7/sam_usbdevhs.c
*
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2015-2016, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.orgr>
*
* This code derives from the UDPHS device controller driver for the SAMA5D3.
@ -70,6 +70,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "barriers.h"
#include "chip.h"
#include "sam_periphclks.h"

1
arch/arm/src/stm32f7/stm32_ethernet.c
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@ -62,6 +62,7 @@
#endif
#include "up_internal.h"
#include "barriers.h"
#include "chip/stm32_syscfg.h"
#include "chip/stm32_pinmap.h"

2
arch/arm/src/stm32f7/stm32_flash.c
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@ -58,6 +58,8 @@
#include <assert.h>
#include <errno.h>
#include "barriers.h"
#include "chip/stm32_flash.h"
#include "up_arch.h"

4
arch/arm/src/stm32f7/stm32_start.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_start.c
*
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2015, 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -49,6 +49,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "barriers.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"
@ -62,6 +63,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Memory Map ***************************************************************/
/*
* 0x0400:0000 - Beginning of the internal FLASH. Address of vectors.

3
arch/arm/src/stm32h7/stm32_start.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32h7/stm32_start.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Copyright (C) 2018-2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@ -49,6 +49,7 @@
#include "up_arch.h"
#include "up_internal.h"
#include "barriers.h"
#ifdef CONFIG_ARCH_FPU
# include "nvic.h"

1
arch/arm/src/stm32l4/stm32l4_qspi.c
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@ -60,6 +60,7 @@
#include "up_internal.h"
#include "up_arch.h"
#include "barriers.h"
#include "stm32l4_gpio.h"
#include "stm32l4_dma.h"

46
arch/arm/src/stm32l4/stm32l4_sdmmc.c
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@ -2784,10 +2784,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
* Name: stm32_dmarecvsetup
*
* Description:
* Setup to perform a read DMA. If the processor supports a data cache,
* then this method will also make sure that the contents of the DMA memory
* and the data cache are coherent. For read transfers this may mean
* invalidating the data cache.
* Setup to perform a read DMA.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
@ -2809,21 +2806,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT
DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
#else
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because the up_invalidate_dcache could lose
* buffered buffered writes if the buffer alignment and sizes are not on
* ARMV7M_DCACHE_LINESIZE boundaries.
*/
if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 ||
(buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0)
{
return -EFAULT;
}
# endif
#endif
/* Reset the DPSM configuration */
@ -2856,10 +2838,6 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
(uint32_t)buffer, (buflen + 3) >> 2,
SDMMC_RXDMA32_CONFIG | priv->dmapri);
/* Force RAM reread */
up_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen);
/* Start the DMA */
stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE);
@ -2874,10 +2852,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
* Name: stm32_dmasendsetup
*
* Description:
* Setup to perform a write DMA. If the processor supports a data cache,
* then this method will also make sure that the contents of the DMA memory
* and the data cache are coherent. For write transfers, this may mean
* flushing the data cache.
* Setup to perform a write DMA.
*
* Input Parameters:
* dev - An instance of the SDIO device interface
@ -2900,19 +2875,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT
DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
#else
# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
/* buffer alignment is required for DMA transfers with dcache in buffered
* mode (not write-through) because the up_flush_dcache would corrupt adjacent
* memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE
* boundaries.
*/
if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 ||
(buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0)
{
return -EFAULT;
}
# endif
#endif
/* Reset the DPSM configuration */
@ -2924,10 +2886,6 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
stm32_sampleinit();
stm32_sample(priv, SAMPLENDX_BEFORE_SETUP);
/* Flush cache to physical memory */
up_flush_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *)buffer;