Fix many coding styles issues
This commit is contained in:
Alan C. Assis
patacongo
parent
4d0f05c340
commit
34c144ad13
@ -85,18 +85,21 @@ static void esp32_set_cpu_freq(int cpu_freq_mhz)
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case 160:
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per_conf = CPU_160M;
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break;
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case 240:
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dbias = DIG_DBIAS_240M;
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per_conf = CPU_240M;
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break;
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case 80:
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per_conf = CPU_80M;
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default:
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break;
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}
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value = (((80 * MHZ) >> 12) & UINT16_MAX)
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| ((((80 * MHZ) >> 12) & UINT16_MAX) << 16);
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value = (((80 * MHZ) >> 12) & UINT16_MAX) |
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((((80 * MHZ) >> 12) & UINT16_MAX) << 16);
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putreg32(value, RTC_APB_FREQ_REG);
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putreg32(per_conf, DPORT_CPU_PER_CONF_REG);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias);
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@ -150,6 +153,7 @@ static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
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dcur = 6;
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bw = 3;
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break;
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case XTAL_26M:
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div_ref = 12;
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div7_0 = 224;
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@ -158,6 +162,7 @@ static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
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dcur = 0;
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bw = 1;
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break;
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case XTAL_24M:
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div_ref = 11;
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div7_0 = 224;
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@ -166,6 +171,7 @@ static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
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dcur = 0;
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bw = 1;
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break;
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default:
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div_ref = 12;
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div7_0 = 224;
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@ -199,6 +205,7 @@ static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
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dcur = 6;
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bw = 3;
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break;
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case XTAL_26M:
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div_ref = 12;
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div7_0 = 144;
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@ -207,6 +214,7 @@ static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
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dcur = 0;
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bw = 1;
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break;
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case XTAL_24M:
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div_ref = 11;
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div7_0 = 144;
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@ -215,6 +223,7 @@ static void esp32_bbpll_configure(enum xtal_freq_e xtal_freq, int pll_freq)
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dcur = 0;
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bw = 1;
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break;
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default:
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div_ref = 12;
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div7_0 = 224;
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@ -344,9 +353,11 @@ void esp32_clockconfig(void)
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case 240:
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source_freq_mhz = RTC_PLL_FREQ_480M;
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break;
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case 160:
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source_freq_mhz = RTC_PLL_FREQ_320M;
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break;
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case 80:
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default:
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return;
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@ -188,16 +188,16 @@
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/* Periheral Clock */
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#define APB_CLK_FREQ_ROM 26*1000000
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#define APB_CLK_FREQ_ROM 26 * 1000000
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#define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM
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#define CPU_CLK_FREQ APB_CLK_FREQ
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#define APB_CLK_FREQ 80*1000000 /* Unit: Hz */
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#define REF_CLK_FREQ ( 1000000 )
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#define APB_CLK_FREQ 80 * 1000000 /* Unit: Hz */
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#define REF_CLK_FREQ (1000000)
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#define UART_CLK_FREQ APB_CLK_FREQ
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#define WDT_CLK_FREQ APB_CLK_FREQ
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#define TIMER_CLK_FREQ (80000000>>4) /* 80MHz divided by 16 */
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#define TIMER_CLK_FREQ (80000000 >> 4) /* 80MHz divided by 16 */
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#define SPI_CLK_DIV 4
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#define TICKS_PER_US_ROM 26 /* CPU is 80MHz */
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#define TICKS_PER_US_ROM 26 /* CPU is 80MHz */
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#define DR_REG_DPORT_BASE 0x3ff00000
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#define DR_REG_UART_BASE 0x3ff40000
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@ -407,8 +407,8 @@
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#define I2C_BBPLL_ENDIV5 11
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#define I2C_BBPLL 0x66
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#define I2C_BBPLL_HOSTID 4
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#define I2C_BBPLL 0x66
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#define I2C_BBPLL_HOSTID 4
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extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
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int indata);
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@ -429,46 +429,46 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
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#define BBPLL_OC_ENB_VCON_VAL 0x00
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#define BBPLL_BBADC_CAL_7_0_VAL 0x00
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#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
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#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
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#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
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#define EFUSE_BLK0_RDATA5_REG (DR_REG_EFUSE_BASE + 0x014)
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#define EFUSE_RD_VOL_LEVEL_HP_INV 0x03
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#define EFUSE_RD_VOL_LEVEL_HP_INV_S 22
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
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#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
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#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + i*0x1000)
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#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068)
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#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
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#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4)
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#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0)
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#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4)
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#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
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#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
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#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
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#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
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#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70)
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#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70)
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#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30)
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#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30)
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#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0)
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#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
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#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0)
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#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
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/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
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* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
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* Valid if RTC_CNTL_DBG_ATTEN is 0.
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*/
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#define RTC_CNTL_DBIAS_1V00 2
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#define RTC_CNTL_DBIAS_1V10 4
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#define RTC_CNTL_DBIAS_1V25 7
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#define RTC_CNTL_DBIAS_1V00 2
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#define RTC_CNTL_DBIAS_1V10 4
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#define RTC_CNTL_DBIAS_1V25 7
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/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
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#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007
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#define RTC_CNTL_DIG_DBIAS_WAK_S 11
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#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007
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#define RTC_CNTL_DIG_DBIAS_WAK_S 11
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/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ;
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* description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL
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*/
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#define RTC_CNTL_SOC_CLK_SEL 0x00000003
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#define RTC_CNTL_SOC_CLK_SEL_S 27
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#define RTC_CNTL_SOC_CLK_SEL 0x00000003
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#define RTC_CNTL_SOC_CLK_SEL_S 27
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#define RTC_CNTL_SOC_CLK_SEL_XTL 0
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#define RTC_CNTL_SOC_CLK_SEL_PLL 1
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#define RTC_CNTL_SOC_CLK_SEL_8M 2
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@ -481,44 +481,46 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
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* proper voltage for these two cases.
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*/
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#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, EFUSE_RD_VOL_LEVEL_HP_INV)))
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#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - \
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(REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, \
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EFUSE_RD_VOL_LEVEL_HP_INV)))
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#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT
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#else
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
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#endif
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT
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#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
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#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
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#define DELAY_PLL_DBIAS_RAISE 3
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#define DELAY_PLL_ENABLE_WITH_150K 80
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#define DELAY_PLL_ENABLE_WITH_32K 160
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#define DELAY_PLL_DBIAS_RAISE 3
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#define DELAY_PLL_ENABLE_WITH_150K 80
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#define DELAY_PLL_ENABLE_WITH_32K 160
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/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ;
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* description: BB_I2C force power down
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*/
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#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
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#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6))
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/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ;
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* description: BB_PLL force power down
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*/
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#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
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#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10))
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/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ;
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* description: BB_PLL _I2C force power down
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*/
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#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
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#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8))
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/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ;
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* description: PLLA force power down
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*/
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#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
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#define RTC_CNTL_PLLA_FORCE_PD_S 23
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#define RTC_CNTL_PLLA_FORCE_PD (BIT(23))
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#define RTC_CNTL_PLLA_FORCE_PD_S 23
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/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ;
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* description: BIAS_I2C force power down
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@ -527,7 +529,7 @@ extern int rom_i2c_writeReg(int block, int block_id, int reg_add,
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#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18))
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#define MHZ (1000000)
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#define RTC_PLL_FREQ_320M 320
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#define RTC_PLL_FREQ_480M 480
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#define RTC_PLL_FREQ_320M 320
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#define RTC_PLL_FREQ_480M 480
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#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_SOC_H */
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