SAMV71 MAN configuration data
This commit is contained in:
Gregory Nutt
parent
a5755cb378
commit
34c3c780e1
@ -107,33 +107,41 @@
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/* MCAN0 Configuration ******************************************************/
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#ifdef CONFIG_SAMV7_MCAN0
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# if (CONFIG_SAMV7_MCAN0_NSTDFILTERS > 128)
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# error Invalid MCAN0 number of Standard Filters
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/* Bit timing */
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# define MCAN0_TSEG1 (CONFIG_SAMV7_MCAN0_PROPSEG + CONFIG_SAMV7_MCAN0_PHASESEG1)
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# define MCAN0_TSEG2 CONFIG_SAMV7_MCAN0_PHASESEG2
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# define MCAN0_BRP ((uint32_t)(((float) SAMV7_MCANCLK_FREQUENCY / \
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((float)(MCAN0_TSEG1 + MCAN0_TSEG2 + 3) * \
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(float)CONFIG_SAMV7_MCAN0_BITRATE)) - 1))
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# define MCAN0_SJW (CONFIG_SAMV7_MCAN0_FSJW - 1)
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# if MCAN0_TSEG1 > 63
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# error Invalid MCAN0 TSEG1
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# endif
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# if MCAN0_TSEG2 > 15
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# error Invalid MCAN0 TSEG2
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# endif
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# if MCAN0_SJW > 15
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# error Invalid MCAN0 SJW
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# endif
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# if (CONFIG_SAMV7_MCAN0_NEXTFILTERS > 64)
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# error Invalid MCAN0 number of Extended Filters
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# endif
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# define MCAN0_FTSEG1 (CONFIG_SAMV7_MCAN0_FPROPSEG + CONFIG_SAMV7_MCAN0_FPHASESEG1)
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# define MCAN0_FTSEG2 (CONFIG_SAMV7_MCAN0_FPHASESEG2)
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# define MCAN0_FBRP ((uint32_t)(((float) SAMV7_MCANCLK_FREQUENCY / \
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((float)(MCAN0_FTSEG1 + MCAN0_FTSEG2 + 3) * \
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(float)CONFIG_SAMV7_MCAN0_FBITRATE)) - 1))
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# define MCAN0_FSJW (CONFIG_SAMV7_MCAN0_FFSJW - 1)
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# if (CONFIG_SAMV7_MCAN0_RXFIFO0_SIZE > 64)
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# error Invalid MCAN0 number of RX FIFO0 elements
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# if MCAN0_FTSEG1 > 15
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# error Invalid MCAN0 FTSEG1
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# endif
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# if (CONFIG_SAMV7_MCAN0_RXFIFO1_SIZE > 64)
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# error Invalid MCAN0 number of RX FIFO1 elements
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# if MCAN0_FTSEG2 > 7
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# error Invalid MCAN0 FTSEG2
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# endif
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# if (CONFIG_SAMV7_MCAN0_DEDICATED_RXBUFFER_SIZE > 64)
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# error Invalid MCAN0 number of RX BUFFER elements
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# endif
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# if (CONFIG_SAMV7_MCAN0_TXEVENTFIFO_SIZE > 32)
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# error Invalid MCAN0 number of TX EVENT FIFO elements
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# endif
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# if ((CONFIG_SAMV7_MCAN0_DEDICATED_TXBUFFER_SIZE + \
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CONFIG_SAMV7_MCAN0_DEDICATED_TXFIFOQ_SIZE) > 32)
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# error Invalid MCAN0 number of TX BUFFER elements
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# if MCAN0_FSJW > 3
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# error Invalid MCAN0 FSJW
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# endif
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/* MCAN0 RX FIFO0 element size */
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@ -166,6 +174,13 @@
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# error Undefined MCAN0 RX FIFO0 element size
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# endif
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# if CONFIG_SAMV7_MCAN0_RXFIFO0_SIZE > 64
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# error Invalid MCAN0 number of RX FIFO0 elements
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# endif
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# define MCAN0_RXFIFO0_WORDS \
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(CONFIG_SAMV7_MCAN0_RXFIFO0_SIZE * ((MCAN0_RXFIFO0_ELEMENT_SIZE/4) + 2))
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/* MCAN0 RX FIFO1 element size */
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# if defined(CONFIG_SAMV7_MCAN0_RXFIFO1_8BYTES)
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@ -196,6 +211,26 @@
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# error Undefined MCAN0 RX FIFO1 element size
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# endif
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# if CONFIG_SAMV7_MCAN0_RXFIFO1_SIZE > 64
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# error Invalid MCAN0 number of RX FIFO1 elements
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# endif
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# define MCAN0_RXFIFO1_WORDS \
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(CONFIG_SAMV7_MCAN0_RXFIFO1_SIZE * ((MCAN1_RXFIFO1_ELEMENT_SIZE/4) + 2))
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/* MCAN0 Filters */
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# if (CONFIG_SAMV7_MCAN0_NSTDFILTERS > 128)
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# error Invalid MCAN0 number of Standard Filters
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# endif
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# if (CONFIG_SAMV7_MCAN0_NEXTFILTERS > 64)
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# error Invalid MCAN0 number of Extended Filters
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# endif
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#define MCAN0_STDFILTER_WORDS CONFIG_SAMV7_MCAN0_NSTDFILTERS
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#define MCAN0_EXTFILTER_WORDS (CONFIG_SAMV7_MCAN0_NEXTFILTERS * 2)
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/* MCAN0 RX buffer element size */
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# if defined(CONFIG_SAMV7_MCAN0_RXBUFFER_8BYTES)
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@ -226,6 +261,14 @@
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# error Undefined MCAN0 RX buffer element size
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# endif
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# if (CONFIG_SAMV7_MCAN0_DEDICATED_RXBUFFER_SIZE > 64)
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# error Invalid MCAN0 number of RX BUFFER elements
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# endif
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# define MCAN0_DEDICATED_RXBUFFER_WORDS \
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(CONFIG_SAMV7_MCAN0_DEDICATED_RXBUFFER_SIZE * \
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((MCAN0_RXBUFFER_ELEMENT_SIZE/4) + 2))
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/* MCAN0 TX buffer element size */
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# if defined(CONFIG_SAMV7_MCAN0_TXBUFFER_8BYTES)
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@ -255,39 +298,67 @@
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# else
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# error Undefined MCAN0 TX buffer element size
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# endif
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# if ((CONFIG_SAMV7_MCAN0_DEDICATED_TXBUFFER_SIZE + \
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CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE) > 32)
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# error Invalid MCAN0 number of TX BUFFER elements
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# endif
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# define MCAN0_DEDICATED_TXBUFFER_WORDS \
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(CONFIG_SAMV7_MCAN0_DEDICATED_TXBUFFER_SIZE * \
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((MCAN0_TXBUFFER_ELEMENT_SIZE/4) + 2))
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/* MCAN0 TX FIFOs */
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# define MCAN0_TXEVENTFIFO_WORDS (CONFIG_SAMV7_MCAN0_TXEVENTFIFO_SIZE * 2)
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# define MCAN0_TXFIFIOQ_WORDS \
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(CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE * ((MCAN0_TXBUFFER_ELEMENT_SIZE/4) + 2))
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# if CONFIG_SAMV7_MCAN0_TXEVENTFIFO_SIZE > 32
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# error Invalid MCAN0 number of TX EVENT FIFO elements
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# endif
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#endif /* CONFIG_SAMV7_MCAN0 */
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/* MCAN1 Configuration ******************************************************/
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#ifdef CONFIG_SAMV7_MCAN1
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# if (CONFIG_SAMV7_MCAN1_NSTDFILTERS > 128)
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# error Invalid MCAN1 number of Standard Filters
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/* Bit timing */
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# define MCAN1_TSEG1 (CONFIG_SAMV7_MCAN1_PROPSEG + CONFIG_SAMV7_MCAN1_PHASESEG1)
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# define MCAN1_TSEG2 CONFIG_SAMV7_MCAN1_PHASESEG2
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# define MCAN1_BRP ((uint32_t)(((float) SAMV7_MCANCLK_FREQUENCY / \
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((float)(MCAN1_TSEG1 + MCAN1_TSEG2 + 3) * \
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(float)CONFIG_SAMV7_MCAN1_BITRATE)) - 1))
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# define MCAN1_SJW (CONFIG_SAMV7_MCAN1_FSJW - 1)
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# if MCAN1_TSEG1 > 63
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# error Invalid MCAN1 TSEG1
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# endif
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# if MCAN1_TSEG2 > 15
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# error Invalid MCAN1 TSEG2
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# endif
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# if MCAN1_SJW > 15
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# error Invalid MCAN1 SJW
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# endif
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# if (CONFIG_SAMV7_MCAN1_NEXTFILTERS > 64)
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# error Invalid MCAN1 number of Extended Filters
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# endif
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# define MCAN1_FTSEG1 (CONFIG_SAMV7_MCAN1_FPROPSEG + CONFIG_SAMV7_MCAN1_FPHASESEG1)
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# define MCAN1_FTSEG2 (CONFIG_SAMV7_MCAN1_FPHASESEG2)
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# define MCAN1_FBRP ((uint32_t)(((float) SAMV7_MCANCLK_FREQUENCY / \
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((float)(MCAN1_FTSEG1 + MCAN1_FTSEG2 + 3) * \
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(float)CONFIG_SAMV7_MCAN1_FBITRATE)) - 1))
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# define MCAN1_FSJW (CONFIG_SAMV7_MCAN1_FFSJW - 1)
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# if (CONFIG_SAMV7_MCAN1_RXFIFO0_SIZE > 64)
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# error Invalid MCAN1 number of RX FIFO 0 elements
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# endif
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# if (CONFIG_SAMV7_MCAN1_RXFIFO1_SIZE > 64)
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# error Invalid MCAN1 number of RX FIFO 0 elements
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# endif
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# if (CONFIG_SAMV7_MCAN1_DEDICATED_RXBUFFER_SIZE > 64)
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# error Invalid MCAN1 number of RX BUFFER elements
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# endif
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# if (CONFIG_SAMV7_MCAN1_TXEVENTFIFO_SIZE > 32)
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# error Invalid MCAN1 number of TX EVENT FIFO elements
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# endif
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# if ((CONFIG_SAMV7_MCAN1_DEDICATED_TXBUFFER_SIZE + \
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CONFIG_SAMV7_MCAN1_DEDICATED_TXFIFOQ_SIZE) > 32)
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# error Invalid MCAN1 number of TX BUFFER elements
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# endif
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#if MCAN1_FTSEG1 > 15
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# error Invalid MCAN1 FTSEG1
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#endif
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#if MCAN1_FTSEG2 > 7
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# error Invalid MCAN1 FTSEG2
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#endif
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#if MCAN1_FSJW > 3
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# error Invalid MCAN1 FSJW
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#endif
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/* MCAN1 RX FIFO0 element size */
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@ -319,6 +390,13 @@
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# error Undefined MCAN1 RX FIFO0 element size
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# endif
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# if CONFIG_SAMV7_MCAN1_RXFIFO0_SIZE > 64
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# error Invalid MCAN1 number of RX FIFO 0 elements
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# endif
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# define MCAN1_RXFIFO0_WORDS \
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(CONFIG_SAMV7_MCAN1_RXFIFO0_SIZE * ((MCAN1_RXFIFO0_ELEMENT_SIZE/4) + 2))
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/* MCAN1 RX FIFO1 element size */
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# if defined(CONFIG_SAMV7_MCAN1_RXFIFO1_8BYTES)
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@ -349,6 +427,26 @@
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# error Undefined MCAN1 RX FIFO1 element size
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# endif
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# if CONFIG_SAMV7_MCAN1_RXFIFO1_SIZE > 64)
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# error Invalid MCAN1 number of RX FIFO 0 elements
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# endif
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# define MCAN1_RXFIFO1_WORDS \
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(CONFIG_SAMV7_MCAN1_RXFIFO1_SIZE * ((MCAN1_RXFIFO1_ELEMENT_SIZE/4) + 2))
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/* MCAN1 Filters */
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# if CONFIG_SAMV7_MCAN1_NSTDFILTERS > 128
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# error Invalid MCAN1 number of Standard Filters
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# endif
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# if CONFIG_SAMV7_MCAN1_NEXTFILTERS > 64
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# error Invalid MCAN1 number of Extended Filters
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# endif
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# define MCAN1_STDFILTER_WORDS CONFIG_SAMV7_MCAN1_NSTDFILTERS
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# define MCAN1_EXTFILTER_WORDS (CONFIG_SAMV7_MCAN1_NEXTFILTERS * 2)
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/* MCAN1 RX buffer element size */
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# if defined(CONFIG_SAMV7_MCAN1_RXBUFFER_8BYTES)
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@ -379,6 +477,14 @@
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# error Undefined MCAN1 RX buffer element size
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# endif
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# if CONFIG_SAMV7_MCAN1_DEDICATED_RXBUFFER_SIZE > 64
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# error Invalid MCAN1 number of RX BUFFER elements
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# endif
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# define MCAN1_DEDICATED_RXBUFFER_WORDS \
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(CONFIG_SAMV7_MCAN1_DEDICATED_RXBUFFER_SIZE * \
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((MCAN1_RXBUFFER_ELEMENT_SIZE/4) + 2))
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/* MCAN1 TX buffer element size */
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# if defined(CONFIG_SAMV7_MCAN1_TXBUFFER_8BYTES)
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@ -408,6 +514,26 @@
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# else
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# error Undefined MCAN1 TX buffer element size
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# endif
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# if ((CONFIG_SAMV7_MCAN1_DEDICATED_TXBUFFER_SIZE + \
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CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE) > 32)
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# error Invalid MCAN1 number of TX BUFFER elements
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# endif
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# define MCAN1_DEDICATED_TXBUFFER_WORDS \
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(CONFIG_SAMV7_MCAN1_DEDICATED_TXBUFFER_SIZE * \
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((MCAN1_TXBUFFER_ELEMENT_SIZE/4) + 2))
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/* MCAN1 TX FIFOs */
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# if CONFIG_SAMV7_MCAN1_TXEVENTFIFO_SIZE > 32
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# error Invalid MCAN1 number of TX EVENT FIFO elements
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# endif
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# define MCAN1_TXEVENTFIFO_WORDS (CONFIG_SAMV7_MCAN1_TXEVENTFIFO_SIZE * 2)
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# define MCAN1_TXFIFIOQ_WORDS \
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(CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE * ((MCAN0_TXBUFFER_ELEMENT_SIZE/4) + 2))
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#endif /* CONFIG_SAMV7_MCAN1 */
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/* Mailboxes ****************************************************************/
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@ -486,14 +612,31 @@ struct sam_filter_s
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struct sam_config_s
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{
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uint8_t port; /* CAN port number (1 or 2) */
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uint8_t pid; /* CAN periperal ID/IRQ number */
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uint8_t nrecvmb; /* Number of receive mailboxes */
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xcpt_t handler; /* CAN interrupt handler */
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uintptr_t base; /* Base address of the CAN control registers */
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uint32_t baud; /* Configured baud */
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pio_pinset_t rxpinset; /* RX pin configuration */
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pio_pinset_t txpinset; /* TX pin configuration */
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xcpt_t handler; /* MCAN interrupt handler */
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uintptr_t base; /* Base address of the CAN control registers */
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uint32_t baud; /* Configured baud */
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uint32_t btp; /* Bit timing/prescaler register setting */
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uint32_t fbtp; /* Fast bit timing/prescaler register setting */
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uint8_t port; /* CAN port number (1 or 2) */
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uint8_t pid; /* CAN peripheral ID/IRQ number */
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uint8_t nstdfilters; /* Number of standard filters (up to 128) */
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uint8_t nextfilters; /* Number of extended filters (up to 64) */
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uint8_t nfifo0; /* Number of FIFO0 elements (up to 64) */
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uint8_t nfifo1; /* Number of FIFO1 elements (up to 64) */
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uint8_t nrxdedicated; /* Number of dedicated RX buffers (up to 64) */
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uint8_t ntxeventfifo; /* Number of TXevent FIFO elements (up to 32) */
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uint8_t ntxdedicated; /* Number of dedicated TX buffers (up to 64) */
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uint8_t ntxfifoq; /* Number of TX FIFO queue elements (up to 32) */
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uint8_t rxfifo0ecode; /* Encoded RX FIFO0 element size */
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uint8_t rxfifo0esize; /* RX FIFO0 element size */
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uint8_t rxfifo1ecode; /* Encoded RX FIFO1 element size */
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uint8_t rxfifo1esize; /* RX FIFO1 element size */
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uint8_t rxbufferecode; /* Encoded RX buffer element size */
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uint8_t rxbufferesize; /* RX buffer element size */
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uint8_t txbufferecode; /* Encoded TX buffer element size */
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uint8_t txbufferesize; /* TX buffer element size */
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/* Mailbox filters */
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@ -601,32 +744,34 @@ static const struct can_ops_s g_mcanops =
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#ifdef CONFIG_SAMV7_MCAN0
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static const struct sam_config_s g_mcan0const =
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{
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.port = 0,
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.pid = SAM_PID_CAN0,
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.nrecvmb = CONFIG_SAMV7_MCAN0_NRECVMB,
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.handler = mcan0_interrupt,
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.base = SAM_CAN0_VBASE,
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.baud = CONFIG_SAMV7_MCAN0_BITRATE,
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.rxpinset = PIO_CAN0_RX,
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.txpinset = PIO_CAN0_TX,
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.filter =
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{
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{
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.addr = CONFIG_SAMV7_MCAN0_ADDR0,
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.mask = CONFIG_SAMV7_MCAN0_MASK0,
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},
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#if CONFIG_SAMV7_MCAN0_NRECVMB > 1
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{
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.addr = CONFIG_SAMV7_MCAN0_ADDR1,
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.mask = CONFIG_SAMV7_MCAN0_MASK1,
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},
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#if CONFIG_SAMV7_MCAN0_NRECVMB > 1
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{
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.addr = CONFIG_SAMV7_MCAN0_ADDR2,
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.mask = CONFIG_SAMV7_MCAN0_MASK2,
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},
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#endif
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#endif
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.nrecvmb = CONFIG_SAMV7_MCAN0_NRECVMB,
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.handler = mcan0_interrupt,
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.base = SAM_MCAN0_BASE,
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.baud = CONFIG_SAMV7_MCAN0_BITRATE,
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.btp = MCAN_BTP_BRP(MCAN0_BRP) | MCAN_BTP_TSEG1(MCAN0_TSEG1) |
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MCAN_BTP_TSEG2(MCAN0_TSEG2) | MCAN_BTP_SJW(MCAN0_SJW),
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.fbtp = MCAN_FBTP_FBRP(MCAN0_FBRP) | MCAN_FBTP_FTSEG1(MCAN0_FTSEG1) |
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MCAN_FBTP_FTSEG2(MCAN0_FTSEG2) | MCAN_FBTP_FSJW(MCAN0_FSJW),
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.port = 0,
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.pid = SAM_PID_MCAN00,
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.nstdfilters = CONFIG_SAMV7_MCAN0_NSTDFILTERS,
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.nextfitlers = CONFIG_SAMV7_MCAN0_NEXTFILTERS,
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.nfifo0 = CONFIG_SAMV7_MCAN0_RXFIFO0_SIZE,
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.nfifo1 = CONFIG_SAMV7_MCAN0_RXFIFO1_SIZE,
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.nrxdedicated = CONFIG_SAMV7_MCAN0_DEDICATED_RXBUFFER_SIZE,
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.ntxeventfifo = CONFIG_SAMV7_MCAN0_TXEVENTFIFO_SIZE,
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.ntxdedicated = CONFIG_SAMV7_MCAN0_DEDICATED_TXBUFFER_SIZE,
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.ntxfifoq = CONFIG_SAMV7_MCAN0_TXFIFOQ_SIZE,
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.rxfifo0ecode = MCAN0_RXFIFO0_ENCODED_SIZE,
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.rxfifo0esize = (MCAN0_RXFIFO0_ELEMENT_SIZE / 4) + 2,
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.rxfifo1ecode = MCAN0_RXFIFO1_ENCODED_SIZE,
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.rxfifo1esize = (MCAN0_RXFIFO1_ELEMENT_SIZE / 4) + 2,
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.rxbufferecode = MCAN0_RXBUFFER_ENCODED_SIZE,
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.rxbufferesize = (MCAN0_RXBUFFER_ELEMENT_SIZE / 4) + 2,
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.txbufferecode = MCAN0_TXBUFFER_ENCODED_SIZE,
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.txbufferesize = (MCAN0_TXBUFFER_ELEMENT_SIZE / 4) + 2,
|
||||
},
|
||||
};
|
||||
|
||||
@ -637,33 +782,34 @@ static struct can_dev_s g_mcan0dev;
|
||||
#ifdef CONFIG_SAMV7_MCAN1
|
||||
static const struct sam_config_s g_mcan1const =
|
||||
{
|
||||
.port = 1,
|
||||
.pid = SAM_PID_CAN1,
|
||||
.rxpinset = PIO_CAN1_RX,
|
||||
.txpinset = PIO_CAN1_TX,
|
||||
.nrecvmb = CONFIG_SAMV7_MCAN1_NRECVMB,
|
||||
.handler = mcan1_interrupt,
|
||||
.base = SAM_CAN1_VBASE,
|
||||
.baud = CONFIG_SAMV7_MCAN1_BITRATE,
|
||||
.rxpinset = PIO_CAN1_RX,
|
||||
.txpinset = PIO_CAN1_TX,
|
||||
.filter =
|
||||
{
|
||||
{
|
||||
.addr = CONFIG_SAMV7_MCAN1_ADDR0,
|
||||
.mask = CONFIG_SAMV7_MCAN1_MASK0,
|
||||
},
|
||||
#if CONFIG_SAMV7_MCAN1_NRECVMB > 1
|
||||
{
|
||||
.addr = CONFIG_SAMV7_MCAN1_ADDR1,
|
||||
.mask = CONFIG_SAMV7_MCAN1_MASK1,
|
||||
},
|
||||
#if CONFIG_SAMV7_MCAN1_NRECVMB > 1
|
||||
{
|
||||
.addr = CONFIG_SAMV7_MCAN1_ADDR2,
|
||||
.mask = CONFIG_SAMV7_MCAN1_MASK2,
|
||||
},
|
||||
#endif
|
||||
#endif
|
||||
},
|
||||
.btp = MCAN_BTP_BRP(MCAN1_BRP) | MCAN_BTP_TSEG1(MCAN1_TSEG1) |
|
||||
MCAN_BTP_TSEG2(MCAN1_TSEG2) | MCAN_BTP_SJW(MCAN1_SJW),
|
||||
.fbtp = MCAN_FBTP_FBRP(MCAN1_FBRP) | MCAN_FBTP_FTSEG1(MCAN1_FTSEG1) |
|
||||
MCAN_FBTP_FTSEG2(MCAN1_FTSEG2) | MCAN_FBTP_FSJW(MCAN1_FSJW),
|
||||
.port = 1,
|
||||
.pid = SAM_PID_MCAN10,
|
||||
.nstdfilters = CONFIG_SAMV7_MCAN1_NSTDFILTERS,
|
||||
.nextfitlers = CONFIG_SAMV7_MCAN1_NEXTFILTERS,
|
||||
.nfifo0 = CONFIG_SAMV7_MCAN1_RXFIFO0_SIZE,
|
||||
.nfifo1 = CONFIG_SAMV7_MCAN1_RXFIFO1_SIZE,
|
||||
.nrxdedicated = CONFIG_SAMV7_MCAN0_DEDICATED_RXBUFFER_SIZE,
|
||||
.ntxeventfifo = CONFIG_SAMV7_MCAN1_TXEVENTFIFO_SIZE,
|
||||
.ntxdedicated = CONFIG_SAMV7_MCAN1_DEDICATED_TXBUFFER_SIZE,
|
||||
.ntxfifoq = CONFIG_SAMV7_MCAN1_TXFIFOQ_SIZE,
|
||||
.rxfifo0ecode = MCAN1_RXFIFO0_ENCODED_SIZE,
|
||||
.rxfifo0esize = (MCAN1_RXFIFO0_ELEMENT_SIZE / 4) + 2,
|
||||
.rxfifo1ecode = MCAN1_RXFIFO1_ENCODED_SIZE,
|
||||
.rxfifo1esize = (MCAN1_RXFIFO1_ELEMENT_SIZE / 4) + 2,
|
||||
.rxbufferecode = MCAN1_RXBUFFER_ENCODED_SIZE,
|
||||
.rxbufferesize = (MCAN1_RXBUFFER_ELEMENT_SIZE / 4) + 2,
|
||||
.txbufferecode = MCAN1_TXBUFFER_ENCODED_SIZE,
|
||||
.txbufferesize = (MCAN0_TXBUFFER_ELEMENT_SIZE / 4) + 2,
|
||||
};
|
||||
|
||||
static struct sam_mcan_s g_mcan1priv;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user