arch/stm32: Fix nxstyle errors
arch/arm/src/stm32/hardware/stm32_adc.h:
* Fix nxstyle errors.
arch/arm/src/stm32/hardware/stm32_adc_v2.h:
* Fix nxstyle errors.
This commit is contained in:
Nathan Hartman
Xiang Xiao
parent
bd79eaa5a6
commit
350a8b31a8
@ -1,4 +1,4 @@
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/****************************************************************************************************
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/****************************************************************************
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* arch/arm/src/stm32/hardware/stm32_adc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -31,14 +31,14 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_H
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/****************************************************************************************************
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/****************************************************************************
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* Included Files
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****************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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@ -56,7 +56,8 @@
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* which differs too much to keep it in the same file as ADC IPv1.
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*/
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#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(CONFIG_STM32_HAVE_IP_ADC_V2)
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#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && \
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defined(CONFIG_STM32_HAVE_IP_ADC_V2)
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# error Only one STM32 ADC IP version must be selected
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#endif
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@ -1,4 +1,4 @@
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/****************************************************************************************************
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/****************************************************************************
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* arch/arm/src/stm32/hardware/stm32_adc_v2.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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@ -32,26 +32,28 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H
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/****************************************************************************************************
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/****************************************************************************
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* Included Files
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****************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/****************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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****************************************************************************/
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/* Configuration ************************************************************************************/
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/* Configuration ************************************************************/
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/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), G4, H7, L0, L4, L4+ */
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/* This is implementation for STM32 ADC IPv2 - F0, F3 (without F37x), G4,
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* H7, L0, L4, L4+
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*/
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#define HAVE_IP_ADC_V2
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#undef HAVE_IP_ADC_V1 /* No ADC IPv1 */
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@ -84,7 +86,7 @@
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# define HAVE_ADC_CFGR2
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#endif
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/* Base addresses ***********************************************************************************/
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/* Base addresses ***********************************************************/
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#define STM32_ADC1_OFFSET 0x0000
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#define STM32_ADC2_OFFSET 0x0100
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@ -99,7 +101,7 @@
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#define STM32_ADC12CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC12_BASE) /* ADC1, ADC2 common */
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#define STM32_ADC34CMN_BASE (STM32_ADCCMN_OFFSET + STM32_ADC34_BASE) /* ADC3, ADC4 common */
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/* Register Offsets *********************************************************************************/
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/* Register Offsets *********************************************************/
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#define STM32_ADC_ISR_OFFSET 0x0000 /* ADC interrupt and status register */
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#define STM32_ADC_IER_OFFSET 0x0004 /* ADC interrupt enable register */
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@ -138,7 +140,7 @@
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#define STM32_ADC_CCR_OFFSET 0x0008 /* Common control register */
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#define STM32_ADC_CDR_OFFSET 0x000c /* Common regular data register for dual mode */
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/* Register Addresses *******************************************************************************/
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/* Register Addresses *******************************************************/
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#if STM32_NADC > 0
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# define STM32_ADC1_ISR (STM32_ADC1_BASE + STM32_ADC_ISR_OFFSET)
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@ -284,9 +286,11 @@
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# define STM32_ADC34_CDR (STM32_ADC34CMN_BASE + STM32_ADC_CDR_OFFSET)
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#endif
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/* Register Bitfield Definitions ********************************************************************/
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/* Register Bitfield Definitions ********************************************/
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/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
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/* ADC interrupt and status register (ISR), and
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* ADC interrupt enable register (IER)
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*/
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#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
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#define ADC_INT_EOSMP (1 << 1) /* Bit 1: End of sampling flag */
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@ -860,16 +864,16 @@
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#define ADC_CDR_RDATA_SLV_SHIFT (16) /* Bits 16-31: Regular data of the slave ADC */
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#define ADC_CDR_RDATA_SLV_MASK (0xffff << ADC_CDR_RDATA_SLV_SHIFT)
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/****************************************************************************************************
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/****************************************************************************
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* Public Types
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****************************************************************************************************/
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****************************************************************************/
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/****************************************************************************************************
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/****************************************************************************
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* Public Data
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****************************************************************************************************/
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****************************************************************************/
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/****************************************************************************************************
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************************************/
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_ADC_V2_H */
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