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SAMV7 XDMAC: Don't sample interrupt status registers in debug mode. This can cause loss of interrupts

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This commit is contained in:
Gregory Nutt 2015-11-07 11:25:20 -06:00
parent dd69967934
commit 352d2a1d02
3 changed files with 13 additions and 12 deletions
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5
arch/arm/src/samv7/sam_qspi.c
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@ -129,10 +129,7 @@
#define MEMORY_SYNC() do { ARM_DSB(); ARM_ISB(); } while (0)
/* The SAMV7x QSPI driver insists that transfers be performed in multiples
* of 32-bits.
*
* REVISIT: Why is this done? This logic is here only because it is also
* done this way in the Atmel sample code. But I have no idea why.
* of 32-bits. The alignment requirement only applies to RX DMA data.
*/
#define ALIGN_SHIFT 2

4
arch/arm/src/samv7/sam_xdmac.c
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@ -2037,7 +2037,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
regs->gcfg = sam_getdmac(xdmac, SAM_XDMAC_GCFG_OFFSET);
regs->gwac = sam_getdmac(xdmac, SAM_XDMAC_GWAC_OFFSET);
regs->gim = sam_getdmac(xdmac, SAM_XDMAC_GIM_OFFSET);
regs->gis = sam_getdmac(xdmac, SAM_XDMAC_GIS_OFFSET);
regs->gs = sam_getdmac(xdmac, SAM_XDMAC_GS_OFFSET);
regs->grs = sam_getdmac(xdmac, SAM_XDMAC_GRS_OFFSET);
regs->gws = sam_getdmac(xdmac, SAM_XDMAC_GWS_OFFSET);
@ -2046,7 +2045,6 @@ void sam_dmasample(DMA_HANDLE handle, struct sam_dmaregs_s *regs)
/* Sample channel registers */
regs->cim = sam_getdmach(xdmach, SAM_XDMACH_CIM_OFFSET);
regs->cis = sam_getdmach(xdmach, SAM_XDMACH_CIS_OFFSET);
regs->csa = sam_getdmach(xdmach, SAM_XDMACH_CSA_OFFSET);
regs->cda = sam_getdmach(xdmach, SAM_XDMACH_CDA_OFFSET);
regs->cnda = sam_getdmach(xdmach, SAM_XDMACH_CNDA_OFFSET);
@ -2085,14 +2083,12 @@ void sam_dmadump(DMA_HANDLE handle, const struct sam_dmaregs_s *regs,
dmadbg(" GCFG[%08x]: %08x\n", SAM_XDMAC_GCFG, regs->gcfg);
dmadbg(" GWAC[%08x]: %08x\n", SAM_XDMAC_GWAC, regs->gwac);
dmadbg(" GIM[%08x]: %08x\n", SAM_XDMAC_GIM, regs->gim);
dmadbg(" GIS[%08x]: %08x\n", SAM_XDMAC_GIS, regs->gis);
dmadbg(" GS[%08x]: %08x\n", SAM_XDMAC_GS, regs->gs);
dmadbg(" GRS[%08x]: %08x\n", SAM_XDMAC_GRS, regs->grs);
dmadbg(" GWS[%08x]: %08x\n", SAM_XDMAC_GWS, regs->gws);
dmadbg(" GSWS[%08x]: %08x\n", SAM_XDMAC_GSWS, regs->gsws);
dmadbg(" DMA Channel Registers:\n");
dmadbg(" CIM[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIM_OFFSET, regs->cim);
dmadbg(" CIS[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CIS_OFFSET, regs->cis);
dmadbg(" CSA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CSA_OFFSET, regs->csa);
dmadbg(" CDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CDA_OFFSET, regs->cda);
dmadbg(" CNDA[%08x]: %08x\n", xdmach->base + SAM_XDMACH_CNDA_OFFSET, regs->cnda);

16
arch/arm/src/samv7/sam_xdmac.h
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@ -175,22 +175,30 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, void *arg, int result);
#ifdef CONFIG_DEBUG_DMA
struct sam_dmaregs_s
{
/* Global Registers */
/* Global Registers.
*
* This includes all readable global XDMAC registers except for the global
* interrupt status register (XDMAC_GIS). Reading from the status
* register could cause loss of interrupts.
*/
uint32_t gtype; /* Global Type Register */
uint32_t gcfg; /* Global Configuration Register */
uint32_t gwac; /* Global Weighted Arbiter Configuration Register */
uint32_t gim; /* Global Interrupt Mask Register */
uint32_t gis; /* Global Interrupt Status Register */
uint32_t gs; /* Global Channel Status Register */
uint32_t grs; /* Global Channel Read Suspend Register */
uint32_t gws; /* Global Channel Write Suspend Register */
uint32_t gsws; /* Global Channel Software Request Status Register */
/* Channel Registers */
/* Channel Registers
*
* This includes all readable XDMAC channel registers except for the
* channel interrupt status register (XDMAC_CIS). Reading from the status
* register could cause loss of interrupts.
*/
uint32_t cim; /* Channel Interrupt Mask Register */
uint32_t cis; /* Channel Interrupt Status Register */
uint32_t csa; /* Channel Source Address Register */
uint32_t cda; /* Channel Destination Address Register */
uint32_t cnda; /* Channel Next Descriptor Address Register */