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SAM3/4 and SAMV7 UART: The IMR register is read-only. This means that sam_restoreints() does not actually re-enable UART interrupts.

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This commit is contained in:
Gregory Nutt 2015-04-08 15:04:10 -06:00
parent 9e1a7113f7
commit 35312b31f9
4 changed files with 2 additions and 6 deletions
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2
arch/arm/src/sam34/sam_lowputc.c
View File

@ -299,8 +299,6 @@ void up_lowputc(char ch)
/* Send the character */
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
irqrestore(flags);
return;
}
irqrestore(flags);

2
arch/arm/src/sam34/sam_serial.c
View File

@ -652,7 +652,7 @@ static inline void up_restoreusartint(struct up_dev_s *priv, uint32_t imr)
{
/* Restore the previous interrupt state */
up_serialout(priv, SAM_UART_IMR_OFFSET, imr);
up_serialout(priv, SAM_UART_IER_OFFSET, imr);
}
/****************************************************************************

2
arch/arm/src/samv7/sam_lowputc.c
View File

@ -226,8 +226,6 @@ void up_lowputc(char ch)
/* Send the character */
putreg32((uint32_t)ch, SAM_CONSOLE_BASE + SAM_UART_THR_OFFSET);
irqrestore(flags);
return;
}
irqrestore(flags);

2
arch/arm/src/samv7/sam_serial.c
View File

@ -712,7 +712,7 @@ static inline void sam_restoreusartint(struct sam_dev_s *priv, uint32_t imr)
{
/* Restore the previous interrupt state */
sam_serialout(priv, SAM_UART_IMR_OFFSET, imr);
sam_serialout(priv, SAM_UART_IER_OFFSET, imr);
}
/****************************************************************************