diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1516a63f7d..521d900b51 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -265,6 +265,7 @@ config ARCH_CORTEXM4 config ARCH_CORTEXM7 bool default n + select ARCH_HAVE_FPU select ARCH_HAVE_IRQPRIO select ARCH_HAVE_RAMVECTORS select ARCH_HAVE_HIPRI_INTERRUPT diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h index 3b65e77a23..fada7f2d25 100644 --- a/arch/arm/include/stm32f7/chip.h +++ b/arch/arm/include/stm32f7/chip.h @@ -73,7 +73,7 @@ * Parts STM32F74xxG have 1024Kb of FLASH */ -#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || +#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \ defined(CONFIG_ARCH_CHIP_STM32F756) #if defined(CONFIG_ARCH_CHIP_STM32F745) @@ -123,7 +123,7 @@ # define STM32F7_NUSBOTGHS 1 /* USB OTG HS */ # define STM32F7_NCAN 2 /* CAN1-2 */ # define STM32F7_NSAI 2 /* SAI1-2 */ -# define STM32F7_NSPDFRX 4 /* 4 SPDFRX inputs */ +# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */ # define STM32F7_NSDMMC 1 /* SDMMC interface */ # define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */ # define STM32F7_NDMA 2 /* DMA1-2 */ diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index f72f3c094c..8aff039876 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -2,3 +2,397 @@ # For a description of the syntax of this configuration file, # see the file kconfig-language.txt in the NuttX tools repository. # + +if ARCH_CHIP_STM32F7 + +comment "STM32 F7 Configuration Options" + +choice + prompt "STM32 F7 Chip Selection" + default ARCH_CHIP_STM32F746 + depends on ARCH_CHIP_STM32F7 + +config ARCH_CHIP_STM32F745 + bool "STM32F745xx" + select STM32F7_STM32F74xx + ---help--- + STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + +config ARCH_CHIP_STM32F746 + bool "STM32F746xx" + select STM32F7_STM32F74xx + select STM32F7_HAVE_LTDC + ---help--- + STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + +config ARCH_CHIP_STM32F756 + bool "STM32F756xx" + select STM32F7_STM32F75xx + select STM32F7_HAVE_LTDC + ---help--- + STM32 F7 Cortex M7, 512 or 1024Kb FLASH, 335 (240++16+54) Kb SRAM + +endchoice # STM32 F7 Chip Selection + +config STM32F7_STM32F74xx + bool + default n + +config STM32F7_STM32F75xx + bool + default n + +menu "STM32 Peripheral Support" + +# These "hidden" settings determine is a peripheral option is available for the +# selection MCU + +config STM32F7_HAVE_LTDC + bool + default n + +# These "hidden" settings are the OR of individual peripheral selections +# indicating that the general capabilitiy is required. + +config STM32F7_ADC + bool + default n + +config STM32F7_CAN + bool + default n + +config STM32F7_DAC + bool + default n + +config STM32F7_I2C + bool + default n + +config STM32F7_SAI + bool + default n + +config STM32F7_SPI + bool + default n + +config STM32F7_USART + bool + default n + +# These are the peripheral selections proper + +config STM32F7_ADC1 + bool "ADC1" + default n + select STM32F7_ADC + +config STM32F7_ADC2 + bool "ADC2" + default n + select STM32F7_ADC + +config STM32F7_ADC3 + bool "ADC3" + default n + select STM32F7_ADC + +config STM32F7_BKPSRAM + bool "Enable BKP RAM Domain" + default n + +config STM32F7_CAN1 + bool "CAN1" + default n + select CAN + select STM32F7_CAN + +config STM32F7_CAN2 + bool "CAN2" + default n + select CAN + select STM32F7_CAN + +config STM32F7_CEC + bool "CEC" + default n + depends on STM32F7_VALUELINE + +config STM32F7_CRC + bool "CRC" + default n + +config STM32F7_CRYP + bool "CRYP" + default n + +config STM32F7_DMA1 + bool "DMA1" + default n + select ARCH_DMA + +config STM32F7_DMA2 + bool "DMA2" + default n + select ARCH_DMA + +config STM32F7_DAC1 + bool "DAC1" + default n + select STM32F7_DAC + +config STM32F7_DAC2 + bool "DAC2" + default n + select STM32F7_DAC + +config STM32F7_DCMI + bool "DCMI" + default n + +config STM32F7_ETHMAC + bool "Ethernet MAC" + default n + select NETDEVICES + select ARCH_HAVE_PHY + +config STM32F7_FSMC + bool "FSMC" + default n + +config STM32F7_I2C1 + bool "I2C1" + default n + select STM32F7_I2C + +config STM32F7_I2C2 + bool "I2C2" + default n + select STM32F7_I2C + +config STM32F7_I2C3 + bool "I2C3" + default n + select STM32F7_I2C + +config STM32F7_LTDC + bool "LTDC" + default n + depends on STM32F7_HAVE_LTDC + ---help--- + The STM32 LTDC is an LCD-TFT Display Controller available on + the STM32F429 and STM32F439 devices. It is a standard parallel + video interface (HSYNC, VSYNC, etc.) for controlling TFT + LCD displays. + +config STM32F7_DMA2D + bool "DMA2D" + default n + ---help--- + The STM32 DMA2D is an Chrom-Art Accelerator for image manipulation + available on the STM32 F7 devices. + +config STM32F7_OTGFS + bool "OTG FS" + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32F7_OTGHS + bool "OTG HS" + default n + select USBHOST_HAVE_ASYNCH if USBHOST + +config STM32F7_PWR + bool "PWR" + default n + +config STM32F7_RNG + bool "RNG" + default n + select ARCH_HAVE_RNG + +config STM32F7_SAI1 + bool "SAI1" + default n + select STM32F7_SAI + +config STM32F7_SAI2 + bool "SAI2" + default n + select STM32F7_SAI + +config STM32F7_SDMMC1 + bool "SDMMC1" + default n + select ARCH_HAVE_SDIO + +config STM32F7_SPDIFRX + bool "SPDIFRX" + default n + +config STM32F7_SPI1 + bool "SPI1" + default n + select SPI + select STM32F7_SPI + +config STM32F7_SPI2 + bool "SPI2" + default n + select SPI + select STM32F7_SPI + +config STM32F7_SPI3 + bool "SPI3" + default n + select SPI + select STM32F7_SPI + +config STM32F7_SPI4 + bool "SPI4" + default n + select SPI + select STM32F7_SPI + +config STM32F7_SPI5 + bool "SPI5" + default n + select SPI + select STM32F7_SPI + +config STM32F7_SPI6 + bool "SPI6" + default n + select SPI + select STM32F7_SPI + +config STM32F7_TIM1 + bool "TIM1" + default n + +config STM32F7_TIM2 + bool "TIM2" + default n + +config STM32F7_TIM3 + bool "TIM3" + default n + +config STM32F7_TIM4 + bool "TIM4" + default n + +config STM32F7_TIM5 + bool "TIM5" + default n + +config STM32F7_TIM6 + bool "TIM6" + default n + +config STM32F7_TIM7 + bool "TIM7" + default n + +config STM32F7_TIM8 + bool "TIM8" + default n + +config STM32F7_TIM9 + bool "TIM9" + default n + +config STM32F7_TIM10 + bool "TIM10" + default n + +config STM32F7_TIM11 + bool "TIM11" + default n + +config STM32F7_TIM12 + bool "TIM12" + default n + +config STM32F7_TIM13 + bool "TIM13" + default n + +config STM32F7_TIM14 + bool "TIM14" + default n + +config STM32F7_TIM15 + bool "TIM15" + default n + +config STM32F7_USART1 + bool "USART1" + default n + select ARCH_HAVE_USART1 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F7_USART + +config STM32F7_USART2 + bool "USART2" + default n + select ARCH_HAVE_USART2 + select ARCH_HAVE_SERIAL_TERMIOS + select STM32F7_USART + +config STM32F7_USART3 + bool "USART3" + default n + select ARCH_HAVE_SERIAL_TERMIOS + select ARCH_HAVE_USART3 + select STM32F7_USART + +config STM32F7_UART4 + bool "UART4" + default n + select ARCH_HAVE_SERIAL_TERMIOS + select ARCH_HAVE_UART4 + select STM32F7_USART + +config STM32F7_UART5 + bool "UART5" + default n + select ARCH_HAVE_SERIAL_TERMIOS + select ARCH_HAVE_UART5 + select STM32F7_USART + +config STM32F7_USART6 + bool "USART6" + default n + select ARCH_HAVE_SERIAL_TERMIOS + select ARCH_HAVE_USART6 + select STM32F7_USART + +config STM32F7_UART7 + bool "UART7" + default n + select ARCH_HAVE_SERIAL_TERMIOS + select ARCH_HAVE_UART7 + select STM32F7_USART + +config STM32F7_UART8 + bool "UART8" + default n + select ARCH_HAVE_SERIAL_TERMIOS + select ARCH_HAVE_UART8 + select STM32F7_USART + +config STM32F7_IWDG + bool "IWDG" + default n + select WATCHDOG + +config STM32F7_WWDG + bool "WWDG" + default n + select WATCHDOG + +endmenu +endif # ARCH_CHIP_STM32F7