arch/arm/src/imxrt/chip/imxrt_lpspi.h: IMXRT1050 LPSPI register and bit definitions added.
This commit is contained in:
Ivan Ucherdzhiev
Gregory Nutt
parent
5a0733d0d6
commit
35fbaf7c4c
370
arch/arm/src/imxrt/chip/imxrt_lpspi.h
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arch/arm/src/imxrt/chip/imxrt_lpspi.h
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/********************************************************************************************
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* arch/arm/src/imxrt/imxrt_lpspi.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Pavlina Koleva <pavlinaikoleva19@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H
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#define __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/imxrt_memorymap.h"
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* Register offsets *************************************************************************/
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#define IMXRT_LPSPI_VERID_OFFSET 0x0000 /* Version ID Register offset */
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#define IMXRT_LPSPI_PARAM_OFFSET 0x0004 /* Parameter Register offset */
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#define IMXRT_LPSPI_CR_OFFSET 0x0010 /* Control Register offset */
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#define IMXRT_LPSPI_SR_OFFSET 0x0014 /* Status Register offset */
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#define IMXRT_LPSPI_IER_OFFSET 0x0018 /* Interrupt Enable Register offset */
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#define IMXRT_LPSPI_DER_OFFSET 0x001C /* DMA Enable Register offset */
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#define IMXRT_LPSPI_CFGR0_OFFSET 0x0020 /* Configuration Register 0 offset */
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#define IMXRT_LPSPI_CFGR1_OFFSET 0x0024 /* Configuration Register 1 offset */
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#define IMXRT_LPSPI_DMR0_OFFSET 0x0030 /* Data Match Register 0 offset */
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#define IMXRT_LPSPI_DMR1_OFFSET 0x0034 /* Data Match Register 1 offset */
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#define IMXRT_LPSPI_CCR_OFFSET 0x0040 /* Clock Configuration Register offset */
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#define IMXRT_LPSPI_FCR_OFFSET 0x0058 /* FIFO Control Register offset */
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#define IMXRT_LPSPI_FSR_OFFSET 0x005C /* FIFO Status Register offset */
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#define IMXRT_LPSPI_TCR_OFFSET 0x0060 /* Transmit Command Register offset */
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#define IMXRT_LPSPI_TDR_OFFSET 0x0064 /* Transmit Data Register offset */
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#define IMXRT_LPSPI_RSR_OFFSET 0x0070 /* Receive Status Register offset */
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#define IMXRT_LPSPI_RDR_OFFSET 0x0074 /* Receive Data Register offset */
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/* Register addresses ***********************************************************************/
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#define IMXRT_LPSPI1_VERID (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_VERID_OFFSET)
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#define IMXRT_LPSPI1_PARAM (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_PARAM_OFFSET)
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#define IMXRT_LPSPI1_CR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CR_OFFSET)
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#define IMXRT_LPSPI1_SR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_SR_OFFSET)
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#define IMXRT_LPSPI1_IER (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_IER_OFFSET)
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#define IMXRT_LPSPI1_DER (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DER_OFFSET)
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#define IMXRT_LPSPI1_CFGR0 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
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#define IMXRT_LPSPI1_CFGR1 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
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#define IMXRT_LPSPI1_DMR0 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DMR0_OFFSET)
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#define IMXRT_LPSPI1_DMR1 (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_DMR1_OFFSET)
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#define IMXRT_LPSPI1_CCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_CCR_OFFSET)
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#define IMXRT_LPSPI1_FCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_FCR_OFFSET)
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#define IMXRT_LPSPI1_FSR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_FSR_OFFSET)
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#define IMXRT_LPSPI1_TCR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_TCR_OFFSET)
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#define IMXRT_LPSPI1_TDR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_TDR_OFFSET)
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#define IMXRT_LPSPI1_RSR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_RSR_OFFSET)
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#define IMXRT_LPSPI1_RDR (IMXRT_LPSPI1_BASE + IMXRT_LPSPI_RDR_OFFSET)
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#define IMXRT_LPSPI2_VERID (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_VERID_OFFSET)
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#define IMXRT_LPSPI2_PARAM (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_PARAM_OFFSET)
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#define IMXRT_LPSPI2_CR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CR_OFFSET)
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#define IMXRT_LPSPI2_SR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_SR_OFFSET)
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#define IMXRT_LPSPI2_IER (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_IER_OFFSET)
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#define IMXRT_LPSPI2_DER (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DER_OFFSET)
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#define IMXRT_LPSPI2_CFGR0 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
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#define IMXRT_LPSPI2_CFGR1 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
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#define IMXRT_LPSPI2_DMR0 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DMR0_OFFSET)
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#define IMXRT_LPSPI2_DMR1 (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_DMR1_OFFSET)
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#define IMXRT_LPSPI2_CCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_CCR_OFFSET)
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#define IMXRT_LPSPI2_FCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_FCR_OFFSET)
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#define IMXRT_LPSPI2_FSR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_FSR_OFFSET)
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#define IMXRT_LPSPI2_TCR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_TCR_OFFSET)
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#define IMXRT_LPSPI2_TDR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_TDR_OFFSET)
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#define IMXRT_LPSPI2_RSR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_RSR_OFFSET)
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#define IMXRT_LPSPI2_RDR (IMXRT_LPSPI2_BASE + IMXRT_LPSPI_RDR_OFFSET)
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#define IMXRT_LPSPI3_VERID (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_VERID_OFFSET)
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#define IMXRT_LPSPI3_PARAM (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_PARAM_OFFSET)
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#define IMXRT_LPSPI3_CR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CR_OFFSET)
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#define IMXRT_LPSPI3_SR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_SR_OFFSET)
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#define IMXRT_LPSPI3_IER (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_IER_OFFSET)
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#define IMXRT_LPSPI3_DER (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DER_OFFSET)
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#define IMXRT_LPSPI3_CFGR0 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
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#define IMXRT_LPSPI3_CFGR1 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
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#define IMXRT_LPSPI3_DMR0 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DMR0_OFFSET)
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#define IMXRT_LPSPI3_DMR1 (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_DMR1_OFFSET)
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#define IMXRT_LPSPI3_CCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_CCR_OFFSET)
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#define IMXRT_LPSPI3_FCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_FCR_OFFSET)
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#define IMXRT_LPSPI3_FSR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_FSR_OFFSET)
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#define IMXRT_LPSPI3_TCR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_TCR_OFFSET)
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#define IMXRT_LPSPI3_TDR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_TDR_OFFSET)
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#define IMXRT_LPSPI3_RSR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_RSR_OFFSET)
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#define IMXRT_LPSPI3_RDR (IMXRT_LPSPI3_BASE + IMXRT_LPSPI_RDR_OFFSET)
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#define IMXRT_LPSPI4_VERID (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_VERID_OFFSET)
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#define IMXRT_LPSPI4_PARAM (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_PARAM_OFFSET)
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#define IMXRT_LPSPI4_CR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CR_OFFSET)
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#define IMXRT_LPSPI4_SR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_SR_OFFSET)
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#define IMXRT_LPSPI4_IER (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_IER_OFFSET)
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#define IMXRT_LPSPI4_DER (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DER_OFFSET)
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#define IMXRT_LPSPI4_CFGR0 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CFGR0_OFFSET)
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#define IMXRT_LPSPI4_CFGR1 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CFGR1_OFFSET)
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#define IMXRT_LPSPI4_DMR0 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DMR0_OFFSET)
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#define IMXRT_LPSPI4_DMR1 (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_DMR1_OFFSET)
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#define IMXRT_LPSPI4_CCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_CCR_OFFSET)
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#define IMXRT_LPSPI4_FCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_FCR_OFFSET)
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#define IMXRT_LPSPI4_FSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_FSR_OFFSET)
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#define IMXRT_LPSPI4_TCR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_TCR_OFFSET)
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#define IMXRT_LPSPI4_TDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_TDR_OFFSET)
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#define IMXRT_LPSPI4_RSR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RSR_OFFSET)
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#define IMXRT_LPSPI4_RDR (IMXRT_LPSPI4_BASE + IMXRT_LPSPI_RDR_OFFSET)
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/* Register bit definitions *****************************************************************/
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/* Version ID Register */
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#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number */
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#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT)
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#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number */
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#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT)
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#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number */
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#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT)
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/* Parameter Register */
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#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size */
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#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT)
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#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size */
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#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT)
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#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number */
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#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT)
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/* Bits 24-31: Reserved */
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/* Control Register */
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#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable */
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#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset */
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#define LPSPI_CR_DOZEN (1 << 2) /* Bit 2: Doze mode enable */
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# define LPSPI_CR_DOZEN_EN (0 << 2) /* Module is enabled in Doze mode */
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# define LPSPI_CR_DOZEN_DIS (1 << 2) /* Module is disabled in Doze mode */
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#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable */
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/* Bits 4-7: Reserved */
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#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO */
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#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO */
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/* Bits 10-31: Reserved */
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/* Status Register */
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#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag */
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#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag */
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/* Bits 2-7: Reserved */
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#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag */
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#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag */
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#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag */
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#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag */
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#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag */
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#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag */
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/* Bits 14-23: Reserved */
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#define LPSPI_SR_REF (1 << 24) /* Bit 24: Module Busy Flag*/
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/* Bits 25-31: Reserved */
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/* Interrupt Enable Register */
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#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable */
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#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable */
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/* Bits 2-7: Reserved */
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#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable */
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#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable */
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#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable */
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#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable */
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#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable */
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#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable */
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/* Bits 14-31: Reserved */
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/* DMA Enable Register */
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#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable */
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#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable */
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/* Bits 2-31: Reserved */
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/* Configuration Register 0 */
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#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable */
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#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity */
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# define LPSPI_CFGR0_HRPOL_LOW (0 << 1) /* Active low */
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# define LPSPI_CFGR0_HRPOL_HIGH (1 << 1) /* Active high */
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#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select */
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# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */
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# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */
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/* Bits 3-7: Reserved */
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#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bits 8: Circular FIFO Enable */
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#define LPSPI_CFGR0_RDMO (1 << 9) /* Bits 9: Receive Data Match Only */
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# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* RD stored in the receive FIFO as in normal operations */
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# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* RD discarded unless the Data Match Flag (DMF) is set */
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/* Bits 10-31: Reserved */
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/* Configuration Register 1 */
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#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode */
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#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point */
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# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */
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# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */
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#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS enabled */
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#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall enabled */
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/* Bits 4-7: Reserved */
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#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-11: Peripheral Chip Select Polarity */
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#define LPSPI_CFGR1_PCSPOL_MASK (0xf << LPSPI_CFGR1_PCSPOL_SHIFT)
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# define LPSPI_CFGR1_PCSPOL_LOW (0 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active low */
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# define LPSPI_CFGR1_PCSPOL_HIGH (1 << LPSPI_CFGR1_PCSPOL_SHIFT) /* The Peripheral Chip Select pin PCSx is active high */
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/* Bits 12-15: Reserved */
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#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration */
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#define LPSPI_CFGR1_MATCFG_MASK (7 << LPSPI_CFGR1_MATCFG_SHIFT)
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# define LPSPI_CFGR1_MATCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_MATCFG_SHIFT)
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/* Bits 19-23: Reserved */
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#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration */
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#define LPSPI_CFGR1_PINCFG_MASK (3 << LPSPI_CFGR1_PINCFG_SHIFT)
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# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */
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# define LPSPI_CFGR1_PINCFG_SIN_SIN (1 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */
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# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (2 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */
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# define LPSPI_CFGR1_PINCFG_SOUT_SIN (3 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */
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# define LPSPI_CFGR1_PINCFG(n) ((uint32_t)(n) << LPSPI_CFGR1_PINCFG_SHIFT)
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#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config */
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# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */
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# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */
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#define LPSPI_CFGR1_PCSCFG (1 << 27) /* Bit 27: Peripheral Chip Select Configuration */
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# define LPSPI_CFGR1_PCSCFG_EN (0 << 27) /* PCS[3:2] are enabled */
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# define LPSPI_CFGR1_PCSCFG_DIS (1 << 27) /* PCS[3:2] are disabled */
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/* Bits 28-31: Reserved */
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/* Data Match Register 0 */
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#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value */
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#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT)
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# define LPSPI_DMR0_MATCH0(n) ((uint32_t)(n) << LPSPI_DMR0_MATCH0_SHIFT)
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/* Data Match Register 0 */
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#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value */
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#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT)
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# define LPSPI_DMR1_MATCH1(n) ((uint32_t)(n) << LPSPI_DMR1_MATCH1_SHIFT)
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/* Clock Configuration Register */
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#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider */
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#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT)
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# define LPSPI_CCR_SCKDIV(n) ((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT)
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#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers */
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#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT)
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# define LPSPI_CCR_DBT(n) ((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT)
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#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay */
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#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT)
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# define LPSPI_CCR_PCSSCK(n) ((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT)
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#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay */
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#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT)
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# define LPSPI_CCR_SCKPCS(n) ((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT)
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/* FIFO Control Register */
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#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-3: Transmit FIFO Watermark */
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#define LPSPI_FCR_TXWATER_MASK (0xf << LPSPI_FCR_TXWATER_SHIFT)
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# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT)
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/* Bits 4-7: Reserved */
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/* Bits 8-15: Reserved */
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#define LPSPI_FCR_RXWATER_SHIFT (8) /* Bits 16-19: Receive FIFO Watermark */
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#define LPSPI_FCR_RXWATER_MASK (0xf << LPSPI_FCR_RXWATER_SHIFT)
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# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT)
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/* Bits 20-23: Reserved */
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/* Bits 24-31: Reserved */
|
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|
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/* FIFO Status Register */
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|
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#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-4: Transmit FIFO Count */
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#define LPSPI_FSR_TXCOUNT_MASK (0x1f << LPSPI_FSR_TXCOUNT_SHIFT)
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/* Bits 5-7: Reserved */
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/* Bits 8-15: Reserved */
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#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-20: Receive FIFO Count */
|
||||
#define LPSPI_FSR_RXCOUNT_MASK (0x1f << LPSPI_FSR_RXCOUNT_SHIFT)
|
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/* Bits 21-23: Reserved */
|
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/* Bits 24-31: Reserved */
|
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|
||||
/* Transmit Command Register */
|
||||
#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size */
|
||||
#define LPSPI_TCR_FRAMESZ_MASK (0xfff << LPSPI_TCR_FRAMESZ_SHIFT)
|
||||
# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT)
|
||||
/* Bits 12-15: Reserved */
|
||||
#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width */
|
||||
#define LPSPI_TCR_WIDTH_MASK (3 << LPSPI_TCR_WIDTH_SHIFT)
|
||||
# define LPSPI_TCR_WIDTH_1BIT (0 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */
|
||||
# define LPSPI_TCR_WIDTH_2BIT (1 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */
|
||||
# define LPSPI_TCR_WIDTH_4BIT (2 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */
|
||||
#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask */
|
||||
#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask */
|
||||
#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command */
|
||||
#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer */
|
||||
#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap */
|
||||
#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First */
|
||||
# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
|
||||
#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-25: Peripheral Chip Select */
|
||||
#define LPSPI_TCR_PCS_MASK (3 << LPSPI_TCR_PCS_SHIFT)
|
||||
# define LPSPI_TCR_PCS_0 (0 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[0] */
|
||||
# define LPSPI_TCR_PCS_1 (1 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[1] */
|
||||
# define LPSPI_TCR_PCS_2 (2 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[2] */
|
||||
# define LPSPI_TCR_PCS_3 (3 << LPSPI_TCR_PCS_SHIFT) /* Transfer using LPSPI_PCS[3] */
|
||||
/* Bit 26: Reserved */
|
||||
#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value */
|
||||
#define LPSPI_TCR_PRESCALE_MASK (7 << LPSPI_TCR_PRESCALE_SHIFT)
|
||||
# define LPSPI_TCR_PRESCALE_1 (0 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */
|
||||
# define LPSPI_TCR_PRESCALE_2 (1 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */
|
||||
# define LPSPI_TCR_PRESCALE_4 (2 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */
|
||||
# define LPSPI_TCR_PRESCALE_8 (3 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */
|
||||
# define LPSPI_TCR_PRESCALE_16 (4 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */
|
||||
# define LPSPI_TCR_PRESCALE_32 (5 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */
|
||||
# define LPSPI_TCR_PRESCALE_64 (6 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */
|
||||
# define LPSPI_TCR_PRESCALE_128 (7 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */
|
||||
# define LPSPI_TCR_PRESCALE(n) ((uint32_t)(n) << LPSPI_TCR_PRESCALE_SHIFT)
|
||||
#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase */
|
||||
# define LPSPI_TCR_CPHA_CPT_LEAD (0 << 30) /* Data captured - leading edge of SCK and changed - following edge of SCK */
|
||||
# define LPSPI_TCR_CPHA_CPT_FOLLOW (1 << 30) /* Data changed - leading edge of SCK and captured - following edge of SCK */
|
||||
#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity */
|
||||
# define LPSPI_TCR_CPOL_INACT_LOW (0 << 31) /* The inactive state value of SCK is low */
|
||||
# define LPSPI_TCR_CPOL_INACT_HIGH (1 << 31) /* The inactive state value of SCK is high */
|
||||
|
||||
/* Transmit Data Register */
|
||||
|
||||
#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data */
|
||||
# define LPSPI_TCR_DATA(n) ((uint32_t)(n) << LPSPI_TDR_DATA_SHIFT)
|
||||
|
||||
/* Receive Status Register */
|
||||
|
||||
#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame */
|
||||
#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* Receive Data Register */
|
||||
|
||||
#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data */
|
||||
#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_LPSPI_H */
|
||||
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