drivers: sensors: fix Mixed Case errors
Fix Mixed Case errors reposrted by nxstyle. Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea
Xiang Xiao
parent
7a29e1f5fb
commit
3631809e9d
@ -370,30 +370,30 @@ static int bmg160_open(FAR struct file *filep)
|
||||
|
||||
bmg160_write_register(priv,
|
||||
BMG160_RANGE_REG,
|
||||
BMG160_RANGE_REG_FIX_VAL_bm |
|
||||
BMG160_RANGE_REG_FSR_1_bm |
|
||||
BMG160_RANGE_REG_FSR_0_bm);
|
||||
BMG160_RANGE_REG_FIX_VAL_BM |
|
||||
BMG160_RANGE_REG_FSR_1_BM |
|
||||
BMG160_RANGE_REG_FSR_0_BM);
|
||||
|
||||
/* Enable - the fastest data output rate ODR = 2000 Hz -> BW = 230 Hz */
|
||||
|
||||
bmg160_write_register(priv, BMG160_BW_REG, BMG160_BW_REG_ODR_0_bm);
|
||||
bmg160_write_register(priv, BMG160_BW_REG, BMG160_BW_REG_ODR_0_BM);
|
||||
|
||||
/* Enable - new data interrupt 1 */
|
||||
|
||||
bmg160_write_register(priv,
|
||||
BMG160_INT_EN_0_REG, BMG160_INT_EN_0_REG_DATA_EN_bm);
|
||||
BMG160_INT_EN_0_REG, BMG160_INT_EN_0_REG_DATA_EN_BM);
|
||||
|
||||
/* Enable - active high level interrupt 1 - push-pull interrupt */
|
||||
|
||||
bmg160_write_register(priv,
|
||||
BMG160_INT_EN_1_REG,
|
||||
BMG160_INT_EN_1_REG_INT1_LVL_bm);
|
||||
BMG160_INT_EN_1_REG_INT1_LVL_BM);
|
||||
|
||||
/* Enable - map new data interrupt to INT1 */
|
||||
|
||||
bmg160_write_register(priv,
|
||||
BMG160_INT_MAP_1_REG,
|
||||
BMG160_INT_MAP_1_REG_INT1_DATA_bm);
|
||||
BMG160_INT_MAP_1_REG_INT1_DATA_BM);
|
||||
|
||||
/* Read measurement data to ensure DRDY is low */
|
||||
|
||||
|
||||
@ -199,7 +199,7 @@ static void lis3mdl_reset(FAR struct lis3mdl_dev_s *dev)
|
||||
{
|
||||
lis3mdl_write_register(dev,
|
||||
LIS3MDL_CTRL_REG_2,
|
||||
LIS3MDL_CTRL_REG_2_SOFT_RST_bm);
|
||||
LIS3MDL_CTRL_REG_2_SOFT_RST_BM);
|
||||
|
||||
up_mdelay(100);
|
||||
}
|
||||
@ -404,8 +404,8 @@ static int lis3mdl_open(FAR struct file *filep)
|
||||
|
||||
lis3mdl_write_register(priv,
|
||||
LIS3MDL_CTRL_REG_2,
|
||||
LIS3MDL_CTRL_REG_2_FS_1_bm |
|
||||
LIS3MDL_CTRL_REG_2_FS_0_bm);
|
||||
LIS3MDL_CTRL_REG_2_FS_1_BM |
|
||||
LIS3MDL_CTRL_REG_2_FS_0_BM);
|
||||
|
||||
/* Enable - temperature sensor - ultra high performance mode (UMP) for X
|
||||
* and Y - fast output data rates This results in a output data rate of
|
||||
@ -414,10 +414,10 @@ static int lis3mdl_open(FAR struct file *filep)
|
||||
|
||||
lis3mdl_write_register(priv,
|
||||
LIS3MDL_CTRL_REG_1,
|
||||
LIS3MDL_CTRL_REG_1_TEMP_EN_bm |
|
||||
LIS3MDL_CTRL_REG_1_OM_1_bm |
|
||||
LIS3MDL_CTRL_REG_1_OM_0_bm |
|
||||
LIS3MDL_CTRL_REG_1_FAST_ODR_bm);
|
||||
LIS3MDL_CTRL_REG_1_TEMP_EN_BM |
|
||||
LIS3MDL_CTRL_REG_1_OM_1_BM |
|
||||
LIS3MDL_CTRL_REG_1_OM_0_BM |
|
||||
LIS3MDL_CTRL_REG_1_FAST_ODR_BM);
|
||||
|
||||
/* Enable * - ultra high performance mode (UMP) for Z * This should result
|
||||
* to the same output data rate as for X and Y.
|
||||
@ -425,8 +425,8 @@ static int lis3mdl_open(FAR struct file *filep)
|
||||
|
||||
lis3mdl_write_register(priv,
|
||||
LIS3MDL_CTRL_REG_4,
|
||||
LIS3MDL_CTRL_REG_4_OMZ_1_bm |
|
||||
LIS3MDL_CTRL_REG_4_OMZ_0_bm);
|
||||
LIS3MDL_CTRL_REG_4_OMZ_1_BM |
|
||||
LIS3MDL_CTRL_REG_4_OMZ_0_BM);
|
||||
|
||||
/* Enable * - block data update for magnetic sensor data * This should
|
||||
* prevent race conditions when reading sensor data.
|
||||
@ -434,7 +434,7 @@ static int lis3mdl_open(FAR struct file *filep)
|
||||
|
||||
lis3mdl_write_register(priv,
|
||||
LIS3MDL_CTRL_REG_5,
|
||||
LIS3MDL_CTRL_REG_5_BDU_bm);
|
||||
LIS3MDL_CTRL_REG_5_BDU_BM);
|
||||
|
||||
/* Enable continuous conversion mode - the device starts measuring now. */
|
||||
|
||||
|
||||
@ -138,7 +138,7 @@ static void mlx90393_start_burst_mode(FAR struct mlx90393_dev_s *dev)
|
||||
|
||||
/* Start Burst Mode (Continuous Measurement on all channels) */
|
||||
|
||||
SPI_SEND(dev->spi, MLX90393_SB | MLX90393_ZYXT_bm);
|
||||
SPI_SEND(dev->spi, MLX90393_SB | MLX90393_ZYXT_BM);
|
||||
|
||||
/* Write an idle byte to retrieve the status byte */
|
||||
|
||||
@ -173,7 +173,7 @@ static void mlx90393_read_measurement_data(FAR struct mlx90393_dev_s *dev)
|
||||
|
||||
/* Issue command to read measurement data on all channels */
|
||||
|
||||
SPI_SEND(dev->spi, MLX90393_RM | MLX90393_ZYXT_bm);
|
||||
SPI_SEND(dev->spi, MLX90393_RM | MLX90393_ZYXT_BM);
|
||||
|
||||
/* Write an idle byte to retrieve the status byte */
|
||||
|
||||
|
||||
@ -144,206 +144,206 @@
|
||||
|
||||
/* BMG160 RANGE_REG Definitions */
|
||||
|
||||
#define BMG160_RANGE_REG_FSR_0_bm (1 << 0) /* Full scale selection bit 0 */
|
||||
#define BMG160_RANGE_REG_FSR_1_bm (1 << 1) /* Full scale selection bit 1 */
|
||||
#define BMG160_RANGE_REG_FSR_2_bm (1 << 2) /* Full scale selection bit 2 */
|
||||
#define BMG160_RANGE_REG_FIX_VAL_bm (1 << 7) /* write 1 to 7th bit of Range Register */
|
||||
#define BMG160_RANGE_REG_FSR_0_BM (1 << 0) /* Full scale selection bit 0 */
|
||||
#define BMG160_RANGE_REG_FSR_1_BM (1 << 1) /* Full scale selection bit 1 */
|
||||
#define BMG160_RANGE_REG_FSR_2_BM (1 << 2) /* Full scale selection bit 2 */
|
||||
#define BMG160_RANGE_REG_FIX_VAL_BM (1 << 7) /* write 1 to 7th bit of Range Register */
|
||||
|
||||
/* BMG160 BW_REG Definitions */
|
||||
|
||||
#define BMG160_BW_REG_ODR_0_bm (1 << 0) /* Output data rate selection bit 0 */
|
||||
#define BMG160_BW_REG_ODR_1_bm (1 << 1) /* Output data rate selection bit 1 */
|
||||
#define BMG160_BW_REG_ODR_2_bm (1 << 2) /* Output data rate selection bit 2 */
|
||||
#define BMG160_BW_REG_ODR_0_BM (1 << 0) /* Output data rate selection bit 0 */
|
||||
#define BMG160_BW_REG_ODR_1_BM (1 << 1) /* Output data rate selection bit 1 */
|
||||
#define BMG160_BW_REG_ODR_2_BM (1 << 2) /* Output data rate selection bit 2 */
|
||||
|
||||
/* BMG160 LPM1_REG Definitions */
|
||||
|
||||
#define BMG160_LPM1_REG_SP_bm (1 << 7) /* active suspend mode */
|
||||
#define BMG160_LPM1_REG_D_SP_bm (1 << 5) /* active deep suspend mode */
|
||||
#define BMG160_LPM1_REG_S_DUR_0_bm (1 << 1) /* Sleep duration selection bit 0 */
|
||||
#define BMG160_LPM1_REG_S_DUR_1_bm (1 << 2) /* Sleep duration selection bit 1 */
|
||||
#define BMG160_LPM1_REG_S_DUR_2_bm (1 << 3) /* Sleep duration selection bit 2 */
|
||||
#define BMG160_LPM1_REG_SP_BM (1 << 7) /* active suspend mode */
|
||||
#define BMG160_LPM1_REG_D_SP_BM (1 << 5) /* active deep suspend mode */
|
||||
#define BMG160_LPM1_REG_S_DUR_0_BM (1 << 1) /* Sleep duration selection bit 0 */
|
||||
#define BMG160_LPM1_REG_S_DUR_1_BM (1 << 2) /* Sleep duration selection bit 1 */
|
||||
#define BMG160_LPM1_REG_S_DUR_2_BM (1 << 3) /* Sleep duration selection bit 2 */
|
||||
|
||||
/* BMG160 LPM1_REG Definitions */
|
||||
|
||||
#define BMG160_LPM1_REG_AS_DUR_0_bm (1 << 0) /* Auto sleep duration selection bit 0 */
|
||||
#define BMG160_LPM1_REG_AS_DUR_1_bm (1 << 1) /* Auto sleep duration selection bit 1 */
|
||||
#define BMG160_LPM1_REG_AS_DUR_2_bm (1 << 2) /* Auto sleep duration selection bit 2 */
|
||||
#define BMG160_LPM1_REG_E_T_S_0_bm (1 << 4) /* External trigger selection bit 0 */
|
||||
#define BMG160_LPM1_REG_E_T_S_1_bm (1 << 5) /* External trigger selection bit 1 */
|
||||
#define BMG160_LPM1_REG_P_S_M_bm (1 << 6) /* Power save mode */
|
||||
#define BMG160_LPM1_REG_FAST_PU_bm (1 << 7) /* Fast power-up mode */
|
||||
#define BMG160_LPM1_REG_AS_DUR_0_BM (1 << 0) /* Auto sleep duration selection bit 0 */
|
||||
#define BMG160_LPM1_REG_AS_DUR_1_BM (1 << 1) /* Auto sleep duration selection bit 1 */
|
||||
#define BMG160_LPM1_REG_AS_DUR_2_BM (1 << 2) /* Auto sleep duration selection bit 2 */
|
||||
#define BMG160_LPM1_REG_E_T_S_0_BM (1 << 4) /* External trigger selection bit 0 */
|
||||
#define BMG160_LPM1_REG_E_T_S_1_BM (1 << 5) /* External trigger selection bit 1 */
|
||||
#define BMG160_LPM1_REG_P_S_M_BM (1 << 6) /* Power save mode */
|
||||
#define BMG160_LPM1_REG_FAST_PU_BM (1 << 7) /* Fast power-up mode */
|
||||
|
||||
/* BMG160 RATE_HBW_REG Definitions */
|
||||
|
||||
#define BMG160_HBW_REG_DATA_HIGH_BW_bm (1 << 7) /* Enable unfiltered data reading */
|
||||
#define BMG160_HBW_REG_SHW_DIS_bm (1 << 6) /* Disable shadow mechanism for the rate data output register */
|
||||
#define BMG160_HBW_REG_DATA_HIGH_BW_BM (1 << 7) /* Enable unfiltered data reading */
|
||||
#define BMG160_HBW_REG_SHW_DIS_BM (1 << 6) /* Disable shadow mechanism for the rate data output register */
|
||||
|
||||
/* Interrupt Status Register Definitions ************************************/
|
||||
|
||||
/* BMG160 INT_EN_0_REG Definitions */
|
||||
|
||||
#define BMG160_INT_EN_0_REG_DATA_EN_bm (1 << 7) /* Enable new data interrupt */
|
||||
#define BMG160_INT_EN_0_REG_FIFO_EN_bm (1 << 6) /* Enable FIFO interrupt */
|
||||
#define BMG160_INT_EN_0_REG_AUTO_OFF_EN_bm (1 << 1) /* Enable auto-offset compensation */
|
||||
#define BMG160_INT_EN_0_REG_DATA_EN_BM (1 << 7) /* Enable new data interrupt */
|
||||
#define BMG160_INT_EN_0_REG_FIFO_EN_BM (1 << 6) /* Enable FIFO interrupt */
|
||||
#define BMG160_INT_EN_0_REG_AUTO_OFF_EN_BM (1 << 1) /* Enable auto-offset compensation */
|
||||
|
||||
/* BMG160 INT_EN_1_REG Definitions */
|
||||
|
||||
#define BMG160_INT_EN_1_REG_INT2_OD_bm (1 << 3) /* Select open drive for INT2 */
|
||||
#define BMG160_INT_EN_1_REG_INT2_LVL_bm (1 << 2) /* Select active level '1' for INT2 */
|
||||
#define BMG160_INT_EN_1_REG_INT1_OD_bm (1 << 1) /* Select open drive for INT1 */
|
||||
#define BMG160_INT_EN_1_REG_INT1_LVL_bm (1 << 0) /* Select active level '1' for INT1 */
|
||||
#define BMG160_INT_EN_1_REG_INT2_OD_BM (1 << 3) /* Select open drive for INT2 */
|
||||
#define BMG160_INT_EN_1_REG_INT2_LVL_BM (1 << 2) /* Select active level '1' for INT2 */
|
||||
#define BMG160_INT_EN_1_REG_INT1_OD_BM (1 << 1) /* Select open drive for INT1 */
|
||||
#define BMG160_INT_EN_1_REG_INT1_LVL_BM (1 << 0) /* Select active level '1' for INT1 */
|
||||
|
||||
/* BMG160 INT_MAP_0_REG Definitions */
|
||||
|
||||
#define BMG160_INT_MAP_0_REG_INT1_HIGH_bm (1 << 3) /* Map high rate interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_0_REG_INT1_ANY_bm (1 << 1) /* Map Any-Motion to INT1 pin */
|
||||
#define BMG160_INT_MAP_0_REG_INT1_HIGH_BM (1 << 3) /* Map high rate interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_0_REG_INT1_ANY_BM (1 << 1) /* Map Any-Motion to INT1 pin */
|
||||
|
||||
/* BMG160 INT_MAP_1_REG Definitions */
|
||||
|
||||
#define BMG160_INT_MAP_1_REG_INT2_DATA_bm (1 << 7) /* Map new data interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_Fast_OFF_bm (1 << 6) /* Map Fast Offset interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_FIFO_bm (1 << 5) /* Map FIFO interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_AUTO_OFF_bm (1 << 4) /* Map Auto Offset tap interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_AUTO_OFF_bm (1 << 3) /* Map Auto Offset tap interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_FIFO_bm (1 << 2) /* Map FIFO interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_Fast_OFF_bm (1 << 1) /* Map Fast Offset interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_DATA_bm (1 << 0) /* Map new data interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_DATA_BM (1 << 7) /* Map new data interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_FAST_OFF_BM (1 << 6) /* Map Fast Offset interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_FIFO_BM (1 << 5) /* Map FIFO interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT2_AUTO_OFF_BM (1 << 4) /* Map Auto Offset tap interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_AUTO_OFF_BM (1 << 3) /* Map Auto Offset tap interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_FIFO_BM (1 << 2) /* Map FIFO interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_FAST_OFF_BM (1 << 1) /* Map Fast Offset interrupt to INT1 pin */
|
||||
#define BMG160_INT_MAP_1_REG_INT1_DATA_BM (1 << 0) /* Map new data interrupt to INT1 pin */
|
||||
|
||||
/* BMG160 INT_MAP_2_REG Definitions */
|
||||
|
||||
#define BMG160_INT_MAP_0_REG_INT2_HIGH_bm (1 << 3) /* Map high rate interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_0_REG_INT2_ANY_bm (1 << 1) /* Map Any-Motion to INT2 pin */
|
||||
#define BMG160_INT_MAP_0_REG_INT2_HIGH_BM (1 << 3) /* Map high rate interrupt to INT2 pin */
|
||||
#define BMG160_INT_MAP_0_REG_INT2_ANY_BM (1 << 1) /* Map Any-Motion to INT2 pin */
|
||||
|
||||
/* BMG160 INT_ZERO_REG Definitions */
|
||||
|
||||
#define BMG160_INT_ZERO_REG_SLOW_OFF_UN_bm (1 << 5) /* Selects unfiltered data for slow offset compensation */
|
||||
#define BMG160_INT_ZERO_REG_HIGH_UN_D_bm (1 << 3) /* Selects unfiltered data for high rate interrupt */
|
||||
#define BMG160_INT_ZERO_REG_ANY_UN_D_bm (1 << 1) /* Selects unfiltered data for any motion interrupt */
|
||||
#define BMG160_INT_ZERO_REG_SLOW_OFF_UN_BM (1 << 5) /* Selects unfiltered data for slow offset compensation */
|
||||
#define BMG160_INT_ZERO_REG_HIGH_UN_D_BM (1 << 3) /* Selects unfiltered data for high rate interrupt */
|
||||
#define BMG160_INT_ZERO_REG_ANY_UN_D_BM (1 << 1) /* Selects unfiltered data for any motion interrupt */
|
||||
|
||||
/* BMG160 INT_ONE_REG Definitions */
|
||||
|
||||
#define BMG160_INT_ONE_REG_FAST_OFF_UN_bm (1 << 7) /* Selects unfiltered data for fast offset compensation */
|
||||
#define BMG160_INT_ONE_REG_FAST_OFF_UN_BM (1 << 7) /* Selects unfiltered data for fast offset compensation */
|
||||
|
||||
/* BMG160 INT_TWO_REG Definitions */
|
||||
|
||||
#define BMG160_INT_TWO_REG_ANY_EN_Z_bm (1 << 2) /* Enables any motion interrupt for z-axis */
|
||||
#define BMG160_INT_TWO_REG_ANY_EN_Y_bm (1 << 1) /* Enables any motion interrupt for y-axis */
|
||||
#define BMG160_INT_TWO_REG_ANY_EN_X_bm (1 << 0) /* Enables any motion interrupt for x-axis */
|
||||
#define BMG160_INT_TWO_REG_ANY_EN_Z_BM (1 << 2) /* Enables any motion interrupt for z-axis */
|
||||
#define BMG160_INT_TWO_REG_ANY_EN_Y_BM (1 << 1) /* Enables any motion interrupt for y-axis */
|
||||
#define BMG160_INT_TWO_REG_ANY_EN_X_BM (1 << 0) /* Enables any motion interrupt for x-axis */
|
||||
|
||||
/* BMG160 INT_FOUR_REG Definitions */
|
||||
|
||||
#define BMG160_INT_FOUR_REG_FIFO_WM_EN_bm (1 << 2) /* Enables fifo water mark level interrupt */
|
||||
#define BMG160_INT_FOUR_REG_FIFO_WM_EN_BM (1 << 2) /* Enables fifo water mark level interrupt */
|
||||
|
||||
/* BMG160 INT_RST_LATCH_REG Definitions */
|
||||
|
||||
#define BMG160_INT_RST_LATCH_REG_RST_INT_bm (1 << 7) /* Clears any latched interrupts */
|
||||
#define BMG160_INT_RST_LATCH_REG_OFF_RST_bm (1 << 6) /* Resets the Offset value calculated with Fast-, Slow- and AutoOffset */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_STAT_bm (1 << 4)
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_3_bm (1 << 3) /* Latch mode selection bit 3 */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_2_bm (1 << 2) /* Latch mode selection bit 2 */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_1_bm (1 << 1) /* Latch mode selection bit 1 */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_0_bm (1 << 0) /* Latch mode selection bit 0 */
|
||||
#define BMG160_INT_RST_LATCH_REG_RST_INT_BM (1 << 7) /* Clears any latched interrupts */
|
||||
#define BMG160_INT_RST_LATCH_REG_OFF_RST_BM (1 << 6) /* Resets the Offset value calculated with Fast-, Slow- and AutoOffset */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_STAT_BM (1 << 4)
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_3_BM (1 << 3) /* Latch mode selection bit 3 */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_2_BM (1 << 2) /* Latch mode selection bit 2 */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_1_BM (1 << 1) /* Latch mode selection bit 1 */
|
||||
#define BMG160_INT_RST_LATCH_REG_LATCH_INT_0_BM (1 << 0) /* Latch mode selection bit 0 */
|
||||
|
||||
/* Interrupt High Rate Configuration Register Definitions *******************/
|
||||
|
||||
/* BMG160 HIGH_TH_X_REG Definitions */
|
||||
|
||||
#define BMG160_HIGH_TH_X_REG_HY_X_1_bm (1 << 7)
|
||||
#define BMG160_HIGH_TH_X_REG_HY_X_0_bm (1 << 6)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_4_bm (1 << 5)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_3_bm (1 << 4)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_2_bm (1 << 3)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_1_bm (1 << 2)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_0_bm (1 << 1)
|
||||
#define BMG160_HIGH_TH_X_REG_EN_X_1_bm (1 << 0) /* Enables high rate interrupt for x-axis */
|
||||
#define BMG160_HIGH_TH_X_REG_HY_X_1_BM (1 << 7)
|
||||
#define BMG160_HIGH_TH_X_REG_HY_X_0_BM (1 << 6)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_4_BM (1 << 5)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_3_BM (1 << 4)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_2_BM (1 << 3)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_1_BM (1 << 2)
|
||||
#define BMG160_HIGH_TH_X_REG_TH_X_0_BM (1 << 1)
|
||||
#define BMG160_HIGH_TH_X_REG_EN_X_1_BM (1 << 0) /* Enables high rate interrupt for x-axis */
|
||||
|
||||
/* BMG160 HIGH_DUR_X_REG Definitions */
|
||||
|
||||
#define BMG160_HIGH_DUR_X_REG_7_bm (1 << 7)
|
||||
#define BMG160_HIGH_DUR_X_REG_6_bm (1 << 6)
|
||||
#define BMG160_HIGH_DUR_X_REG_5_bm (1 << 5)
|
||||
#define BMG160_HIGH_DUR_X_REG_4_bm (1 << 4)
|
||||
#define BMG160_HIGH_DUR_X_REG_3_bm (1 << 3)
|
||||
#define BMG160_HIGH_DUR_X_REG_2_bm (1 << 2)
|
||||
#define BMG160_HIGH_DUR_X_REG_1_bm (1 << 1)
|
||||
#define BMG160_HIGH_DUR_X_REG_0_bm (1 << 0)
|
||||
#define BMG160_HIGH_DUR_X_REG_7_BM (1 << 7)
|
||||
#define BMG160_HIGH_DUR_X_REG_6_BM (1 << 6)
|
||||
#define BMG160_HIGH_DUR_X_REG_5_BM (1 << 5)
|
||||
#define BMG160_HIGH_DUR_X_REG_4_BM (1 << 4)
|
||||
#define BMG160_HIGH_DUR_X_REG_3_BM (1 << 3)
|
||||
#define BMG160_HIGH_DUR_X_REG_2_BM (1 << 2)
|
||||
#define BMG160_HIGH_DUR_X_REG_1_BM (1 << 1)
|
||||
#define BMG160_HIGH_DUR_X_REG_0_BM (1 << 0)
|
||||
|
||||
/* BMG160 HIGH_TH_Y_REG Definitions */
|
||||
|
||||
#define BMG160_HIGH_TH_Y_REG_HY_Y_1_bm (1 << 7)
|
||||
#define BMG160_HIGH_TH_Y_REG_HY_Y_0_bm (1 << 6)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_4_bm (1 << 5)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_3_bm (1 << 4)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_2_bm (1 << 3)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_1_bm (1 << 2)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_0_bm (1 << 1)
|
||||
#define BMG160_HIGH_TH_Y_REG_EN_Y_1_bm (1 << 0) /* Enables high rate interrupt for Y-axis */
|
||||
#define BMG160_HIGH_TH_Y_REG_HY_Y_1_BM (1 << 7)
|
||||
#define BMG160_HIGH_TH_Y_REG_HY_Y_0_BM (1 << 6)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_4_BM (1 << 5)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_3_BM (1 << 4)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_2_BM (1 << 3)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_1_BM (1 << 2)
|
||||
#define BMG160_HIGH_TH_Y_REG_TH_Y_0_BM (1 << 1)
|
||||
#define BMG160_HIGH_TH_Y_REG_EN_Y_1_BM (1 << 0) /* Enables high rate interrupt for Y-axis */
|
||||
|
||||
/* BMG160 HIGH_DUR_Y_REG Definitions */
|
||||
|
||||
#define BMG160_HIGH_DUR_Y_REG_7_bm (1 << 7)
|
||||
#define BMG160_HIGH_DUR_Y_REG_6_bm (1 << 6)
|
||||
#define BMG160_HIGH_DUR_Y_REG_5_bm (1 << 5)
|
||||
#define BMG160_HIGH_DUR_Y_REG_4_bm (1 << 4)
|
||||
#define BMG160_HIGH_DUR_Y_REG_3_bm (1 << 3)
|
||||
#define BMG160_HIGH_DUR_Y_REG_2_bm (1 << 2)
|
||||
#define BMG160_HIGH_DUR_Y_REG_1_bm (1 << 1)
|
||||
#define BMG160_HIGH_DUR_Y_REG_0_bm (1 << 0)
|
||||
#define BMG160_HIGH_DUR_Y_REG_7_BM (1 << 7)
|
||||
#define BMG160_HIGH_DUR_Y_REG_6_BM (1 << 6)
|
||||
#define BMG160_HIGH_DUR_Y_REG_5_BM (1 << 5)
|
||||
#define BMG160_HIGH_DUR_Y_REG_4_BM (1 << 4)
|
||||
#define BMG160_HIGH_DUR_Y_REG_3_BM (1 << 3)
|
||||
#define BMG160_HIGH_DUR_Y_REG_2_BM (1 << 2)
|
||||
#define BMG160_HIGH_DUR_Y_REG_1_BM (1 << 1)
|
||||
#define BMG160_HIGH_DUR_Y_REG_0_BM (1 << 0)
|
||||
|
||||
/* BMG160 HIGH_TH_Z_REG Definitions */
|
||||
|
||||
#define BMG160_HIGH_TH_Z_REG_HY_Z_1_bm (1 << 7)
|
||||
#define BMG160_HIGH_TH_Z_REG_HY_Z_0_bm (1 << 6)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_4_bm (1 << 5)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_3_bm (1 << 4)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_2_bm (1 << 3)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_1_bm (1 << 2)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_0_bm (1 << 1)
|
||||
#define BMG160_HIGH_TH_Z_REG_EN_Z_1_bm (1 << 0) /* Enables high rate interrupt for Z-axis */
|
||||
#define BMG160_HIGH_TH_Z_REG_HY_Z_1_BM (1 << 7)
|
||||
#define BMG160_HIGH_TH_Z_REG_HY_Z_0_BM (1 << 6)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_4_BM (1 << 5)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_3_BM (1 << 4)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_2_BM (1 << 3)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_1_BM (1 << 2)
|
||||
#define BMG160_HIGH_TH_Z_REG_TH_Z_0_BM (1 << 1)
|
||||
#define BMG160_HIGH_TH_Z_REG_EN_Z_1_BM (1 << 0) /* Enables high rate interrupt for Z-axis */
|
||||
|
||||
/* BMG160 HIGH_DUR_Z_REG Definitions */
|
||||
|
||||
#define BMG160_HIGH_DUR_Z_REG_7_bm (1 << 7)
|
||||
#define BMG160_HIGH_DUR_Z_REG_6_bm (1 << 6)
|
||||
#define BMG160_HIGH_DUR_Z_REG_5_bm (1 << 5)
|
||||
#define BMG160_HIGH_DUR_Z_REG_4_bm (1 << 4)
|
||||
#define BMG160_HIGH_DUR_Z_REG_3_bm (1 << 3)
|
||||
#define BMG160_HIGH_DUR_Z_REG_2_bm (1 << 2)
|
||||
#define BMG160_HIGH_DUR_Z_REG_1_bm (1 << 1)
|
||||
#define BMG160_HIGH_DUR_Z_REG_0_bm (1 << 0)
|
||||
#define BMG160_HIGH_DUR_Z_REG_7_BM (1 << 7)
|
||||
#define BMG160_HIGH_DUR_Z_REG_6_BM (1 << 6)
|
||||
#define BMG160_HIGH_DUR_Z_REG_5_BM (1 << 5)
|
||||
#define BMG160_HIGH_DUR_Z_REG_4_BM (1 << 4)
|
||||
#define BMG160_HIGH_DUR_Z_REG_3_BM (1 << 3)
|
||||
#define BMG160_HIGH_DUR_Z_REG_2_BM (1 << 2)
|
||||
#define BMG160_HIGH_DUR_Z_REG_1_BM (1 << 1)
|
||||
#define BMG160_HIGH_DUR_Z_REG_0_BM (1 << 0)
|
||||
|
||||
/* Offset Register Definitions **********************************************/
|
||||
|
||||
/* BMG160 SOC_REG */
|
||||
|
||||
#define BMG160_SOC_REG_SLOW_OFF_EN_Z_bm (1 << 2) /* Enables slow offset compensation for z-axis */
|
||||
#define BMG160_SOC_REG_SLOW_OFF_EN_Y_bm (1 << 1) /* Enables slow offset compensation for y-axis */
|
||||
#define BMG160_SOC_REG_SLOW_OFF_EN_X_bm (1 << 0) /* Enables slow offset compensation for x-axis */
|
||||
#define BMG160_SOC_REG_SLOW_OFF_EN_Z_BM (1 << 2) /* Enables slow offset compensation for z-axis */
|
||||
#define BMG160_SOC_REG_SLOW_OFF_EN_Y_BM (1 << 1) /* Enables slow offset compensation for y-axis */
|
||||
#define BMG160_SOC_REG_SLOW_OFF_EN_X_BM (1 << 0) /* Enables slow offset compensation for x-axis */
|
||||
|
||||
/* BMG160 FOC_REG */
|
||||
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_bm (1 << 2) /* Triggers the fast offset compensation for the enabled axes */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_Z_bm (1 << 2) /* Enables fast offset compensation for z-axis */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_Y_bm (1 << 1) /* Enables fast offset compensation for y-axis */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_X_bm (1 << 0) /* Enables fast offset compensation for x-axis */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_BM (1 << 2) /* Triggers the fast offset compensation for the enabled axes */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_Z_BM (1 << 2) /* Enables fast offset compensation for z-axis */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_Y_BM (1 << 1) /* Enables fast offset compensation for y-axis */
|
||||
#define BMG160_FOC_REG_FAST_OFF_EN_X_BM (1 << 0) /* Enables fast offset compensation for x-axis */
|
||||
|
||||
/* NVM Control Register Definitions *****************************************/
|
||||
|
||||
/* BMG160 TRIM_NVM_CTRL_REG */
|
||||
|
||||
#define BMG160_TRIM_NVM_CTRL_REG_NVM_LOAD_bm (1 << 3) /* Triggers an update of all config registers form NVM,
|
||||
#define BMG160_TRIM_NVM_CTRL_REG_NVM_LOAD_BM (1 << 3) /* Triggers an update of all config registers form NVM,
|
||||
* the NVM_RDY flag must be '1' prior to triggering the update */
|
||||
#define BMG160_TRIM_NVM_CTRL_REG_NVM_PROG_TRIG_bm (1 << 1) /* Triggers an NVM write operation; (see page 59, data sheet)
|
||||
#define BMG160_TRIM_NVM_CTRL_REG_NVM_PROG_TRIG_BM (1 << 1) /* Triggers an NVM write operation; (see page 59, data sheet)
|
||||
* the NVM_RDY flag must be '1' prior to triggering the update */
|
||||
#define BMG160_TRIM_NVM_CTRL_REG_NVM_PROG_MODE_bm (1 << 0) /* unlock NVM write operation */
|
||||
#define BMG160_TRIM_NVM_CTRL_REG_NVM_PROG_MODE_BM (1 << 0) /* unlock NVM write operation */
|
||||
|
||||
/* Digital Interface Register Definitions ***********************************/
|
||||
|
||||
/* BMG160 BGW_SPI3_WDT_REG */
|
||||
|
||||
#define BMG160_BGW_SPI3_WDT_REG_I2C_WDT_EN_bm (1 << 2) /* Enables watchdog at the SDA pin if I2C mode is selected */
|
||||
#define BMG160_BGW_SPI3_WDT_REG_I2C_WDT_SEL_bm (1 << 1) /* Select an I2C watchdog timer period of 50ms */
|
||||
#define BMG160_BGW_SPI3_WDT_REG_SPI3_bm (1 << 0) /* Enable 3-wire SPI mode */
|
||||
#define BMG160_BGW_SPI3_WDT_REG_I2C_WDT_EN_BM (1 << 2) /* Enables watchdog at the SDA pin if I2C mode is selected */
|
||||
#define BMG160_BGW_SPI3_WDT_REG_I2C_WDT_SEL_BM (1 << 1) /* Select an I2C watchdog timer period of 50ms */
|
||||
#define BMG160_BGW_SPI3_WDT_REG_SPI3_BM (1 << 0) /* Enable 3-wire SPI mode */
|
||||
|
||||
/* Offset Configuration Register Definitions ********************************/
|
||||
|
||||
@ -351,14 +351,14 @@
|
||||
|
||||
/* BMG160 FIFO_CONFIG_0_REG */
|
||||
|
||||
#define BMG160_FIFO_CONFIG_0_REG_TAG_bm (1 << 7) /* Enables FIFO tag (interrupt) */
|
||||
#define BMG160_FIFO_CONFIG_0_REG_TAG_BM (1 << 7) /* Enables FIFO tag (interrupt) */
|
||||
|
||||
/* BMG160 FIFO_CONFIG_1_REG */
|
||||
|
||||
#define BMG160_FIFO_CONFIG_1_REG_MODE_1_bm (1 << 7) /* FIFO mode selection bit 1 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_MODE_0_bm (1 << 6) /* FIFO mode selection bit 0 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_DATA_SEL_1_bm (1 << 1) /* FIFO data selection bit 1 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_DATA_SEL_0_bm (1 << 0) /* FIFO data selection bit 0 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_MODE_1_BM (1 << 7) /* FIFO mode selection bit 1 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_MODE_0_BM (1 << 6) /* FIFO mode selection bit 0 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_DATA_SEL_1_BM (1 << 1) /* FIFO data selection bit 1 */
|
||||
#define BMG160_FIFO_CONFIG_1_REG_DATA_SEL_0_BM (1 << 0) /* FIFO data selection bit 0 */
|
||||
|
||||
/* SPI BUS PARAMETERS *******************************************************/
|
||||
|
||||
|
||||
@ -60,29 +60,29 @@
|
||||
|
||||
/* LIS3MDL CTRL_REG_1 Bit Definitions ***************************************/
|
||||
|
||||
#define LIS3MDL_CTRL_REG_1_TEMP_EN_bm (1<<7) /* Enable the temperature sensor */
|
||||
#define LIS3MDL_CTRL_REG_1_OM_1_bm (1<<6) /* Select the operating mode of X and Y axis bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_1_OM_0_bm (1<<5) /* Select the operating mode of X and Y axis bit 0 */
|
||||
#define LIS3MDL_CTRL_REG_1_DO2_bm (1<<4) /* Output data rate selection bit 2 */
|
||||
#define LIS3MDL_CTRL_REG_1_DO1_bm (1<<3) /* Output data rate selection bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_1_DO0_bm (1<<2) /* Output data rate selection bit 2 */
|
||||
#define LIS3MDL_CTRL_REG_1_FAST_ODR_bm (1<<1) /* Enable higher output data rates */
|
||||
#define LIS3MDL_CTRL_REG_1_TEMP_EN_BM (1<<7) /* Enable the temperature sensor */
|
||||
#define LIS3MDL_CTRL_REG_1_OM_1_BM (1<<6) /* Select the operating mode of X and Y axis bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_1_OM_0_BM (1<<5) /* Select the operating mode of X and Y axis bit 0 */
|
||||
#define LIS3MDL_CTRL_REG_1_DO2_BM (1<<4) /* Output data rate selection bit 2 */
|
||||
#define LIS3MDL_CTRL_REG_1_DO1_BM (1<<3) /* Output data rate selection bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_1_DO0_BM (1<<2) /* Output data rate selection bit 2 */
|
||||
#define LIS3MDL_CTRL_REG_1_FAST_ODR_BM (1<<1) /* Enable higher output data rates */
|
||||
|
||||
/* LIS3MDL CTRL_REG_2 Bit Definitions ***************************************/
|
||||
|
||||
#define LIS3MDL_CTRL_REG_2_FS_1_bm (1<<6) /* Full scale selection bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_2_FS_0_bm (1<<5) /* Full scale selection bit 0 */
|
||||
#define LIS3MDL_CTRL_REG_2_REBOOT_bm (1<<3) /* Reboot Memory Content */
|
||||
#define LIS3MDL_CTRL_REG_2_SOFT_RST_bm (1<<2) /* Soft Reset */
|
||||
#define LIS3MDL_CTRL_REG_2_FS_1_BM (1<<6) /* Full scale selection bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_2_FS_0_BM (1<<5) /* Full scale selection bit 0 */
|
||||
#define LIS3MDL_CTRL_REG_2_REBOOT_BM (1<<3) /* Reboot Memory Content */
|
||||
#define LIS3MDL_CTRL_REG_2_SOFT_RST_BM (1<<2) /* Soft Reset */
|
||||
|
||||
/* LIS3MDL CTRL_REG_4 Bit Definitions ***************************************/
|
||||
|
||||
#define LIS3MDL_CTRL_REG_4_OMZ_1_bm (1<<3) /* Select the operating mode of Z axis bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_4_OMZ_0_bm (1<<2) /* Select the operating mode of Z axis bit 0 */
|
||||
#define LIS3MDL_CTRL_REG_4_OMZ_1_BM (1<<3) /* Select the operating mode of Z axis bit 1 */
|
||||
#define LIS3MDL_CTRL_REG_4_OMZ_0_BM (1<<2) /* Select the operating mode of Z axis bit 0 */
|
||||
|
||||
/* LIS3MDL CTRL_REG_5 Bit Definitions ***************************************/
|
||||
|
||||
#define LIS3MDL_CTRL_REG_5_BDU_bm (1<<6) /* Enable block data update for magnetic data (prevent race conditions while reading) */
|
||||
#define LIS3MDL_CTRL_REG_5_BDU_BM (1<<6) /* Enable block data update for magnetic data (prevent race conditions while reading) */
|
||||
|
||||
/* SPI BUS PARAMETERS *******************************************************/
|
||||
|
||||
|
||||
@ -51,11 +51,11 @@
|
||||
|
||||
/* MLX90393 Sensor Selection Bit Definitions ********************************/
|
||||
|
||||
#define MLX90393_T_bm (1<<0) /* Temperature Sensor Bitmask */
|
||||
#define MLX90393_X_bm (1<<1) /* Magnetometer X-Axis Bitmask */
|
||||
#define MLX90393_Y_bm (1<<2) /* Magnetometer Y-Axis Bitmask */
|
||||
#define MLX90393_Z_bm (1<<3) /* Magnetometer Z-Axis Bitmask */
|
||||
#define MLX90393_ZYXT_bm (MLX90393_Z_bm | MLX90393_Y_bm | MLX90393_X_bm | MLX90393_T_bm)
|
||||
#define MLX90393_T_BM (1<<0) /* Temperature Sensor Bitmask */
|
||||
#define MLX90393_X_BM (1<<1) /* Magnetometer X-Axis Bitmask */
|
||||
#define MLX90393_Y_BM (1<<2) /* Magnetometer Y-Axis Bitmask */
|
||||
#define MLX90393_Z_BM (1<<3) /* Magnetometer Z-Axis Bitmask */
|
||||
#define MLX90393_ZYXT_BM (MLX90393_Z_BM | MLX90393_Y_BM | MLX90393_X_BM | MLX90393_T_BM)
|
||||
|
||||
/* SPI BUS PARAMETERS *******************************************************/
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user