Add FSMC support
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2163 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
8baaf18f1e
commit
3635d4d672
@ -283,7 +283,16 @@ STM3210E-EVAL-specific Configuration Options
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the delay actually is 100 seconds.
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Individual subsystems can be enabled:
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AHB
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---
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CONFIG_STM32_DMA1
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CONFIG_STM32_DMA2
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CONFIG_STM32_CRC
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CONFIG_STM32_FSMC
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CONFIG_STM32_SDIO
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APB1
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----
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CONFIG_STM32_TIM2
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CONFIG_STM32_TIM3
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CONFIG_STM32_TIM4
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@ -305,6 +314,9 @@ STM3210E-EVAL-specific Configuration Options
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CONFIG_STM32_PWR
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CONFIG_STM32_DAC
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CONFIG_STM32_USB
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APB2
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----
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CONFIG_STM32_ADC1
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CONFIG_STM32_ADC2
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CONFIG_STM32_TIM1
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@ -95,7 +95,14 @@ CONFIG_STM32_BUILDROOT=y
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CONFIG_STM32_DFU=y
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#
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# Individual subsystems can be enabled:
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# Individual subsystems can be enabled:
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# AHB:
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CONFIG_STM32_DMA1=n
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CONFIG_STM32_DMA2=n
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CONFIG_STM32_CRC=n
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CONFIG_STM32_FSMC=y
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CONFIG_STM32_SDIO=n
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# APB1:
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CONFIG_STM32_TIM2=n
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CONFIG_STM32_TIM3=n
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CONFIG_STM32_TIM4=n
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@ -116,6 +123,7 @@ CONFIG_STM32_CAN=n
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CONFIG_STM32_BKP=n
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CONFIG_STM32_PWR=n
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CONFIG_STM32_DAC=n
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# APB2:
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CONFIG_STM32_ADC1=n
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CONFIG_STM32_ADC2=n
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CONFIG_STM32_TIM1=n
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@ -96,6 +96,15 @@ CONFIG_STM32_DFU=y
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#
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# Individual subsystems can be enabled:
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#
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# Individual subsystems can be enabled:
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# AHB:
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CONFIG_STM32_DMA1=n
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CONFIG_STM32_DMA2=n
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CONFIG_STM32_CRC=n
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CONFIG_STM32_FSMC=y
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CONFIG_STM32_SDIO=n
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# APB1:
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CONFIG_STM32_TIM2=n
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CONFIG_STM32_TIM3=n
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CONFIG_STM32_TIM4=n
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@ -116,6 +125,7 @@ CONFIG_STM32_CAN=n
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CONFIG_STM32_BKP=n
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CONFIG_STM32_PWR=n
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CONFIG_STM32_DAC=n
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# APB2:
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CONFIG_STM32_ADC1=n
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CONFIG_STM32_ADC2=n
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CONFIG_STM32_TIM1=n
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@ -39,7 +39,7 @@ CFLAGS += -I$(TOPDIR)/sched
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ASRCS =
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AOBJS = $(ASRCS:.S=$(OBJEXT))
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CSRCS = up_boot.c up_leds.c up_spi.c
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CSRCS = up_boot.c up_leds.c up_spi.c up_extmem.c
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ifeq ($(CONFIG_EXAMPLES_NSH_ARCHINIT),y)
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CSRCS += up_nsh.c
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endif
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@ -74,6 +74,24 @@
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#define GPIO_FLASH_CS (GPIO_OUTPUT|GPIO_CNF_OUTPP|GPIO_MODE_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN2)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* GPIO settings that will be altered when external memory is selected */
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struct extmem_save_s
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{
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uint32 gpiod_crl;
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uint32 gpiod_crh;
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uint32 gpioe_crl;
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uint32 gpioe_crh;
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uint32 gpiof_crl;
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uint32 gpiof_crh;
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uint32 gpiog_crl;
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uint32 gpiog_crh;
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};
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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@ -90,6 +108,45 @@
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extern void weak_function stm32_spiinitialize(void);
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/************************************************************************************
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* Name: stm32_selectnor
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*
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* Description:
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* Initialize to access NOR flash
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*
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************************************************************************************/
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extern void stm32_selectnor(struct extmem_save_s *save);
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/************************************************************************************
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* Name: stm32_deselectnor
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*
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* Description:
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* Disable NOR FLASH
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*
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************************************************************************************/
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extern void stm32_deselectnor(struct extmem_save_s *restore);
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/************************************************************************************
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* Name: stm32_selectsram
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*
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* Description:
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* Initialize to access external SRAM
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*
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************************************************************************************/
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extern void stm32_selectsram(struct extmem_save_s *save);
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/************************************************************************************
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* Name: stm32_deselectsram
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*
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* Description:
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* Disable NOR FLASH
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*
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************************************************************************************/
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extern void stm32_deselectsram(struct extmem_save_s *restore);
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#endif /* __ASSEMBLY__ */
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#endif /* __CONFIGS_STM3210E_EVAL_SRC_STM3210E_INTERNAL_H */
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@ -71,15 +71,17 @@
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************************************************************************************/
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void stm32_boardinitialize(void)
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{
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{
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/* Initialize the DMA subsystem if the weak function stm32_dmainitialize has been
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* brought into the build
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*/
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#if defined(CONFIG_STM32_DMA1) || defined(CONFIG_STM32_DMA2)
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if (stm32_dmainitialize)
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{
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stm32_dmainitialize();
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}
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#endif
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/* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function
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* stm32_spiinitialize() has been brought into the link.
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380
configs/stm3210e-eval/src/up_extmem.c
Normal file
380
configs/stm3210e-eval/src/up_extmem.c
Normal file
@ -0,0 +1,380 @@
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/************************************************************************************
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* configs/stm3210e-eval/src/up_extmem.c
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* arch/arm/src/board/up_extmem.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <assert.h>
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#include <debug.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "chip.h"
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#include "stm32_fsmc.h"
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#include "stm32_gpio.h"
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#include "stm32_internal.h"
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#include "stm3210e-internal.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#ifndef CONFIG_STM32_FSMC
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# warning "FSMC is not enabled"
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#endif
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#if STM32_NGPIO_PORTS < 6
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# error "Required GPIO ports not enabled"
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#endif
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/************************************************************************************
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* Private Data
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************************************************************************************/
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/* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit
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* accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM,
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* respectively.
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*
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* Pin Usage (per schematic)
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* FLASH SRAM NAND
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* D[0..15] [0..15] [0..15] [0..7]
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* A[0..23] [0..22] [0..18] [16,17]
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* PSMC_NE3 PG10 OUT ~CE --- ---
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* PSMC_NBL0 PE0 OUT ~BLE --- ---
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* PSMC_NBL1 PE1 OUT ~BHE --- ---
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* PSMC_NE2 PG9 OUT --- ~E ---
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* PSMC_NWE PD5 OUT ~WE ~W ~W
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* PSMC_NOE PD4 OUT ~OE ~G ~R
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* PSMC_NWAIT PD6 IN --- R~B ---
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* PSMC_INT2 PG6* IN --- --- R~B
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*
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* *JP7 will switch to PD6
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*/
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/* It would be much more efficient to brute force these all into the
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* the appropriate registers. Just a little tricky.
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*/
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/* GPIO configurations common to SRAM and NOR Flash */
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static const uint16 g_commonconfig[] =
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{
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/* A0... A18 */
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GPIO_NPS_A0, GPIO_NPS_A1, GPIO_NPS_A2, GPIO_NPS_A3,
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GPIO_NPS_A4, GPIO_NPS_A5, GPIO_NPS_A6, GPIO_NPS_A7,
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GPIO_NPS_A8, GPIO_NPS_A9, GPIO_NPS_A10, GPIO_NPS_A11,
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GPIO_NPS_A12, GPIO_NPS_A13, GPIO_NPS_A14, GPIO_NPS_A15,
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GPIO_NPS_A16, GPIO_NPS_A17, GPIO_NPS_A18,
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/* D0... D15 */
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GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3,
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GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7,
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GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11,
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GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15,
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/* NOE, NWE, NE3 */
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GPIO_NPS_NOE, GPIO_NPS_NWE
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};
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#define NCOMMON_CONFIG (sizeof(g_commonconfig)/sizeof(uint16))
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/* GPIO configurations unique to SRAM */
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static const uint16 g_sramconfig[] =
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{
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/* NE3, NBL0, NBL1, */
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GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1
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};
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#define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16))
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/* GPIO configurations unique to NOR Flash */
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static const uint16 g_norconfig[] =
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{
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/* A19... A22 */
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GPIO_NPS_A19, GPIO_NPS_A20, GPIO_NPS_A21, GPIO_NPS_A22,
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/* NE2 */
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GPIO_NPS_NE2
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};
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#define NNOR_CONFIG (sizeof(g_norconfig)/sizeof(uint16))
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_extmemgpios
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*
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* Description:
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* Initialize GPIOs for NOR or SRAM
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*
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************************************************************************************/
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static void stm32_extmemgpios(const uint16 *gpios, int ngpios)
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{
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int i;
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/* Configure GPIOs */
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for (i = 0; i < ngpios; i++)
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{
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stm32_configgpio(gpios[i]);
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}
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}
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/************************************************************************************
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* Name: stm32_savegpios
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*
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* Description:
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* Save current GPIOs that will used by external memory configurations
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*
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************************************************************************************/
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static void stm32_savegpios(struct extmem_save_s *save)
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{
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DEBUGASSERT(save != NULL);
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save->gpiod_crl = getreg32(STM32_GPIOE_CRL);
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save->gpiod_crh = getreg32(STM32_GPIOE_CRH);
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save->gpioe_crl = getreg32(STM32_GPIOD_CRL);
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save->gpioe_crh = getreg32(STM32_GPIOD_CRH);
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save->gpiof_crl = getreg32(STM32_GPIOF_CRL);
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save->gpiof_crh = getreg32(STM32_GPIOF_CRH);
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save->gpiog_crl = getreg32(STM32_GPIOG_CRL);
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save->gpiog_crh = getreg32(STM32_GPIOG_CRH);
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}
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/************************************************************************************
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* Name: stm32_restoregpios
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*
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* Description:
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* Restore GPIOs that were used by external memory configurations
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*
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************************************************************************************/
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static void stm32_restoregpios(struct extmem_save_s *restore)
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{
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DEBUGASSERT(save != NULL);
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putreg32(restore->gpiod_crl, STM32_GPIOE_CRL);
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putreg32(restore->gpiod_crh, STM32_GPIOE_CRH);
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putreg32(restore->gpioe_crl, STM32_GPIOD_CRL);
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putreg32(restore->gpioe_crh, STM32_GPIOD_CRH);
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putreg32(restore->gpiof_crl, STM32_GPIOF_CRL);
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putreg32(restore->gpiof_crh, STM32_GPIOF_CRH);
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putreg32(restore->gpiog_crl, STM32_GPIOG_CRL);
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putreg32(restore->gpiog_crh, STM32_GPIOG_CRH);
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}
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/************************************************************************************
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* Name: stm32_enableclocks
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*
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* Description:
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* enable clocking to the FSMC module
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*
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************************************************************************************/
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static void stm32_enableclocks(void)
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{
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uint32 regval;
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/* Enable AHB clocking to the FSMC */
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regval = getreg32( STM32_RCC_AHBENR);
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regval |= RCC_AHBENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHBENR);
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}
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/************************************************************************************
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* Name: stm32_disableclocks
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*
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* Description:
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* enable clocking to the FSMC module
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*
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************************************************************************************/
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static void stm32_disableclocks(void)
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{
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uint32 regval;
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/* Enable AHB clocking to the FSMC */
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regval = getreg32( STM32_RCC_AHBENR);
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regval &= ~RCC_AHBENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHBENR);
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}
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/************************************************************************************
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* Name: stm32_selectnor
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*
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* Description:
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* Initialize to access NOR flash
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*
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************************************************************************************/
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void stm32_selectnor(struct extmem_save_s *save)
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{
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/* Save current GPIO state */
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stm32_savegpios(save);
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/* Configure new GPIO state */
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stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
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stm32_extmemgpios(g_sramconfig, NNOR_CONFIG);
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/* Enable AHB clocking to the FSMC */
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stm32_enableclocks();
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/* Bank1 NOR/SRAM control register configuration */
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putreg32(FSMC_BCR2_MTYP1|FSMC_BCR2_FACCEN|FSMC_BCR2_MWID0|FSMC_BCR2_WREN, STM32_FSMC_BCR2);
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/* Bank1 NOR/SRAM timing register configuration */
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putreg32(FSMC_BTR2_ADDSET1|FSMC_BTR2_DATAST0|FSMC_BTR2_DATAST2| FSMC_BTR2_DATLAT0, STM32_FSMC_BTR2);
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putreg32(0x0fffffff, STM32_FSMC_BCR3);
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/* Enable the bank */
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putreg32(FSMC_BCR3_MBKEN|FSMC_BCR2_MTYP1|FSMC_BCR2_FACCEN|FSMC_BCR2_MWID0|FSMC_BCR2_WREN, STM32_FSMC_BCR2);
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}
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/************************************************************************************
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* Name: stm32_deselectnor
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*
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* Description:
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* Disable NOR FLASH
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*
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************************************************************************************/
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void stm32_deselectnor(struct extmem_save_s *restore)
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{
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/* Restore registers to their power up settings */
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||||
|
||||
putreg32(0x000030d2, STM32_FSMC_BCR2);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(0x0fffffff, STM32_FSMC_BTR2);
|
||||
|
||||
/* Disable AHB clocking to the FSMC */
|
||||
|
||||
stm32_disableclocks();
|
||||
|
||||
/* Restore GPIOs */
|
||||
|
||||
stm32_restoregpios(restore);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_selectsram
|
||||
*
|
||||
* Description:
|
||||
* Initialize to access external SRAM
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_selectsram(struct extmem_save_s *save)
|
||||
{
|
||||
/* Save current GPIO state */
|
||||
|
||||
stm32_savegpios(save);
|
||||
|
||||
/* Configure new GPIO state */
|
||||
|
||||
stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
|
||||
stm32_extmemgpios(g_norconfig, NSRAM_CONFIG);
|
||||
|
||||
/* Enable AHB clocking to the FSMC */
|
||||
|
||||
stm32_enableclocks();
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
|
||||
putreg32(FSMC_BCR3_MWID0|FSMC_BCR3_WREN, STM32_FSMC_BCR3);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(FSMC_BCR3_WAITPOL, STM32_FSMC_BTR3);
|
||||
putreg32(0xffffffff, STM32_FSMC_BCR3);
|
||||
|
||||
/* Enable the bank */
|
||||
|
||||
putreg32(FSMC_BCR3_MBKEN|FSMC_BCR3_MWID0|FSMC_BCR3_WREN, STM32_FSMC_BCR3);
|
||||
}
|
||||
/************************************************************************************
|
||||
* Name: stm32_deselectsram
|
||||
*
|
||||
* Description:
|
||||
* Disable NOR FLASH
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_deselectsram(struct extmem_save_s *restore)
|
||||
{
|
||||
/* Restore registers to their power up settings */
|
||||
|
||||
putreg32(0x000030d2, STM32_FSMC_BCR3);
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
|
||||
putreg32(0x0fffffff, STM32_FSMC_BTR3);
|
||||
|
||||
/* Disable AHB clocking to the FSMC */
|
||||
|
||||
stm32_disableclocks();
|
||||
|
||||
/* Restore GPIOs */
|
||||
|
||||
stm32_restoregpios(restore);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user