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mpfs: Modify IRQ handling to support also HART0 on PF

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Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen 2021-05-12 08:37:31 +03:00 committed by Xiang Xiao
parent 8b560e7894
commit 3654db3517
2 changed files with 66 additions and 16 deletions
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69
arch/risc-v/src/mpfs/mpfs_irq.c
View File

@ -69,12 +69,16 @@ void up_irqinitialize(void)
uint64_t hart_id = READ_CSR(mhartid);
/* hart0 is E51 we can't run on that (need different irq handling) */
DEBUGASSERT(hart_id != 0);
uint32_t *miebase = (uint32_t *)(MPFS_PLIC_H1_MIE0 +
(hart_id - 1) * MPFS_HART_MIE_OFFSET);
uint32_t *miebase;
if (hart_id == 0)
{
miebase = (uint32_t *)MPFS_PLIC_H0_MIE0;
}
else
{
miebase = (uint32_t *)(MPFS_PLIC_H1_MIE0 +
(hart_id - 1) * MPFS_HART_MIE_OFFSET);
}
putreg32(0x0, miebase + 0);
putreg32(0x0, miebase + 1);
@ -85,8 +89,17 @@ void up_irqinitialize(void)
/* Clear pendings in PLIC (for current hart) */
uintptr_t claim_address = MPFS_PLIC_H1_MCLAIM +
((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET);
uintptr_t claim_address;
if (hart_id == 0)
{
claim_address = MPFS_PLIC_H0_MCLAIM;
}
else
{
claim_address = MPFS_PLIC_H1_MCLAIM +
((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET);
}
uint32_t val = getreg32(claim_address);
putreg32(val, claim_address);
@ -108,8 +121,18 @@ void up_irqinitialize(void)
/* Set irq threshold to 0 (permits all global interrupts) */
uint32_t *threshold_address = (uint32_t *)(MPFS_PLIC_H1_MTHRESHOLD +
((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET));
uint32_t *threshold_address;
if (hart_id == 0)
{
threshold_address = (uint32_t *)MPFS_PLIC_H0_MTHRESHOLD;
}
else
{
threshold_address = (uint32_t *)(MPFS_PLIC_H1_MTHRESHOLD +
((hart_id - 1) *
MPFS_PLIC_NEXTHART_OFFSET));
}
putreg32(0, threshold_address);
/* currents_regs is non-NULL only while processing an interrupt */
@ -164,8 +187,17 @@ void up_disable_irq(int irq)
/* Clear enable bit for the irq */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t miebase = MPFS_PLIC_H1_MIE0 +
((hart_id - 1) * MPFS_HART_MIE_OFFSET);
uintptr_t miebase;
if (hart_id == 0)
{
miebase = MPFS_PLIC_H0_MIE0;
}
else
{
miebase = MPFS_PLIC_H1_MIE0 +
((hart_id - 1) * MPFS_HART_MIE_OFFSET);
}
if (0 <= extirq && extirq <= NR_IRQS - MPFS_IRQ_EXT_START)
{
@ -210,8 +242,17 @@ void up_enable_irq(int irq)
/* Set enable bit for the irq */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t miebase = MPFS_PLIC_H1_MIE0 +
((hart_id - 1) * MPFS_HART_MIE_OFFSET);
uintptr_t miebase;
if (hart_id == 0)
{
miebase = MPFS_PLIC_H0_MIE0;
}
else
{
miebase = MPFS_PLIC_H1_MIE0 +
((hart_id - 1) * MPFS_HART_MIE_OFFSET);
}
if (0 <= extirq && extirq <= NR_IRQS - MPFS_IRQ_EXT_START)
{

13
arch/risc-v/src/mpfs/mpfs_irq_dispatch.c
View File

@ -79,8 +79,17 @@ void *mpfs_dispatch_irq(uint64_t vector, uint64_t *regs)
/* Firstly, check if the irq is machine external interrupt */
uint64_t hart_id = READ_CSR(mhartid);
uintptr_t claim_address = MPFS_PLIC_H1_MCLAIM +
((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET);
uintptr_t claim_address;
if (hart_id == 0)
{
claim_address = MPFS_PLIC_H0_MCLAIM;
}
else
{
claim_address = MPFS_PLIC_H1_MCLAIM +
((hart_id - 1) * MPFS_PLIC_NEXTHART_OFFSET);
}
if (irq == MPFS_IRQ_MEXT)
{