xtensa/esp32s3: Add DMA support to SPI
This commit is contained in:
Alan Carvalho de Assis
Gustavo Henrique Nihei
parent
1cb3c0d630
commit
368d65459c
@ -581,6 +581,29 @@ config ESP32S3_SPI_UDCS
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if ESP32S3_SPI2
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config ESP32S3_SPI2_DMA
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bool "SPI2 use GDMA"
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default n
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depends on ESP32S3_DMA
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---help---
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Enable support for transfers using the GDMA engine.
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config ESP32S3_SPI2_DMADESC_NUM
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int "SPI2 Master GDMA maximum number of descriptors"
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default 2
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depends on ESP32S3_SPI2_DMA
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---help---
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Configure the maximum number of out-link/in-link descriptors to
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be chained for a GDMA transfer.
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config ESP32S3_SPI2_DMATHRESHOLD
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int "SPI2 Master GDMA threshold"
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default 64
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depends on ESP32S3_SPI2_DMA
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---help---
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When SPI GDMA is enabled, GDMA transfers whose size are below the
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defined threshold will be performed by polling logic.
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config ESP32S3_SPI2_CSPIN
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int "SPI2 CS Pin"
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default 10
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@ -48,6 +48,10 @@
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#include "esp32s3_irq.h"
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#include "esp32s3_gpio.h"
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#include "esp32s3_dma.h"
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#endif
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#include "xtensa.h"
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#include "hardware/esp32s3_gpio_sigmap.h"
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#include "hardware/esp32s3_pinmap.h"
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@ -67,6 +71,18 @@
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# define SPI_HAVE_SWCS 0
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#endif
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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/* SPI DMA RX/TX number of descriptors */
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#define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI2_DMADESC_NUM)
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/* SPI DMA reset before exchange */
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#define SPI_DMA_RESET_MASK (SPI_DMA_AFIFO_RST_M | SPI_RX_AFIFO_RST_M)
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#endif
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/* SPI default frequency (limited by clock divider) */
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#define SPI_DEFAULT_FREQ (400000)
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@ -111,8 +127,16 @@ struct esp32s3_spi_config_s
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uint8_t mosi_pin; /* GPIO configuration for MOSI */
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uint8_t miso_pin; /* GPIO configuration for MISO */
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uint8_t clk_pin; /* GPIO configuration for CLK */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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uint8_t periph; /* Peripheral ID */
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uint8_t irq; /* Interrupt ID */
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#endif
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uint32_t clk_bit; /* Clock enable bit */
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uint32_t rst_bit; /* SPI reset bit */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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uint32_t dma_clk_bit; /* DMA clock enable bit */
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uint32_t dma_rst_bit; /* DMA reset bit */
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#endif
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uint32_t cs_insig; /* SPI CS input signal index */
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uint32_t cs_outsig; /* SPI CS output signal index */
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uint32_t mosi_insig; /* SPI MOSI input signal index */
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@ -134,6 +158,12 @@ struct esp32s3_spi_priv_s
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const struct esp32s3_spi_config_s *config;
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int refs; /* Reference count */
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sem_t exclsem; /* Held while chip is selected for mutual exclusion */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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sem_t sem_isr; /* Interrupt wait semaphore */
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int cpu; /* CPU ID */
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int cpuint; /* SPI interrupt ID */
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int32_t dma_channel; /* Channel assigned by the GDMA driver */
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#endif
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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enum spi_mode_e mode; /* Actual SPI hardware mode */
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@ -163,10 +193,19 @@ static uint32_t esp32s3_spi_send(struct spi_dev_s *dev, uint32_t wd);
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static void esp32s3_spi_exchange(struct spi_dev_s *dev,
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const void *txbuffer,
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void *rxbuffer, size_t nwords);
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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static int esp32s3_spi_interrupt(int irq, void *context, void *arg);
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static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv);
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static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
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const void *txbuffer,
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void *rxbuffer,
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uint32_t nwords);
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#else
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static void esp32s3_spi_poll_exchange(struct esp32s3_spi_priv_s *priv,
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const void *txbuffer,
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void *rxbuffer,
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size_t nwords);
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#endif
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#ifndef CONFIG_SPI_EXCHANGE
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static void esp32s3_spi_sndblock(struct spi_dev_s *dev,
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const void *txbuffer,
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@ -178,6 +217,9 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev,
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#ifdef CONFIG_SPI_TRIGGER
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static int esp32s3_spi_trigger(struct spi_dev_s *dev);
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#endif
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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static void esp32s3_spi_dma_init(struct spi_dev_s *dev);
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#endif
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static void esp32s3_spi_init(struct spi_dev_s *dev);
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static void esp32s3_spi_deinit(struct spi_dev_s *dev);
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@ -196,8 +238,16 @@ static const struct esp32s3_spi_config_s esp32s3_spi2_config =
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.mosi_pin = CONFIG_ESP32S3_SPI2_MOSIPIN,
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.miso_pin = CONFIG_ESP32S3_SPI2_MISOPIN,
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.clk_pin = CONFIG_ESP32S3_SPI2_CLKPIN,
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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.periph = ESP32S3_PERIPH_SPI2,
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.irq = ESP32S3_IRQ_SPI2,
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#endif
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.clk_bit = SYSTEM_SPI2_CLK_EN,
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.rst_bit = SYSTEM_SPI2_RST,
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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.dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN,
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.dma_rst_bit = SYSTEM_SPI2_DMA_RST,
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#endif
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.cs_insig = FSPICS0_IN_IDX,
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.cs_outsig = FSPICS0_OUT_IDX,
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.mosi_insig = FSPID_IN_IDX,
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@ -248,6 +298,11 @@ static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
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.config = &esp32s3_spi2_config,
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.refs = 0,
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.exclsem = SEM_INITIALIZER(0),
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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.sem_isr = SEM_INITIALIZER(0),
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.cpuint = -ENOMEM,
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.dma_channel = -1,
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#endif
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.frequency = 0,
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.actual = 0,
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.mode = 0,
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@ -325,6 +380,15 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
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};
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#endif /* CONFIG_ESP32S3_SPI3 */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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/* SPI DMA RX/TX description */
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static struct esp32s3_dmadesc_s dma_rxdesc[SPI_DMA_DESC_NUM];
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static struct esp32s3_dmadesc_s dma_txdesc[SPI_DMA_DESC_NUM];
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#endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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@ -442,6 +506,37 @@ static int esp32s3_spi_lock(struct spi_dev_s *dev, bool lock)
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return ret;
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}
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/****************************************************************************
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* Name: esp32s3_spi_sem_waitdone
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*
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* Description:
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* Wait for a transfer to complete.
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*
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* Input Parameters:
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* priv - SPI private state data
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv)
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{
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int ret;
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struct timespec abstime;
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clock_gettime(CLOCK_REALTIME, &abstime);
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abstime.tv_sec += 10;
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abstime.tv_nsec += 0;
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ret = nxsem_timedwait_uninterruptible(&priv->sem_isr, &abstime);
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return ret;
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}
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#endif
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/****************************************************************************
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* Name: esp32s3_spi_select
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*
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@ -723,6 +818,115 @@ static int esp32s3_spi_hwfeatures(struct spi_dev_s *dev,
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}
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#endif
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/****************************************************************************
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* Name: esp32s3_spi_dma_exchange
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*
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* Description:
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* Exchange a block of data from SPI by DMA.
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*
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* Input Parameters:
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* priv - SPI private state data
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* txbuffer - A pointer to the buffer of data to be sent
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* rxbuffer - A pointer to the buffer in which to receive data
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* nwords - the length of data that to be exchanged in units of words.
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* The wordsize is determined by the number of bits-per-word
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* selected for the SPI interface. If nbits <= 8, the data is
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* packed into uint8_t's; if nbits >8, the data is packed into
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* uint16_t's
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
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const void *txbuffer,
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void *rxbuffer,
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uint32_t nwords)
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{
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const uint32_t total = nwords * (priv->nbits / 8);
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const int32_t channel = priv->dma_channel;
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uint32_t bytes = total;
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uint32_t n;
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uint8_t *tp;
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uint8_t *rp;
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DEBUGASSERT((txbuffer != NULL) || (rxbuffer != NULL));
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spiinfo("nwords=%" PRIu32 "\n", nwords);
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tp = (uint8_t *)txbuffer;
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rp = (uint8_t *)rxbuffer;
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if (tp == NULL)
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{
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tp = rp;
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}
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esp32s3_spi_clr_regbits(SPI_DMA_INT_RAW_REG(2), SPI_TRANS_DONE_INT_RAW_M);
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esp32s3_spi_set_regbits(SPI_DMA_INT_ENA_REG(2), SPI_TRANS_DONE_INT_ENA_M);
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while (bytes != 0)
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{
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/* Reset SPI DMA TX FIFO */
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esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(2), SPI_DMA_RESET_MASK);
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esp32s3_spi_clr_regbits(SPI_DMA_CONF_REG(2), SPI_DMA_RESET_MASK);
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/* Enable SPI DMA TX */
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esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(2), SPI_DMA_TX_ENA_M);
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n = esp32s3_dma_setup(channel, true, dma_txdesc, SPI_DMA_DESC_NUM,
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tp, bytes);
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esp32s3_dma_enable(channel, true);
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putreg32((n * 8 - 1), SPI_MS_DLEN_REG(2));
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esp32s3_spi_set_regbits(SPI_USER_REG(2), SPI_USR_MOSI_M);
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tp += n;
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if (rp != NULL)
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{
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/* Enable SPI DMA RX */
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esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(2), SPI_DMA_RX_ENA_M);
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esp32s3_dma_setup(channel, false, dma_rxdesc, SPI_DMA_DESC_NUM,
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rp, bytes);
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esp32s3_dma_enable(channel, false);
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esp32s3_spi_set_regbits(SPI_USER_REG(2), SPI_USR_MISO_M);
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rp += n;
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}
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else
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{
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esp32s3_spi_clr_regbits(SPI_USER_REG(2), SPI_USR_MISO_M);
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}
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/* Trigger start of user-defined transaction for master. */
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esp32s3_spi_set_regbits(SPI_CMD_REG(2), SPI_UPDATE_M);
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while ((getreg32(SPI_CMD_REG(2)) & SPI_UPDATE_M) != 0)
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{
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;
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}
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esp32s3_spi_set_regbits(SPI_CMD_REG(2), SPI_USR_M);
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esp32s3_spi_sem_waitdone(priv);
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bytes -= n;
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}
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esp32s3_spi_clr_regbits(SPI_DMA_INT_ENA_REG(2), SPI_TRANS_DONE_INT_ENA_M);
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}
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#endif
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/****************************************************************************
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* Name: esp32s3_spi_poll_send
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*
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@ -958,7 +1162,18 @@ static void esp32s3_spi_exchange(struct spi_dev_s *dev,
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{
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struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
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esp32s3_spi_poll_exchange(priv, txbuffer, rxbuffer, nwords);
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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size_t thld = CONFIG_ESP32S3_SPI2_DMATHRESHOLD;
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if (nwords > thld)
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{
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esp32s3_spi_dma_exchange(priv, txbuffer, rxbuffer, nwords);
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}
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else
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#endif
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{
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esp32s3_spi_poll_exchange(priv, txbuffer, rxbuffer, nwords);
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}
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}
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#ifndef CONFIG_SPI_EXCHANGE
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@ -1022,6 +1237,78 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev,
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}
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#endif
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/****************************************************************************
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* Name: esp32s3_spi_trigger
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*
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* Description:
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* Trigger a previously configured DMA transfer.
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*
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* Input Parameters:
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* dev - Device-specific state data
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*
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* Returned Value:
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* OK - Trigger was fired
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* -ENOSYS - Trigger not fired due to lack of DMA or low level support
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* -EIO - Trigger not fired because not previously primed
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*
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****************************************************************************/
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#ifdef CONFIG_SPI_TRIGGER
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static int esp32s3_spi_trigger(struct spi_dev_s *dev)
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{
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return -ENOSYS;
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}
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#endif
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/****************************************************************************
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* Name: esp32s3_spi_dma_init
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*
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* Description:
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* Initialize ESP32-S3 SPI connection to GDMA engine.
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*
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* Input Parameters:
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* dev - Device-specific state data
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*
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* Returned Value:
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* None.
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*
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****************************************************************************/
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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void esp32s3_spi_dma_init(struct spi_dev_s *dev)
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{
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struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
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/* Enable GDMA clock for the SPI peripheral */
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modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, priv->config->dma_clk_bit);
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/* Reset GDMA for the SPI peripheral */
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modifyreg32(SYSTEM_PERIP_RST_EN0_REG, priv->config->dma_rst_bit, 0);
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/* Initialize GDMA controller */
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esp32s3_dma_init();
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/* Request a GDMA channel for SPI peripheral */
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priv->dma_channel = esp32s3_dma_request(ESP32S3_DMA_PERIPH_SPI2, 1, 1,
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true);
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if (priv->dma_channel < 0)
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{
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spierr("Failed to allocate GDMA channel\n");
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DEBUGASSERT(false);
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}
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/* Disable segment transaction mode for SPI Master */
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putreg32((SPI_SLV_RX_SEG_TRANS_CLR_EN_M | SPI_SLV_TX_SEG_TRANS_CLR_EN_M),
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SPI_DMA_CONF_REG(2));
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}
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#endif
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/****************************************************************************
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* Name: esp32s3_spi_init
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*
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@ -1110,6 +1397,13 @@ static void esp32s3_spi_init(struct spi_dev_s *dev)
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putreg32(VALUE_MASK(0, SPI_CS_HOLD_TIME),
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SPI_USER1_REG(priv->config->id));
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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nxsem_init(&priv->sem_isr, 0, 0);
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nxsem_set_protocol(&priv->sem_isr, SEM_PRIO_NONE);
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esp32s3_spi_dma_init(dev);
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#endif
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esp32s3_spi_setfrequency(dev, config->clk_freq);
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esp32s3_spi_setbits(dev, config->width);
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esp32s3_spi_setmode(dev, config->mode);
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@ -1133,6 +1427,10 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
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{
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struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0);
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#endif
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modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, priv->config->clk_bit);
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modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->clk_bit, 0);
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@ -1142,6 +1440,34 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
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priv->nbits = 0;
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}
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/****************************************************************************
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* Name: esp32s3_spi_interrupt
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*
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* Description:
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* Common SPI DMA interrupt handler.
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*
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* Input Parameters:
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* irq - Number of the IRQ that generated the interrupt
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* context - Interrupt register state save info
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* arg - SPI controller private data
|
||||
*
|
||||
* Returned Value:
|
||||
* Standard interrupt return value.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
static int esp32s3_spi_interrupt(int irq, void *context, void *arg)
|
||||
{
|
||||
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)arg;
|
||||
|
||||
esp32s3_spi_clr_regbits(SPI_DMA_INT_RAW_REG(2), SPI_TRANS_DONE_INT_RAW_M);
|
||||
nxsem_post(&priv->sem_isr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: esp32s3_spibus_initialize
|
||||
*
|
||||
@ -1189,6 +1515,54 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port)
|
||||
return spi_dev;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
/* If a CPU Interrupt was previously allocated, then deallocate it */
|
||||
|
||||
if (priv->cpuint != -ENOMEM)
|
||||
{
|
||||
/* Disable the provided CPU Interrupt to configure it. */
|
||||
|
||||
up_disable_irq(priv->config->irq);
|
||||
esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
|
||||
irq_detach(priv->config->irq);
|
||||
|
||||
priv->cpuint = -ENOMEM;
|
||||
priv->cpu = -ENODEV;
|
||||
}
|
||||
|
||||
/* Set up to receive peripheral interrupts on the current CPU */
|
||||
|
||||
priv->cpu = up_cpu_index();
|
||||
priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->config->periph,
|
||||
ESP32S3_INT_PRIO_DEF,
|
||||
ESP32S3_CPUINT_LEVEL);
|
||||
if (priv->cpuint < 0)
|
||||
{
|
||||
/* Failed to allocate a CPU interrupt of this type. */
|
||||
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Attach and enable the IRQ */
|
||||
|
||||
if (irq_attach(priv->config->irq, esp32s3_spi_interrupt, priv) != OK)
|
||||
{
|
||||
/* Failed to attach IRQ, so CPU interrupt must be freed. */
|
||||
|
||||
esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
|
||||
priv->cpuint = -ENOMEM;
|
||||
spin_unlock_irqrestore(&priv->lock, flags);
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/* Enable the CPU interrupt that is linked to the SPI device. */
|
||||
|
||||
up_enable_irq(priv->config->irq);
|
||||
#endif
|
||||
|
||||
esp32s3_spi_init(spi_dev);
|
||||
|
||||
priv->refs++;
|
||||
@ -1234,6 +1608,16 @@ int esp32s3_spibus_uninitialize(struct spi_dev_s *dev)
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
up_disable_irq(priv->config->irq);
|
||||
esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
|
||||
irq_detach(priv->config->irq);
|
||||
|
||||
priv->cpuint = -ENOMEM;
|
||||
|
||||
nxsem_destroy(&priv->sem_isr);
|
||||
#endif
|
||||
|
||||
esp32s3_spi_deinit(dev);
|
||||
|
||||
nxsem_destroy(&priv->exclsem);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user