diff --git a/arch/risc-v/include/arch.h b/arch/risc-v/include/arch.h
index 92b1f66679..1a71fd5371 100644
--- a/arch/risc-v/include/arch.h
+++ b/arch/risc-v/include/arch.h
@@ -35,8 +35,6 @@
 #  include <stdint.h>
 #endif
 
-#include <arch/csr.h>
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
diff --git a/arch/risc-v/include/csr.h b/arch/risc-v/include/csr.h
index a5cb948b0c..25b6316943 100644
--- a/arch/risc-v/include/csr.h
+++ b/arch/risc-v/include/csr.h
@@ -325,37 +325,6 @@
 
 #define MIP_MTIP      (0x1 << 7)
 
-#define CSR_STR(csr) #csr
-
-#define READ_CSR(reg) \
-  ({ \
-     unsigned long tmp; \
-     asm volatile("csrr %0, " CSR_STR(reg) : "=r"(tmp)); \
-     tmp; \
-  })
-
-#define READ_AND_SET_CSR(reg, bits) \
-  ({ \
-     unsigned long tmp; \
-     asm volatile("csrrs %0, " CSR_STR(reg) ", %1": "=r"(tmp) : "rK"(bits)); \
-     tmp; \
-  })
-
-#define WRITE_CSR(reg, val) \
-  ({ \
-     asm volatile("csrw " CSR_STR(reg) ", %0" :: "rK"(val)); \
-  })
-
-#define SET_CSR(reg, bits) \
-  ({ \
-     asm volatile("csrs " CSR_STR(reg) ", %0" :: "rK"(bits)); \
-  })
-
-#define CLEAR_CSR(reg, bits) \
-  ({ \
-     asm volatile("csrc " CSR_STR(reg) ", %0" :: "rK"(bits)); \
-  })
-
 /* In pmpcfg (PMP configuration) register */
 
 #define PMPCFG_R        (1 << 0)  /* readable ? */
diff --git a/arch/risc-v/include/irq.h b/arch/risc-v/include/irq.h
index 4ae804c5b9..21c5f8bd81 100644
--- a/arch/risc-v/include/irq.h
+++ b/arch/risc-v/include/irq.h
@@ -32,14 +32,12 @@
 /* Include chip-specific IRQ definitions (including IRQ numbers) */
 
 #include <nuttx/config.h>
+
 #include <arch/types.h>
 
-#ifndef __ASSEMBLY__
-#include <stdint.h>
 #include <nuttx/irq.h>
 #include <arch/csr.h>
 #include <arch/chip/irq.h>
-#endif
 
 /****************************************************************************
  * Pre-processor Definitions
diff --git a/arch/risc-v/src/bl602/bl602_head.S b/arch/risc-v/src/bl602/bl602_head.S
index 0b2983d1dc..758304c16c 100644
--- a/arch/risc-v/src/bl602/bl602_head.S
+++ b/arch/risc-v/src/bl602/bl602_head.S
@@ -23,7 +23,7 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
     .section .init
     .globl bl602_start
diff --git a/arch/risc-v/src/bl602/bl602_irq.c b/arch/risc-v/src/bl602/bl602_irq.c
index 09472a4a8b..7332fd53ba 100644
--- a/arch/risc-v/src/bl602/bl602_irq.c
+++ b/arch/risc-v/src/bl602/bl602_irq.c
@@ -31,9 +31,8 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
-#include <arch/irq.h>
+#include <nuttx/irq.h>
 #include <arch/board/board.h>
-#include <arch/csr.h>
 
 #include "riscv_internal.h"
 #include "hardware/bl602_clic.h"
diff --git a/arch/risc-v/src/c906/c906_head.S b/arch/risc-v/src/c906/c906_head.S
index 22c5a5d838..a5ad86eadc 100644
--- a/arch/risc-v/src/c906/c906_head.S
+++ b/arch/risc-v/src/c906/c906_head.S
@@ -23,8 +23,8 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include <arch/csr.h>
-#include <arch/irq.h>
+
+#include <nuttx/irq.h>
 
 #include "chip.h"
 #include "c906_memorymap.h"
diff --git a/arch/risc-v/src/c906/c906_irq.c b/arch/risc-v/src/c906/c906_irq.c
index c7059be753..6e68d5aeb8 100644
--- a/arch/risc-v/src/c906/c906_irq.c
+++ b/arch/risc-v/src/c906/c906_irq.c
@@ -30,8 +30,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
-#include <arch/irq.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 #include "c906.h"
diff --git a/arch/risc-v/src/common/riscv_cpuindex.c b/arch/risc-v/src/common/riscv_cpuindex.c
index fbf4e9face..45e252f0ce 100644
--- a/arch/risc-v/src/common/riscv_cpuindex.c
+++ b/arch/risc-v/src/common/riscv_cpuindex.c
@@ -23,10 +23,11 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include <stdint.h>
-#include <nuttx/arch.h>
 
-#include <arch/csr.h>
+#include <stdint.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 
diff --git a/arch/risc-v/src/common/riscv_exception.c b/arch/risc-v/src/common/riscv_exception.c
index 1ffb3e2a1a..5be6b3331e 100644
--- a/arch/risc-v/src/common/riscv_exception.c
+++ b/arch/risc-v/src/common/riscv_exception.c
@@ -33,7 +33,6 @@
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
 #include <nuttx/syslog/syslog.h>
-#include <arch/irq.h>
 
 #include "riscv_internal.h"
 
diff --git a/arch/risc-v/src/common/riscv_getnewintctx.c b/arch/risc-v/src/common/riscv_getnewintctx.c
index 04180f7abb..6b7619a18b 100644
--- a/arch/risc-v/src/common/riscv_getnewintctx.c
+++ b/arch/risc-v/src/common/riscv_getnewintctx.c
@@ -30,8 +30,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
-#include <arch/irq.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 
diff --git a/arch/risc-v/src/common/riscv_internal.h b/arch/risc-v/src/common/riscv_internal.h
index c25a07a606..3bd0542e51 100644
--- a/arch/risc-v/src/common/riscv_internal.h
+++ b/arch/risc-v/src/common/riscv_internal.h
@@ -134,6 +134,8 @@
 #define PMP_ACCESS_DENIED   (-1)    /* Access set and denied */
 #define PMP_ACCESS_FULL     (1)     /* Access set and allowed */
 
+#ifndef __ASSEMBLY__
+
 #define getreg8(a)          (*(volatile uint8_t *)(a))
 #define putreg8(v,a)        (*(volatile uint8_t *)(a) = (v))
 #define getreg16(a)         (*(volatile uint16_t *)(a))
@@ -143,6 +145,37 @@
 #define getreg64(a)         (*(volatile uint64_t *)(a))
 #define putreg64(v,a)       (*(volatile uint64_t *)(a) = (v))
 
+#define READ_CSR(reg) \
+  ({ \
+     uintptr_t reg##_val; \
+     __asm__ __volatile__("csrr %0, " __STR(reg) : "=r"(reg##_val)); \
+     reg##_val; \
+  })
+
+#define READ_AND_SET_CSR(reg, bits) \
+  ({ \
+     uintptr_t reg##_val; \
+     __asm__ __volatile__("csrrs %0, " __STR(reg) ", %1": "=r"(reg##_val) : "rK"(bits)); \
+     reg##_val; \
+  })
+
+#define WRITE_CSR(reg, val) \
+  ({ \
+     __asm__ __volatile__("csrw " __STR(reg) ", %0" :: "rK"(val)); \
+  })
+
+#define SET_CSR(reg, bits) \
+  ({ \
+     __asm__ __volatile__("csrs " __STR(reg) ", %0" :: "rK"(bits)); \
+  })
+
+#define CLEAR_CSR(reg, bits) \
+  ({ \
+     __asm__ __volatile__("csrc " __STR(reg) ", %0" :: "rK"(bits)); \
+  })
+
+#endif
+
 /****************************************************************************
  * Public Types
  ****************************************************************************/
diff --git a/arch/risc-v/src/common/riscv_mmu.c b/arch/risc-v/src/common/riscv_mmu.c
index 4d92de0012..20c8f75697 100644
--- a/arch/risc-v/src/common/riscv_mmu.c
+++ b/arch/risc-v/src/common/riscv_mmu.c
@@ -26,7 +26,7 @@
 
 #include <nuttx/config.h>
 #include <nuttx/arch.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 #include "riscv_mmu.h"
diff --git a/arch/risc-v/src/common/riscv_pmp.c b/arch/risc-v/src/common/riscv_pmp.c
index afa6a5e95f..cf7dc028de 100644
--- a/arch/risc-v/src/common/riscv_pmp.c
+++ b/arch/risc-v/src/common/riscv_pmp.c
@@ -22,13 +22,14 @@
  * Included Files
  ****************************************************************************/
 
+#include <nuttx/config.h>
+
 #include <stdint.h>
 #include <stdbool.h>
 
 #include <nuttx/compiler.h>
-#include <nuttx/config.h>
 #include <nuttx/arch.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 
@@ -70,10 +71,10 @@
 
 #define PMP_READ_REGION_FROM_REG(region, reg) \
   ({ \
-    uintptr_t tmp = READ_CSR(reg); \
-    tmp >>= ((region % PMP_CFG_CNT_IN_REG) * PMP_CFG_BITS_CNT); \
-    tmp &= PMP_CFG_FLAG_MASK; \
-    tmp; \
+    uintptr_t region##_val = READ_CSR(reg); \
+    region##_val >>= ((region % PMP_CFG_CNT_IN_REG) * PMP_CFG_BITS_CNT); \
+    region##_val &= PMP_CFG_FLAG_MASK; \
+    region##_val; \
   })
 
 #ifndef min
diff --git a/arch/risc-v/src/esp32c3/esp32c3_irq.c b/arch/risc-v/src/esp32c3/esp32c3_irq.c
index f52cb0b0e7..e5e8d61812 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_irq.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_irq.c
@@ -24,6 +24,7 @@
 
 #include <nuttx/config.h>
 
+#include <stdint.h>
 #include <assert.h>
 #include <errno.h>
 #include <debug.h>
@@ -33,10 +34,6 @@
 #include <nuttx/board.h>
 #include <arch/board/board.h>
 
-#include <arch/irq.h>
-#include <arch/csr.h>
-#include <stdint.h>
-
 #include "riscv_internal.h"
 #include "hardware/esp32c3_interrupt.h"
 #include "rom/esp32c3_spiflash.h"
diff --git a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c
index 321d196e36..42483bdac7 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c
+++ b/arch/risc-v/src/esp32c3/esp32c3_wifi_adapter.c
@@ -50,10 +50,14 @@
 #include <nuttx/signal.h>
 #include <nuttx/arch.h>
 #include <nuttx/wireless/wireless.h>
+
+#include "riscv_internal.h"
+
 #include "hardware/esp32c3_system.h"
 #include "hardware/wdev_reg.h"
 #include "hardware/esp32c3_rtccntl.h"
 #include "hardware/esp32c3_syscon.h"
+
 #include "esp32c3.h"
 #include "esp32c3_attr.h"
 #include "esp32c3_irq.h"
diff --git a/arch/risc-v/src/fe310/fe310_irq.c b/arch/risc-v/src/fe310/fe310_irq.c
index 1a44ccf4bb..50304f6226 100644
--- a/arch/risc-v/src/fe310/fe310_irq.c
+++ b/arch/risc-v/src/fe310/fe310_irq.c
@@ -31,9 +31,8 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
-#include <arch/irq.h>
+#include <nuttx/irq.h>
 #include <arch/board/board.h>
-#include <arch/csr.h>
 
 #include "riscv_internal.h"
 #include "fe310.h"
diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c
index b01ee914fd..618b4d5abe 100644
--- a/arch/risc-v/src/k210/k210_irq.c
+++ b/arch/risc-v/src/k210/k210_irq.c
@@ -30,8 +30,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
-#include <arch/irq.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 #include "k210.h"
diff --git a/arch/risc-v/src/litex/litex_irq.c b/arch/risc-v/src/litex/litex_irq.c
index 7f8978f0bd..517be49a00 100644
--- a/arch/risc-v/src/litex/litex_irq.c
+++ b/arch/risc-v/src/litex/litex_irq.c
@@ -31,9 +31,8 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
-#include <arch/irq.h>
+#include <nuttx/irq.h>
 #include <arch/board/board.h>
-#include <arch/csr.h>
 
 #include "riscv_internal.h"
 #include "litex.h"
diff --git a/arch/risc-v/src/mpfs/mpfs_head.S b/arch/risc-v/src/mpfs/mpfs_head.S
index ffaad62752..e375dce060 100755
--- a/arch/risc-v/src/mpfs/mpfs_head.S
+++ b/arch/risc-v/src/mpfs/mpfs_head.S
@@ -23,8 +23,8 @@
  ****************************************************************************/
 
 #include <nuttx/config.h>
-#include <arch/csr.h>
-#include <arch/irq.h>
+
+#include <nuttx/irq.h>
 
 #include "chip.h"
 #include "mpfs_memorymap.h"
diff --git a/arch/risc-v/src/mpfs/mpfs_irq.c b/arch/risc-v/src/mpfs/mpfs_irq.c
index c99574a77a..3657f4f901 100755
--- a/arch/risc-v/src/mpfs/mpfs_irq.c
+++ b/arch/risc-v/src/mpfs/mpfs_irq.c
@@ -30,8 +30,7 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
-#include <arch/irq.h>
-#include <arch/csr.h>
+#include <nuttx/irq.h>
 
 #include "riscv_internal.h"
 #include "mpfs.h"
diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
index 36c4e89d41..9a3a704509 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
@@ -31,9 +31,8 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
-#include <arch/irq.h>
+#include <nuttx/irq.h>
 #include <arch/board/board.h>
-#include <arch/csr.h>
 
 #include "riscv_internal.h"
 #include "chip.h"
diff --git a/arch/risc-v/src/rv32m1/rv32m1_irq.c b/arch/risc-v/src/rv32m1/rv32m1_irq.c
index 2dc5d13e79..5ea59733ea 100644
--- a/arch/risc-v/src/rv32m1/rv32m1_irq.c
+++ b/arch/risc-v/src/rv32m1/rv32m1_irq.c
@@ -30,9 +30,8 @@
 
 #include <nuttx/arch.h>
 #include <nuttx/board.h>
-#include <arch/irq.h>
+#include <nuttx/irq.h>
 #include <arch/board/board.h>
-#include <arch/csr.h>
 
 #include "riscv_internal.h"
 #include "rv32m1.h"