More STM3240 header file changes
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4109 42af7a65-404d-4744-a932-0658087f49c3
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@ -2,7 +2,7 @@
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* arch/arm/src/stm32/chip/stm32_flash.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -40,18 +40,21 @@
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* Pre-processor Definitions
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************************************************************************************/
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#ifdef CONFIG_STM32_LOWDENSITY
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#ifdef defined(CONFIG_STM32_LOWDENSITY)
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# define STM32_FLASH_NPAGES 32
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# define STM32_FLASH_PAGESIZE 1024
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#elif CONFIG_STM32_MEDIUMDENSITY
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#elif defined(CONFIG_STM32_MEDIUMDENSITY)
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# define STM32_FLASH_NPAGES 128
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# define STM32_FLASH_PAGESIZE 1024
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#elif CONFIG_STM32_CONNECTIVITYLINE
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#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
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# define STM32_FLASH_NPAGES 128
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# define STM32_FLASH_PAGESIZE 2048
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#elif CONFIG_STM32_HIGHDENSITY
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#elif defined(CONFIG_STM32_HIGHDENSITY)
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# define STM32_FLASH_NPAGES 256
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# define STM32_FLASH_PAGESIZE 2048
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_NPAGES 8
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# define CONFIG_STM32_STM32F40XX (128*1024)
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#endif
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#define STM32_FLASH_SIZE (STM32_FLASH_NPAGES * STM32_FLASH_PAGESIZE)
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@ -63,9 +66,14 @@
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#define STM32_FLASH_OPTKEYR_OFFSET 0x0008
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#define STM32_FLASH_SR_OFFSET 0x000c
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#define STM32_FLASH_CR_OFFSET 0x0010
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#define STM32_FLASH_AR_OFFSET 0x0014
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#define STM32_FLASH_OBR_OFFSET 0x001c
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#define STM32_FLASH_WRPR_OFFSET 0x0020
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#if defined(CONFIG_STM32_STM32F10XX)
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# define STM32_FLASH_AR_OFFSET 0x0014
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# define STM32_FLASH_OBR_OFFSET 0x001c
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# define STM32_FLASH_WRPR_OFFSET 0x0020
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_OPTCR_OFFSET 0x0014
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#endif
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/* Register Addresses ***************************************************************/
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@ -74,42 +82,109 @@
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#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET)
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#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET)
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#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET)
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#define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
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#define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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#define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
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#if defined(CONFIG_STM32_STM32F10XX)
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# define STM32_FLASH_AR (STM32_FLASHIF_BASE+STM32_FLASH_AR_OFFSET)
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# define STM32_FLASH_OBR (STM32_FLASHIF_BASE+STM32_FLASH_OBR_OFFSET)
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# define STM32_FLASH_WRPR (STM32_FLASHIF_BASE+STM32_FLASH_WRPR_OFFSET)
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* TODO: Complete FLASH details from the STM32F10xxx Flash programming manual. */
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/* Flash Status Register (SR) */
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#define FLASH_SR_BSY (1 << 0) /* Busy */
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#define FLASH_SR_PGERR (1 << 2) /* Programming Error */
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#define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
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#define FLASH_SR_EOP (1 << 5) /* End of Operation */
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/* Flash Control Register (CR) */
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#define FLASH_CR_PG (1 << 0) /* Program Page */
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#define FLASH_CR_PER (1 << 1) /* Page Erase */
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#define FLASH_CR_MER (1 << 2) /* Mass Erase */
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#define FLASH_CR_OPTPG (1 << 4) /* Option Byte Programming */
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#define FLASH_CR_OPTER (1 << 5) /* Option Byte Erase */
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#define FLASH_CR_STRT (1 << 6) /* Start Erase */
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#define FLASH_CR_LOCK (1 << 7) /* Page Locked or Lock Page */
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#define FLASH_CR_OPTWRE (1 << 9) /* Option Bytes Write Enable */
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#define FLASH_CR_ERRIE (1 << 10) /* Error Interrupt Enable */
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#define FLASH_CR_EOPIE (1 << 12) /* End of Program Interrupt Enable */
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/* Flash Access Control Register (ACR) */
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#define FLASH_ACR_LATENCY_SHIFT (0)
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#define FLASH_ACR_LATENCY_MASK (7 << FLASH_ACR_LATENCY_SHIFT)
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# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* FLASH Zero Latency cycle */
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# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* FLASH One Latency cycle */
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# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* FLASH Two Latency cycles */
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#define FLASH_ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
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#define FLASH_ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
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# define FLASH_ACR_LATENCY(n) ((n) << FLASH_ACR_LATENCY_SHIFT) /* n wait states */
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# define FLASH_ACR_LATENCY_0 (0 << FLASH_ACR_LATENCY_SHIFT) /* 000: Zero wait states */
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# define FLASH_ACR_LATENCY_1 (1 << FLASH_ACR_LATENCY_SHIFT) /* 001: One wait state */
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# define FLASH_ACR_LATENCY_2 (2 << FLASH_ACR_LATENCY_SHIFT) /* 010: Two wait states */
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# define FLASH_ACR_LATENCY_3 (3 << FLASH_ACR_LATENCY_SHIFT) /* 011: Three wait states */
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# define FLASH_ACR_LATENCY_4 (4 << FLASH_ACR_LATENCY_SHIFT) /* 100: Four wait states */
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# define FLASH_ACR_LATENCY_5 (5 << FLASH_ACR_LATENCY_SHIFT) /* 101: Five wait states */
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# define FLASH_ACR_LATENCY_6 (6 << FLASH_ACR_LATENCY_SHIFT) /* 110: Six wait states */
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# define FLASH_ACR_LATENCY_7 (7 << FLASH_ACR_LATENCY_SHIFT) /* 111: Seven wait states */
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#if defined(CONFIG_STM32_STM32F10XX)
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# define FLASH_ACR_HLFCYA (1 << 3) /* FLASH half cycle access */
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# define FLASH_ACR_PRTFBE (1 << 4) /* FLASH prefetch enable */
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define FLASH_ACR_ICEN (1 << 9) /* Bit 9: Instruction cache enable */
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# define FLASH_ACR_DCEN (1 << 10) /* Bit 10: Data cache enable */
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# define FLASH_ACR_ICRST (1 << 11) /* Bit 11: Instruction cache reset */
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# define FLASH_ACR_DCRST (1 << 12) /* Bit 12: Data cache reset */
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#endif
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/* Flash Status Register (SR) */
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#if defined(CONFIG_STM32_STM32F10XX)
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# define FLASH_SR_BSY (1 << 0) /* Busy */
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# define FLASH_SR_PGERR (1 << 2) /* Programming Error */
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# define FLASH_SR_WRPRT_ERR (1 << 4) /* Write Protection Error */
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# define FLASH_SR_EOP (1 << 5) /* End of Operation */
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define FLASH_SR_EOP (1 << 0) /* Bit 0: End of operation */
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# define FLASH_SR_OPERR (1 << 1) /* Bit 1: Operation error */
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# define FLASH_SR_WRPERR (1 << 4) /* Bit 4: Write protection error */
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# define FLASH_SR_PGAERR (1 << 5) /* Bit 5: Programming alignment error */
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# define FLASH_SR_PGPERR (1 << 6) /* Bit 6: Programming parallelism error */
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# define FLASH_SR_PGSERR (1 << 7) /* Bit 7: Programming sequence error */
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# define FLASH_SR_BSY (1 << 16) /* Bit 16: Busy */
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#endif
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/* Flash Control Register (CR) */
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#if defined(CONFIG_STM32_STM32F10XX)
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# define FLASH_CR_PG (1 << 0) /* Program Page */
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# define FLASH_CR_PER (1 << 1) /* Page Erase */
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# define FLASH_CR_MER (1 << 2) /* Mass Erase */
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# define FLASH_CR_OPTPG (1 << 4) /* Option Byte Programming */
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# define FLASH_CR_OPTER (1 << 5) /* Option Byte Erase */
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# define FLASH_CR_STRT (1 << 6) /* Start Erase */
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# define FLASH_CR_LOCK (1 << 7) /* Page Locked or Lock Page */
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# define FLASH_CR_OPTWRE (1 << 9) /* Option Bytes Write Enable */
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# define FLASH_CR_ERRIE (1 << 10) /* Error Interrupt Enable */
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# define FLASH_CR_EOPIE (1 << 12) /* End of Program Interrupt Enable */
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#elif defined(CONFIG_STM32_STM32F40XX)
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# define FLASH_CR_PG (1 << 0) /* Bit 0: Programming */
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# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
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# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase */
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# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
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# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
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# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */
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# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
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# define FLASH_CR_PSIZE_MASK (3 << FLASH_CR_PSIZE_SHIFT)
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# define FLASH_CR_PSIZE_X8 (0 << FLASH_CR_PSIZE_SHIFT) /* 00 program x8 */
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# define FLASH_CR_PSIZE_X16 (1 << FLASH_CR_PSIZE_SHIFT) /* 01 program x16 */
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# define FLASH_CR_PSIZE_X32 (2 << FLASH_CR_PSIZE_SHIFT) /* 10 program x32 */
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# define FLASH_CR_PSIZE_X64 (3 << FLASH_CR_PSIZE_SHIFT) /* 11 program x64 */
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# define FLASH_CR_EOPIE (1 << 24) /* Bit 24: End of operation interrupt enable */
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# define FLASH_CR_ERRIE (1 << 25) /* Bit 25: Error interrupt enable */
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# define FLASH_CR_LOCK (1 << 31) /* Bit 31: Lock */
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#endif
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/* Flash Option Control Register (OPTCR) */
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#if defined(CONFIG_STM32_STM32F40XX)
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# define FLASH_OPTCR_OPTLOCK (1 << 0) /* Bit 0: Option lock */
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# define FLASH_OPTCR_OPTSTRT (1 << 1) /* Bit 1: Option start */
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# define FLASH_OPTCR_BORLEV_SHIFT (2) /* Bits 2-3: BOR reset Level */
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# define FLASH_OPTCR_BORLEV_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT)
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# define FLASH_OPTCR_VBOR3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* 00: BOR Level 3 */
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# define FLASH_OPTCR_VBOR2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* 01: BOR Level 2 */
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# define FLASH_OPTCR_VBOR1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* 10: BOR Level 1 */
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# define FLASH_OPTCR_VBOR0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* 11: BOR off */
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# define FLASH_OPTCR_USER_SHIFT (5) /* Bits 5-7: User option bytes */
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# define FLASH_OPTCR_USER_MASK (7 << FLASH_OPTCR_USER_SHIFT)
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# define FLASH_OPTCR_NRST_STDBY (1 << 7) /* Bit 7: nRST_STDBY */
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# define FLASH_OPTCR_NRST_STOP (1 << 6) /* Bit 6: nRST_STOP */
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# define FLASH_OPTCR_WDG_SW (1 << 5) /* Bit 5: WDG_SW */
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# define FLASH_OPTCR_RDP_SHIFT (8) /* Bits 8-15: Read protect */
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# define FLASH_OPTCR_RDP_MASK (0xff << FLASH_OPTCR_RDP_SHIFT)
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# define FLASH_OPTCR_NWRP_SHIFT (16) /* Bits 16-27: Not write protect */
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# define FLASH_OPTCR_NWRP_MASK (0xfff << FLASH_OPTCR_NWRP_SHIFT)
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#endif
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_FLASH_H */
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@ -78,6 +78,18 @@
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# define STM32_I2C2_TRISE (STM32_I2C2_BASE+STM32_I2C_TRISE_OFFSET)
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#endif
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#if STM32_NI2C > 2
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# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
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# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
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# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
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# define STM32_I2C3_OAR2 (STM32_I2C3_BASE+STM32_I2C_OAR2_OFFSET)
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# define STM32_I2C3_DR (STM32_I2C3_BASE+STM32_I2C_DR_OFFSET)
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# define STM32_I2C3_SR1 (STM32_I2C3_BASE+STM32_I2C_SR1_OFFSET)
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# define STM32_I2C3_SR2 (STM32_I2C3_BASE+STM32_I2C_SR2_OFFSET)
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# define STM32_I2C3_CCR (STM32_I2C3_BASE+STM32_I2C_CCR_OFFSET)
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# define STM32_I2C3_TRISE (STM32_I2C3_BASE+STM32_I2C_TRISE_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* Control register 1 */
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@ -33,19 +33,18 @@
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*
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************************************************************************************/
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/** \file
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* \author Uros Platise
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* \brief STM32 Flash - Program and Data Memory
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*
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* Provides standard flash access functions, to be used also by the
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* drivers/mtd/progmem.c program memory flash mtd driver.
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/* Provides standard flash access functions, to be used by the flash mtd driver.
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* The interface is defined in the include/nuttx/progmem.h
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*
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* Requirements during write/erase operations on FLASH:
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* - HSI must be ON.
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* - Low Power Modes are not permitted during write/erase
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <errno.h>
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#include "stm32_waste.h"
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#include "up_arch.h"
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/************************************************************************************
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* Declarations
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* Pre-processor Definitions
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************************************************************************************/
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#define FLASH_KEY1 0x45670123
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#define FLASH_KEY2 0xCDEF89AB
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_STM32_FLASH_H
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#define __ARCH_ARM_SRC_STM32_STM32_FLASH_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/progmem.h>
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/************************************************************************************
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* arch/arm/src/stm32/stm32_fsmc.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@ -96,47 +96,47 @@
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/* Register Addresses ***************************************************************/
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#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE+STM32_FSMC_BCR_OFFSET (n))
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#define STM32_FSMC_BCR(n) (STM32_FSMC_BASE+STM32_FSMC_BCR_OFFSET(n))
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#define STM32_FSMC_BCR1 (STM32_FSMC_BASE+STM32_FSMC_BCR1_OFFSET )
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#define STM32_FSMC_BCR2 (STM32_FSMC_BASE+STM32_FSMC_BCR2_OFFSET )
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#define STM32_FSMC_BCR3 (STM32_FSMC_BASE+STM32_FSMC_BCR3_OFFSET )
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#define STM32_FSMC_BCR4 (STM32_FSMC_BASE+STM32_FSMC_BCR4_OFFSET )
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#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE+STM32_FSMC_BTR_OFFSET (n))
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#define STM32_FSMC_BTR(n) (STM32_FSMC_BASE+STM32_FSMC_BTR_OFFSET(n))
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#define STM32_FSMC_BTR1 (STM32_FSMC_BASE+STM32_FSMC_BTR1_OFFSET )
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#define STM32_FSMC_BTR2 (STM32_FSMC_BASE+STM32_FSMC_BTR2_OFFSET )
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#define STM32_FSMC_BTR3 (STM32_FSMC_BASE+STM32_FSMC_BTR3_OFFSET )
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#define STM32_FSMC_BTR4 (STM32_FSMC_BASE+STM32_FSMC_BTR4_OFFSET )
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#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE+STM32_FSMC_BWTR_OFFSET (n))
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#define STM32_FSMC_BWTR(n) (STM32_FSMC_BASE+STM32_FSMC_BWTR_OFFSET(n))
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#define STM32_FSMC_BWTR1 (STM32_FSMC_BASE+STM32_FSMC_BWTR1_OFFSET )
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#define STM32_FSMC_BWTR2 (STM32_FSMC_BASE+STM32_FSMC_BWTR2_OFFSET )
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#define STM32_FSMC_BWTR3 (STM32_FSMC_BASE+STM32_FSMC_BWTR3_OFFSET )
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#define STM32_FSMC_BWTR4 (STM32_FSMC_BASE+STM32_FSMC_BWTR4_OFFSET )
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#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE+STM32_FSMC_PCR_OFFSET (n))
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#define STM32_FSMC_PCR(n) (STM32_FSMC_BASE+STM32_FSMC_PCR_OFFSET(n))
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#define STM32_FSMC_PCR2 (STM32_FSMC_BASE+STM32_FSMC_PCR2_OFFSET )
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#define STM32_FSMC_PCR3 (STM32_FSMC_BASE+STM32_FSMC_PCR3_OFFSET )
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#define STM32_FSMC_PCR4 (STM32_FSMC_BASE+STM32_FSMC_PCR4_OFFSET )
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#define STM32_FSMC_SR(n) (STM32_FSMC_BASE+STM32_FSMC_SR_OFFSET (n))
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#define STM32_FSMC_SR(n) (STM32_FSMC_BASE+STM32_FSMC_SR_OFFSET(n))
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#define STM32_FSMC_SR2 (STM32_FSMC_BASE+STM32_FSMC_SR2_OFFSET )
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#define STM32_FSMC_SR3 (STM32_FSMC_BASE+STM32_FSMC_SR3_OFFSET )
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#define STM32_FSMC_SR4 (STM32_FSMC_BASE+STM32_FSMC_SR4_OFFSET )
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#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE+STM32_FSMC_PMEM_OFFSET (n))
|
||||
#define STM32_FSMC_PMEM(n) (STM32_FSMC_BASE+STM32_FSMC_PMEM_OFFSET(n))
|
||||
#define STM32_FSMC_PMEM2 (STM32_FSMC_BASE+STM32_FSMC_PMEM2_OFFSET )
|
||||
#define STM32_FSMC_PMEM3 (STM32_FSMC_BASE+STM32_FSMC_PMEM3_OFFSET )
|
||||
#define STM32_FSMC_PMEM4 (STM32_FSMC_BASE+STM32_FSMC_PMEM4_OFFSET )
|
||||
|
||||
#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE+STM32_FSMC_PATT_OFFSET (n))
|
||||
#define STM32_FSMC_PATT(n) (STM32_FSMC_BASE+STM32_FSMC_PATT_OFFSET(n))
|
||||
#define STM32_FSMC_PATT2 (STM32_FSMC_BASE+STM32_FSMC_PATT2_OFFSET )
|
||||
#define STM32_FSMC_PATT3 (STM32_FSMC_BASE+STM32_FSMC_PATT3_OFFSET )
|
||||
#define STM32_FSMC_PATT4 (STM32_FSMC_BASE+STM32_FSMC_PATT4_OFFSET )
|
||||
|
||||
#define STM32_PIO4 (STM32_FSMC_BASE+STM32_FSMC_PIO4_OFFSET )
|
||||
|
||||
#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE+STM32_FSMC_ECCR_OFFSET (n))
|
||||
#define STM32_FSMC_ECCR(n) (STM32_FSMC_BASE+STM32_FSMC_ECCR_OFFSET(n))
|
||||
#define STM32_FSMC_ECCR2 (STM32_FSMC_BASE+STM32_FSMC_ECCR2_OFFSET )
|
||||
#define STM32_FSMC_ECCR3 (STM32_FSMC_BASE+STM32_FSMC_ECCR3_OFFSET )
|
||||
|
||||
@ -163,6 +163,9 @@
|
||||
#define FSMC_BCR_WREN (1 << 12) /* Write enable bit */
|
||||
#define FSMC_BCR_WAITEN (1 << 13) /* Wait enable bit */
|
||||
#define FSMC_BCR_EXTMOD (1 << 14) /* Extended mode enable */
|
||||
#ifdef CONFIG_STM32_STM32F40XX
|
||||
# define FSMC_BCR_ASYNCWAIT (1 << 15) /* Wait signal during asynchronous transfers */
|
||||
#endif
|
||||
#define FSMC_BCR_CBURSTRW (1 << 19) /* Write burst enable */
|
||||
|
||||
#define FSMC_BTR_ADDSET_SHIFT (0) /* Address setup phase duration */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user