SAMV7: Update floating point and TCM configuration options. Update TODO list. Update comments. Refresh a configuration
This commit is contained in:
Gregory Nutt
parent
1b4e32ef20
commit
36e88e504a
31
TODO
31
TODO
@ -1,4 +1,4 @@
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NuttX TODO List (Last updated December 29, 2014)
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NuttX TODO List (Last updated March 10, 2015)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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This file summarizes known NuttX bugs, limitations, inconsistencies with
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@ -10,9 +10,9 @@ nuttx/
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(11) Task/Scheduler (sched/)
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(1) Memory Managment (mm/)
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(3) Signals (sched/, arch/)
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(2) pthreads (sched/)
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(8) Kernel/Protected Builds
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(3) Signals (sched/signal, arch/)
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(2) pthreads (sched/pthread)
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(1) Message Queues (sched/mqueue)
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(4) C++ Support
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(6) Binary loaders (binfmt/)
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(12) Network (net/, drivers/net)
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@ -298,7 +298,7 @@ o Memory Managment (mm/)
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Priority: Medium/Low, a good feature to prevent memory leaks but would
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have negative impact on memory usage and code size.
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o Signals (sched/, arch/)
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o Signals (sched/signal, arch/)
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^^^^^^^^^^^^^^^^^^^^^^^
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Title: STANDARD SIGNALS
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@ -326,7 +326,7 @@ o Signals (sched/, arch/)
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Status: Open
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Priority: Low. Even if there are only 31 usable signals, that is still a lot.
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o pthreads (sched/)
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o pthreads (sched/pthreads)
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^^^^^^^^^^^^^^^^^
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Title: CANCELLATION POINTS
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@ -393,6 +393,25 @@ o pthreads (sched/)
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solution. So I discarded a few hours of programming. Not a
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big loss from the experience I gained."
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Message Queues (sched/mqueue)
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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Title: mq_timedsend() ERROR DETECTION
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Description: mq_timedsend() will always return an error an invalid time is
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provided. However, OpenGroup.org says:
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"Under no circumstance shall the operation fail with a timeout
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if there is sufficient room in the queue to add the message
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immediately. The validity of the abstime parameter need not be
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checked when there is sufficient room in the queue."
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Status: Open
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Priority: Low. This is a valid POSIX compliance issue, but not thought
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to be really important in real work programming. It could
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be used to conditionally block like O_NONBLOCK by providing a
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bad time to the function. That seeks hokey and I can't think
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of any other real world use case the demands this functionality.
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o Kernel/Protected Build
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^^^^^^^^^^^^^^^^^^^^^^
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@ -348,13 +348,26 @@ config ARCH_HAVE_FPU
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bool
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default n
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config ARCH_HAVE_DPFPU
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bool
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default n
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config ARCH_FPU
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bool "FPU support"
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default y
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depends on ARCH_HAVE_FPU
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---help---
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Build in support for the ARM Cortex-M4 Floating Point Unit (FPU).
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Check your chip specifications first; not all Cortex-M4 chips support the FPU.
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Check your chip specifications first; not all Cortex-M4 chips
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support the FPU.
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config ARCH_DPFPU
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bool "Double precision FPU support"
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default y
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depends on ARCH_FPU && ARCH_HAVE_DPFPU
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---help---
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Enable toolchain support for double precision (64-bit) floating
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point if both the toolchain and the hardware support it.
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config ARMV7M_MPU
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bool "MPU support"
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@ -23,6 +23,24 @@ config ARMV7M_DCACHE
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default n
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depends on ARMV7M_HAVE_DCACHE
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config ARMV7M_HAVE_ITCM
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bool
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default n
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config ARMV7M_HAVE_DTCM
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bool
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default n
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config ARMV7M_ITCM
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bool "Use ITCM"
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default n
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depends on ARMV7M_HAVE_ITCM
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config ARMV7M_DTCM
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bool "Use DTCM"
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default n
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depends on ARMV7M_HAVE_DTCM
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choice
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prompt "Toolchain Selection"
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default ARMV7M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
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@ -128,7 +128,11 @@ ifeq ($(CONFIG_ARCH_CORTEXM4),y)
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TOOLCHAIN_MTUNE := -mtune=cortex-m4
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TOOLCHAIN_MARCH := -march=armv7e-m
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ifeq ($(CONFIG_ARCH_FPU),y)
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ifeq ($(CONFIG_ARCH_DPFPU),y)
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TOOLCHAIN_MFLOAT := -mfpu=fpv4-sp -mfloat-abi=hard
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else
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TOOLCHAIN_MFLOAT := -mfpu=fpv4-sp-d16 -mfloat-abi=hard
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endif
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else
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TOOLCHAIN_MFLOAT := -mfloat-abi=soft
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endif
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@ -140,9 +144,13 @@ else ifeq ($(CONFIG_ARCH_CORTEXM7),y)
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TOOLCHAIN_MCPU := -mcpu=cortex-m4
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TOOLCHAIN_MTUNE := -mtune=cortex-m4
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TOOLCHAIN_MARCH := -march=armv7e-m
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# FIXME: Most tools do not yet fpv5 FPU types either
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ifeq ($(CONFIG_ARCH_FPU),y)
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# TOOLCHAIN_MFLOAT := -mfpu=fpv5-sp-d16 -mfloat-abi=hard # Single precision
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ifeq ($(CONFIG_ARCH_DPFPU),y)
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TOOLCHAIN_MFLOAT := -mfpu=fpv5-d16 -mfloat-abi=hard
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else
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TOOLCHAIN_MFLOAT := -mfpu=fpv5-sp-d16 -mfloat-abi=hard
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endif
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else
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TOOLCHAIN_MFLOAT := -mfloat-abi=soft
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endif
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@ -54,8 +54,12 @@ endchoice # Atmel SAMV7 Chip Selection
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config ARCH_CHIP_SAMV71
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bool
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default n
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select ARCH_HAVE_FPU
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select ARCH_HAVE_DPFPU # REVISIT
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select ARMV7M_HAVE_ICACHE
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select ARMV7M_HAVE_DCACHE
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select ARMV7M_HAVE_ITCM
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select ARMV7M_HAVE_DTCM
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config ARCH_CHIP_SAMV71Q
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bool
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@ -110,7 +110,9 @@ CONFIG_ARCH_CHIP="samv7"
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CONFIG_ARCH_HAVE_CMNVECTOR=y
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CONFIG_ARMV7M_CMNVECTOR=y
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# CONFIG_ARMV7M_LAZYFPU is not set
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# CONFIG_ARCH_HAVE_FPU is not set
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CONFIG_ARCH_HAVE_FPU=y
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CONFIG_ARCH_HAVE_DPFPU=y
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# CONFIG_ARCH_FPU is not set
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# CONFIG_ARMV7M_MPU is not set
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#
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@ -120,6 +122,10 @@ CONFIG_ARMV7M_HAVE_ICACHE=y
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CONFIG_ARMV7M_HAVE_DCACHE=y
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# CONFIG_ARMV7M_ICACHE is not set
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# CONFIG_ARMV7M_DCACHE is not set
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CONFIG_ARMV7M_HAVE_ITCM=y
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CONFIG_ARMV7M_HAVE_DTCM=y
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# CONFIG_ARMV7M_ITCM is not set
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# CONFIG_ARMV7M_DTCM is not set
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# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set
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# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set
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# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set
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@ -34,11 +34,14 @@
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****************************************************************************/
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/* The SAMV71Q21 has 2048Kb of FLASH beginning at address 0x0400:0000 and
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* 384Kb of SRAM beginining at 0x2000:0000
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* 384Kb of SRAM beginining at 0x2040:0000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address range.
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* the 0x0400:0000 address range (Assuming that ITCM is not enable).
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*
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* NOTE: that the DTCM address of 0x2000:0000 is used for SRAM. If DTCM is
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* disabled, then the accesses will actually occur on the AHB bus.
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*/
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MEMORY
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@ -34,11 +34,14 @@
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****************************************************************************/
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/* The SAMV71Q21 has 2048Kb of FLASH beginning at address 0x0400:0000 and
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* 384Kb of SRAM beginining at 0x2000:0000
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* 384Kb of SRAM beginining at 0x2040:0000
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*
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* When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
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* where the code expects to begin execution by jumping to the entry point in
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* the 0x0800:0000 address range.
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* the 0x0400:0000 address range.
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*
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* NOTE: that the DTCM address of 0x2000:0000 is used for SRAM. If DTCM is
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* disabled, then the accesses will actually occur on the AHB bus.
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*
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* The user space partition will be spanned with a single region of size
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* 2**n bytes. The alignment of the user-space region must be the same.
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