From 370e188fa32ac8e85dfb87a5b6c6846bdae309bc Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 28 Feb 2017 09:05:01 -0600 Subject: [PATCH] Convert more drivers to use new interrupt argument structure. --- arch/arm/src/stm32/stm32_qencoder.c | 98 ++----------------------- arch/arm/src/stm32l4/stm32l4_qencoder.c | 96 ++---------------------- arch/arm/src/tms570/tms570_serial.c | 39 ++-------- arch/xtensa/src/esp32/esp32_serial.c | 49 ++----------- 4 files changed, 23 insertions(+), 259 deletions(-) diff --git a/arch/arm/src/stm32/stm32_qencoder.c b/arch/arm/src/stm32/stm32_qencoder.c index 07e8faf0a9..e2245075b9 100644 --- a/arch/arm/src/stm32/stm32_qencoder.c +++ b/arch/arm/src/stm32/stm32_qencoder.c @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/stm32/stm32_qencoder.c * - * Copyright (C) 2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2012, 2017 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * Diego Sanchez * @@ -259,7 +259,6 @@ struct stm32_qeconfig_s uint32_t enable; /* RCC clock enable bit */ uint32_t base; /* Register base address */ uint32_t psc; /* Timer input clock prescaler */ - xcpt_t handler; /* Interrupt handler for this IRQ */ }; /* Overall, RAM-based state structure */ @@ -304,25 +303,7 @@ static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv); -#if defined(CONFIG_STM32_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32_tim1interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32_tim2interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32_tim3interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32_tim4interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32_tim5interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32_tim8interrupt(int irq, FAR void *context, FAR void * arg); -#endif +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ @@ -363,9 +344,6 @@ static const struct stm32_qeconfig_s g_tim1config = .psc = CONFIG_STM32_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, -#if TIM1_BITWIDTH == 16 - .handler = stm32_tim1interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim1lower = @@ -391,9 +369,6 @@ static const struct stm32_qeconfig_s g_tim2config = .psc = CONFIG_STM32_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, -#if TIM2_BITWIDTH == 16 - .handler = stm32_tim2interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim2lower = @@ -419,9 +394,6 @@ static const struct stm32_qeconfig_s g_tim3config = .psc = CONFIG_STM32_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, -#if TIM3_BITWIDTH == 16 - .handler = stm32_tim3interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim3lower = @@ -447,9 +419,6 @@ static const struct stm32_qeconfig_s g_tim4config = .psc = CONFIG_STM32_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, -#if TIM4_BITWIDTH == 16 - .handler = stm32_tim4interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim4lower = @@ -475,9 +444,6 @@ static const struct stm32_qeconfig_s g_tim5config = .psc = CONFIG_STM32_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, -#if TIM5_BITWIDTH == 16 - .handler = stm32_tim5interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim5lower = @@ -503,9 +469,6 @@ static const struct stm32_qeconfig_s g_tim8config = .psc = CONFIG_STM32_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, -#if TIM8_BITWIDTH == 16 - .handler = stm32_tim8interrupt, -#endif }; static struct stm32_lowerhalf_s g_tim8lower = @@ -713,10 +676,13 @@ static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim) ************************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv) +static int stm32_interrupt(int irq, FAR void *context, FAR void *arg) { + FAR struct stm32_lowerhalf_s *priv = (FAR struct stm32_lowerhalf_s *)arg; uint16_t regval; + DEBUGASSERT(priv != NULL); + /* Verify that this is an update interrupt. Nothing else is expected. */ regval = stm32_getreg16(priv, STM32_GTIM_SR_OFFSET); @@ -744,56 +710,6 @@ static int stm32_interrupt(FAR struct stm32_lowerhalf_s *priv) } #endif -/************************************************************************************ - * Name: stm32_timNinterrupt - * - * Description: - * TIMN interrupt handler - * - ************************************************************************************/ - -#if defined(CONFIG_STM32_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32_tim1interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32_interrupt(&g_tim1lower); -} -#endif - -#if defined(CONFIG_STM32_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32_tim2interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32_interrupt(&g_tim2lower); -} -#endif - -#if defined(CONFIG_STM32_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32_tim3interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32_interrupt(&g_tim3lower); -} -#endif - -#if defined(CONFIG_STM32_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32_tim4interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32_interrupt(&g_tim4lower); -} -#endif - -#if defined(CONFIG_STM32_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32_tim5interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32_interrupt(&g_tim5lower); -} -#endif - -#if defined(CONFIG_STM32_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32_tim8interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32_interrupt(&g_tim8lower); -} -#endif - /************************************************************************************ * Name: stm32_setup * @@ -973,7 +889,7 @@ static int stm32_setup(FAR struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, priv->config->handler, NULL); + ret = irq_attach(priv->config->irq, stm32_interrupt, priv); if (ret < 0) { stm32_shutdown(lower); diff --git a/arch/arm/src/stm32l4/stm32l4_qencoder.c b/arch/arm/src/stm32l4/stm32l4_qencoder.c index 5e2dc4e001..7c65b95d5a 100644 --- a/arch/arm/src/stm32l4/stm32l4_qencoder.c +++ b/arch/arm/src/stm32l4/stm32l4_qencoder.c @@ -199,7 +199,6 @@ struct stm32l4_qeconfig_s uint32_t ti2cfg; /* TI2 input pin configuration (20-bit encoding) */ uint32_t base; /* Register base address */ uint32_t psc; /* Encoder pulses prescaler */ - xcpt_t handler; /* Interrupt handler for this IRQ */ }; /* Overall, RAM-based state structure */ @@ -244,25 +243,7 @@ static FAR struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim); /* Interrupt handling */ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv); -#if defined(CONFIG_STM32L4_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32l4_tim1interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32L4_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32l4_tim2interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32L4_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32l4_tim3interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32L4_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32l4_tim4interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32L4_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32l4_tim5interrupt(int irq, FAR void *context, FAR void * arg); -#endif -#if defined(CONFIG_STM32L4_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32l4_tim8interrupt(int irq, FAR void *context, FAR void * arg); -#endif +static int stm32l4_interrupt(int irq, FAR void *context, FAR void *arg); #endif /* Lower-half Quadrature Encoder Driver Methods */ @@ -301,9 +282,6 @@ static const struct stm32l4_qeconfig_s g_tim1config = .psc = CONFIG_STM32L4_TIM1_QEPSC, .ti1cfg = GPIO_TIM1_CH1IN, .ti2cfg = GPIO_TIM1_CH2IN, -#if TIM1_BITWIDTH == 16 - .handler = stm32l4_tim1interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim1lower = @@ -327,9 +305,6 @@ static const struct stm32l4_qeconfig_s g_tim2config = .psc = CONFIG_STM32L4_TIM2_QEPSC, .ti1cfg = GPIO_TIM2_CH1IN, .ti2cfg = GPIO_TIM2_CH2IN, -#if TIM2_BITWIDTH == 16 - .handler = stm32l4_tim2interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim2lower = @@ -353,9 +328,6 @@ static const struct stm32l4_qeconfig_s g_tim3config = .psc = CONFIG_STM32L4_TIM3_QEPSC, .ti1cfg = GPIO_TIM3_CH1IN, .ti2cfg = GPIO_TIM3_CH2IN, -#if TIM3_BITWIDTH == 16 - .handler = stm32l4_tim3interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim3lower = @@ -379,9 +351,6 @@ static const struct stm32l4_qeconfig_s g_tim4config = .psc = CONFIG_STM32L4_TIM4_QEPSC, .ti1cfg = GPIO_TIM4_CH1IN, .ti2cfg = GPIO_TIM4_CH2IN, -#if TIM4_BITWIDTH == 16 - .handler = stm32l4_tim4interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim4lower = @@ -405,9 +374,6 @@ static const struct stm32l4_qeconfig_s g_tim5config = .psc = CONFIG_STM32L4_TIM5_QEPSC, .ti1cfg = GPIO_TIM5_CH1IN, .ti2cfg = GPIO_TIM5_CH2IN, -#if TIM5_BITWIDTH == 16 - .handler = stm32l4_tim5interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim5lower = @@ -431,9 +397,6 @@ static const struct stm32l4_qeconfig_s g_tim8config = .psc = CONFIG_STM32L4_TIM8_QEPSC, .ti1cfg = GPIO_TIM8_CH1IN, .ti2cfg = GPIO_TIM8_CH2IN, -#if TIM8_BITWIDTH == 16 - .handler = stm32l4_tim8interrupt, -#endif }; static struct stm32l4_lowerhalf_s g_tim8lower = @@ -645,10 +608,13 @@ static FAR struct stm32l4_lowerhalf_s *stm32l4_tim2lower(int tim) ************************************************************************************/ #ifdef HAVE_16BIT_TIMERS -static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv) +static int stm32l4_interrupt(int irq, FAR void *context, FAR void *arg) { + FAR struct stm32l4_lowerhalf_s *priv = (FAR struct stm32l4_lowerhalf_s *)arg; uint16_t regval; + DEBUGASSERT(priv != NULL); + /* Verify that this is an update interrupt. Nothing else is expected. */ regval = stm32l4_getreg16(priv, STM32L4_GTIM_SR_OFFSET); @@ -676,56 +642,6 @@ static int stm32l4_interrupt(FAR struct stm32l4_lowerhalf_s *priv) } #endif -/************************************************************************************ - * Name: stm32l4_timNinterrupt - * - * Description: - * TIMN interrupt handler - * - ************************************************************************************/ - -#if defined(CONFIG_STM32L4_TIM1_QE) && TIM1_BITWIDTH == 16 -static int stm32l4_tim1interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32l4_interrupt(&g_tim1lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM2_QE) && TIM2_BITWIDTH == 16 -static int stm32l4_tim2interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32l4_interrupt(&g_tim2lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM3_QE) && TIM3_BITWIDTH == 16 -static int stm32l4_tim3interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32l4_interrupt(&g_tim3lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM4_QE) && TIM4_BITWIDTH == 16 -static int stm32l4_tim4interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32l4_interrupt(&g_tim4lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM5_QE) && TIM5_BITWIDTH == 16 -static int stm32l4_tim5interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32l4_interrupt(&g_tim5lower); -} -#endif - -#if defined(CONFIG_STM32L4_TIM8_QE) && TIM8_BITWIDTH == 16 -static int stm32l4_tim8interrupt(int irq, FAR void *context, FAR void * arg) -{ - return stm32l4_interrupt(&g_tim8lower); -} -#endif - /************************************************************************************ * Name: stm32l4_setup * @@ -912,7 +828,7 @@ static int stm32l4_setup(FAR struct qe_lowerhalf_s *lower) { /* Attach the interrupt handler */ - ret = irq_attach(priv->config->irq, priv->config->handler, NULL); + ret = irq_attach(priv->config->irq, stm32l4_interrupt, priv); if (ret < 0) { stm32l4_shutdown(lower); diff --git a/arch/arm/src/tms570/tms570_serial.c b/arch/arm/src/tms570/tms570_serial.c index 2878a03fd1..8bb84ed91f 100644 --- a/arch/arm/src/tms570/tms570_serial.c +++ b/arch/arm/src/tms570/tms570_serial.c @@ -132,7 +132,6 @@ struct tms570_dev_s { const uint32_t scibase; /* Base address of SCI registers */ struct sci_config_s config; /* SCI configuration */ - xcpt_t handler; /* Interrupt handler */ uint8_t irq; /* IRQ associated with this SCI */ }; @@ -144,13 +143,7 @@ static int tms570_setup(struct uart_dev_s *dev); static void tms570_shutdown(struct uart_dev_s *dev); static int tms570_attach(struct uart_dev_s *dev); static void tms570_detach(struct uart_dev_s *dev); -static int tms570_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_TMS570_SCI1 -static int tms570_sci1_interrupt(int irq, void *context, FAR void *arg); -#endif -#ifdef CONFIG_TMS570_SCI2 -static int tms570_sci2_interrupt(int irq, void *context, FAR void *arg); -#endif +static int tms570_interrupt(int irq, void *context, FAR void *arg); static int tms570_ioctl(struct file *filep, int cmd, unsigned long arg); static int tms570_receive(struct uart_dev_s *dev, uint32_t *status); static void tms570_rxint(struct uart_dev_s *dev, bool enable); @@ -207,7 +200,6 @@ static struct tms570_dev_s g_sci1priv = .bits = CONFIG_SCI1_BITS, .stopbits2 = CONFIG_SCI1_2STOP, }, - .handler = tms570_sci1_interrupt, .irq = TMS570_REQ_SCI1_0, }; @@ -241,7 +233,6 @@ static struct tms570_dev_s g_sci2priv = .bits = CONFIG_SCI2_BITS, .stopbits2 = CONFIG_SCI2_2STOP, }, - .handler = tms570_sci2_interrupt, .irq = TMS570_REQ_SCI2_0, }; @@ -387,7 +378,7 @@ static int tms570_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->irq, priv->handler, NULL); + ret = irq_attach(priv->irq, tms570_interrupt, dev); if (ret == OK) { /* Enable the interrupt (RX and TX interrupts are still disabled @@ -428,10 +419,11 @@ static void tms570_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int tms570_interrupt(struct uart_dev_s *dev) +static int tms570_interrupt(int irq, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct tms570_dev_s *priv; - uint32_t intvec; + uint32_t intvec; DEBUGASSERT(dev != NULL && dev->priv != NULL); priv = (struct tms570_dev_s *)dev->priv; @@ -514,27 +506,6 @@ static int tms570_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: tms570_sci[n]_interrupt - * - * Description: - * SCI interrupt handlers - * - ****************************************************************************/ - -#ifdef CONFIG_TMS570_SCI1 -static int tms570_sci1_interrupt(int irq, void *context, FAR void *arg) -{ - return tms570_interrupt(&g_sci1port); -} -#endif -#ifdef CONFIG_TMS570_SCI2 -static int tms570_sci2_interrupt(int irq, void *context, FAR void *arg) -{ - return tms570_interrupt(&g_sci2port); -} -#endif - /**************************************************************************** * Name: tms570_ioctl * diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 37027c8b9b..a5b132487d 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/xtensa/src/esp32/esp32_serial.c * - * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -147,7 +147,6 @@ struct esp32_config_s { const uint32_t uartbase; /* Base address of UART registers */ - xcpt_t handler; /* Interrupt handler */ uint8_t periph; /* UART peripheral ID */ uint8_t irq; /* IRQ number assigned to the peripheral */ uint8_t txpin; /* Tx pin number (0-39) */ @@ -186,16 +185,7 @@ static int esp32_setup(struct uart_dev_s *dev); static void esp32_shutdown(struct uart_dev_s *dev); static int esp32_attach(struct uart_dev_s *dev); static void esp32_detach(struct uart_dev_s *dev); -static int esp32_interrupt(struct uart_dev_s *dev); -#ifdef CONFIG_ESP32_UART0 -static int esp32_uart0_interrupt(int cpuint, void *context, FAR void *arg); -#endif -#ifdef CONFIG_ESP32_UART1 -static int esp32_uart1_interrupt(int cpuint, void *context, FAR void *arg); -#endif -#ifdef CONFIG_ESP32_UART2 -static int esp32_uart2_interrupt(int cpuint, void *context, FAR void *arg); -#endif +static int esp32_interrupt(int cpuint, void *context, FAR void *arg); static int esp32_ioctl(struct file *filep, int cmd, unsigned long arg); static int esp32_receive(struct uart_dev_s *dev, unsigned int *status); static void esp32_rxint(struct uart_dev_s *dev, bool enable); @@ -249,7 +239,6 @@ static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE]; static const struct esp32_config_s g_uart0config = { .uartbase = DR_REG_UART_BASE, - .handler = esp32_uart0_interrupt, .periph = ESP32_PERIPH_UART, .irq = ESP32_IRQ_UART, .txpin = CONFIG_ESP32_UART0_TXPIN, @@ -296,7 +285,6 @@ static uart_dev_t g_uart0port = static const struct esp32_config_s g_uart1config = { .uartbase = DR_REG_UART1_BASE, - .handler = esp32_uart1_interrupt, .periph = ESP32_PERIPH_UART1, .irq = ESP32_IRQ_UART1, .txpin = CONFIG_ESP32_UART1_TXPIN, @@ -343,7 +331,6 @@ static uart_dev_t g_uart1port = static const struct esp32_config_s g_uart2config = { .uartbase = DR_REG_UART2_BASE, - .handler = esp32_uart2_interrupt, .periph = ESP32_PERIPH_UART2, .irq = ESP32_IRQ_UART2, .txpin = CONFIG_ESP32_UART2_TXPIN, @@ -675,7 +662,7 @@ static int esp32_attach(struct uart_dev_s *dev) /* Attach and enable the IRQ */ - ret = irq_attach(priv->config->irq, priv->config->handler, NULL); + ret = irq_attach(priv->config->irq, esp32_interrupt, dev); if (ret == OK) { /* Enable the CPU interrupt (RX and TX interrupts are still disabled @@ -735,8 +722,9 @@ static void esp32_detach(struct uart_dev_s *dev) * ****************************************************************************/ -static int esp32_interrupt(struct uart_dev_s *dev) +static int esp32_interrupt(int cpuint, void *context, FAR void *arg) { + struct uart_dev_s *dev = (struct uart_dev_s *)arg; struct esp32_dev_s *priv; uint32_t regval; uint32_t status; @@ -806,33 +794,6 @@ static int esp32_interrupt(struct uart_dev_s *dev) return OK; } -/**************************************************************************** - * Name: esp32_uart[n]_interrupt - * - * Description: - * UART interrupt handlers - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_UART0 -static int esp32_uart0_interrupt(int cpuint, void *context, FAR void *arg) -{ - return esp32_interrupt(&g_uart0port); -} -#endif -#ifdef CONFIG_ESP32_UART1 -static int esp32_uart1_interrupt(int cpuint, void *context, FAR void *arg) -{ - return esp32_interrupt(&g_uart1port); -} -#endif -#ifdef CONFIG_ESP32_UART2 -static int esp32_uart2_interrupt(int cpuint, void *context, FAR void *arg) -{ - return esp32_interrupt(&g_uart2port); -} -#endif - /**************************************************************************** * Name: esp32_ioctl *