diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index a323f7d0be..aa8fb3a2bf 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -28,30 +28,6 @@ config ARCH_CHIP_STM32L432KC ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM -config ARCH_CHIP_STM32L433RB - bool "STM32L433RB" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_B - select STM32L4_IO_CONFIG_K - ---help--- - STM32 L4 Cortex M4, 128 Kb FLASH, 64 Kb SRAM - -config ARCH_CHIP_STM32L433RC - bool "STM32L433RC" - select STM32L4_STM32L433XX - select STM32L4_FLASH_CONFIG_C - select STM32L4_IO_CONFIG_K - ---help--- - STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM - -config ARCH_CHIP_STM32L442KC - bool "STM32L442KC" - select STM32L4_STM32L442XX - select STM32L4_FLASH_CONFIG_C - select STM32L4_IO_CONFIG_K - ---help--- - STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM - config ARCH_CHIP_STM32L433CB bool "STM32L433CB" select STM32L4_STM32L433XX @@ -92,6 +68,14 @@ config ARCH_CHIP_STM32L433VC ---help--- STM32 L4 Cortex M4, 256 Kb FLASH, 64 Kb SRAM +config ARCH_CHIP_STM32L442KC + bool "STM32L442KC" + select STM32L4_STM32L442XX + select STM32L4_FLASH_CONFIG_C + select STM32L4_IO_CONFIG_K + ---help--- + STM32 L4 Cortex M4, AES, 256 Kb FLASH, 64 Kb SRAM + config ARCH_CHIP_STM32L443CC bool "STM32L443CC" select STM32L4_STM32L443XX @@ -300,13 +284,78 @@ config ARCH_CHIP_STM32L476RE ---help--- STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM -config ARCH_CHIP_STM32L486 # REVISIT: expand for each chip - bool "STM32L486xx" +config ARCH_CHIP_STM32L486RG + bool "STM32L486RG" select STM32L4_STM32L486XX select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_R ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM +config ARCH_CHIP_STM32L486JG + bool "STM32L486JG" + select STM32L4_STM32L486XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_J + ---help--- + STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM + +config ARCH_CHIP_STM32L486VG + bool "STM32L486VG" + select STM32L4_STM32L486XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_V + ---help--- + STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM + +config ARCH_CHIP_STM32L486QG + bool "STM32L486QG" + select STM32L4_STM32L486XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_Q + ---help--- + STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM + +config ARCH_CHIP_STM32L486ZG + bool "STM32L486ZG" + select STM32L4_STM32L486XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_Z + ---help--- + STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM + +config ARCH_CHIP_STM32L496RE + bool "STM32L496RE" + select STM32L4_STM32L496XX + select STM32L4_FLASH_CONFIG_E + select STM32L4_IO_CONFIG_R + ---help--- + STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM + +config ARCH_CHIP_STM32L496RG + bool "STM32L496RG" + select STM32L4_STM32L496XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_R + ---help--- + STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM + +config ARCH_CHIP_STM32L496VE + bool "STM32L496VE" + select STM32L4_STM32L496XX + select STM32L4_FLASH_CONFIG_E + select STM32L4_IO_CONFIG_V + ---help--- + STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM + +config ARCH_CHIP_STM32L496VG + bool "STM32L496VG" + select STM32L4_STM32L496XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_V + ---help--- + STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM + config ARCH_CHIP_STM32L496ZE bool "STM32L496ZE" select STM32L4_STM32L496XX @@ -323,6 +372,14 @@ config ARCH_CHIP_STM32L496ZG ---help--- STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM +config ARCH_CHIP_STM32L496AG + bool "STM32L496AG" + select STM32L4_STM32L496XX + select STM32L4_FLASH_CONFIG_G + select STM32L4_IO_CONFIG_A + ---help--- + STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM + config ARCH_CHIP_STM32L4A6 # REVISIT: expand for each chip bool "STM32L4A6xx" select STM32L4_STM32L4A6XX diff --git a/arch/arm/src/stm32l4/stm32l4_adc.c b/arch/arm/src/stm32l4/stm32l4_adc.c index 7abf3f4104..c023a32a06 100644 --- a/arch/arm/src/stm32l4/stm32l4_adc.c +++ b/arch/arm/src/stm32l4/stm32l4_adc.c @@ -1530,6 +1530,8 @@ static int adc_set_ch(FAR struct adc_dev_s *dev, uint8_t ch) static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; + uint32_t regval; + uint32_t tmp; int ret = OK; switch (cmd) @@ -1538,6 +1540,56 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) adc_startconv(priv, true); break; + case ANIOC_WDOG_UPPER: /* Set watchdog upper threshold */ + { + regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + + /* Verify new upper threshold greater than lower threshold */ + + tmp = (regval & ADC_TR1_LT_MASK) >> ADC_TR1_LT_SHIFT; + if (arg < tmp) + { + ret = -EINVAL; + break; + } + + /* Set the watchdog threshold register */ + + regval &= ~ADC_TR1_HT_MASK; + regval |= ((arg << ADC_TR1_HT_SHIFT) & ADC_TR1_HT_MASK); + adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + + /* Ensure analog watchdog is enabled */ + + adc_wdog_enable(priv); + } + break; + + case ANIOC_WDOG_LOWER: /* Set watchdog lower threshold */ + { + regval = adc_getreg(priv, STM32L4_ADC_TR1_OFFSET); + + /* Verify new lower threshold less than upper threshold */ + + tmp = (regval & ADC_TR1_HT_MASK) >> ADC_TR1_HT_SHIFT; + if (arg > tmp) + { + ret = -EINVAL; + break; + } + + /* Set the watchdog threshold register */ + + regval &= ~ADC_TR1_LT_MASK; + regval |= ((arg << ADC_TR1_LT_SHIFT) & ADC_TR1_LT_MASK); + adc_putreg(priv, STM32L4_ADC_TR1_OFFSET, regval); + + /* Ensure analog watchdog is enabled */ + + adc_wdog_enable(priv); + } + break; + default: aerr("ERROR: Unknown cmd: %d\n", cmd); ret = -ENOTTY; diff --git a/include/nuttx/analog/ioctl.h b/include/nuttx/analog/ioctl.h index 97e4836018..5c0cd21ee9 100644 --- a/include/nuttx/analog/ioctl.h +++ b/include/nuttx/analog/ioctl.h @@ -58,9 +58,15 @@ #define ANIOC_TRIGGER _ANIOC(0x0001) /* Trigger one conversion * IN: None * OUT: None */ +#define ANIOC_WDOG_UPPER _ANIOC(0x0002) /* Set upper threshold for watchdog + * IN: Threshold value + * OUT: None */ +#define ANIOC_WDOG_LOWER _ANIOC(0x0003) /* Set lower threshold for watchdog + * IN: Threshold value + * OUT: None */ #define AN_FIRST 0x0001 /* First common command */ -#define AN_NCMDS 1 /* Two common commands */ +#define AN_NCMDS 3 /* Number of common commands */ /* User defined ioctl commands are also supported. These will be forwarded * by the upper-half QE driver to the lower-half QE driver via the ioctl() @@ -69,7 +75,7 @@ * command numbers from overlapping. */ -/* See include/nuttx/sensors/ads1242.h */ +/* See include/nuttx/analog/ads1242.h */ #define AN_ADS2142_FIRST (AN_FIRST + AN_NCMDS) #define AN_ADS2142_NCMDS 6 diff --git a/include/nuttx/sensors/ioctl.h b/include/nuttx/sensors/ioctl.h index 18b414773f..83b2d9b701 100644 --- a/include/nuttx/sensors/ioctl.h +++ b/include/nuttx/sensors/ioctl.h @@ -1,5 +1,5 @@ /**************************************************************************** - * include/nuttx/input/ioctl.h + * include/nuttx/sensors/ioctl.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Alan Carvalho de Assis