BCM2708: Flesh out some GPIO logic.
This commit is contained in:
Gregory Nutt
parent
c810a77cca
commit
3750da237c
@ -39,9 +39,120 @@
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <nuttx/arch.h>
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#include "up_arch.h"
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#include "bcm_config.h"
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#include "chip/bcm2708_gpio.h"
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#include "bcm_gpio.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Function: bcm_gpio_fsel
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*
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* Description:
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* Set the FSEL field for the given pin.
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*
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************************************************************************************/
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static void bcm_gpio_fsel(unsigned int pin, uint8_t mode)
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{
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uintptr_t regaddr = BCM_GPIO_GPFSEL(pin);
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uint32_t clrbits = BCM_GPIO_GPFSEL_FSEL_MASK(pin);
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uint32_t setbits = BCM_GPIO_GPFSEL_FSEL(pin, mode);
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modifyreg32(regaddr, clrbits, setbits);
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}
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/************************************************************************************
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* Function: bcm_gpio_pudclk
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*
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* Description:
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* Clocks the value written into the pud to the GPIO pin.
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*
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************************************************************************************/
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static void bcm_gpio_pudclk(unsigned int pin, bool enable)
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{
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uintptr_t regaddr = BCM_GPIO_GPPUDCLK(pin);
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uint32_t mask = BCM_GPIO_GPPUD_PUDCLK_MASK(pin);
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if (enable)
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{
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modifyreg32(regaddr, 0, mask);
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}
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else
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{
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modifyreg32(regaddr, mask, 0);
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}
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}
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/************************************************************************************
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* Function: bcm_gpio_configpud
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*
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* Description:
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* "The GPIO Pull-up/down Clock Registers control the actuation of internal
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* pull-downs on the respective GPIO pins. These registers must be used in
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* conjunction with the GPPUD register to effect GPIO Pull-up/down changes. The
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* following sequence of events is required:
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*
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* "1. Write to GPPUD to set the required control signal (i.e. Pull-up or Pull-
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* Down or neither to remove the current Pull-up/down)
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* "2. Wait 150 cycles – this provides the required set-up time for the control
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* signal
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* "3. Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you
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* wish to modify – NOTE only the pads which receive a clock will be modified,
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* all others will retain their previous state.
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* "4. Wait 150 cycles – this provides the required hold time for the control
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* signal
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* "5. Write to GPPUD to remove the control signal
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* "6. Write to GPPUDCLK0/1 to remove the clock"
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*
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************************************************************************************/
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static void bcm_gpio_configpud(unsigned int pin, gpio_pinset_t pinset)
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{
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uint32_t pud = (pinset & GPIO_PUD_MASK) >> GPIO_PUD_SHIFT;
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/* "1. Write to GPPUD to set the required control signal (i.e. Pull-up or Pull-
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* Down or neither to remove the current Pull-up/down)
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*/
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putreg32(pud, BCM_GPIO_GPPUD);
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/* "2. Wait 150 cycles – this provides the required set-up time for the control
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* signal
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*/
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up_udelay(10);
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/* "3. Write to GPPUDCLK0/1 to clock the control signal into the GPIO pads you
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* wish to modify – NOTE only the pads which receive a clock will be modified,
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* all others will retain their previous state.
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*/
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bcm_gpio_pudclk(pin, true);
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/* "4. Wait 150 cycles – this provides the required hold time for the control
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* signal
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*/
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up_udelay(10);
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/* "5. Write to GPPUD to remove the control signal */
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putreg32(BCM_GPIO_GPPUD_PUD_OFF, BCM_GPIO_GPPUD);
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/* "6. Write to GPPUDCLK0/1 to remove the clock" */
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bcm_gpio_pudclk(pin, false);
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -59,46 +170,89 @@
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void bcm_gpio_initialize(void)
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{
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#warning Missing logic
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/* Nothing to be done */
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}
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/************************************************************************************
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* Name: bcm_configgpio
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* Name: bcm_gpio_config
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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*
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************************************************************************************/
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int bcm_configgpio(gpio_pinset_t cfgset)
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int bcm_gpio_config(gpio_pinset_t pinset)
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{
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#warning Missing logic
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return -ENOSYS;
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unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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uint8_t mode;
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/* First, force the pin into an innocuous input state */
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bcm_gpio_fsel(pin, BCM_GPIO_GPFSEL_FSEL_INPUT);
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#ifdef CONFIG_BCM2708_GPIO_IRQ
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/* Make sure that interrupts are disabled */
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bcm_gpio_irqconfig(pinset & ~GPIO_INT_MASK);
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#endif
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/* Configure the pin pull-ups or pull-downs */
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bcm_gpio_configpud(pin, pinset);
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/* If the the pin is an output, set the correct output state */
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mode = (pinset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
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if (mode == BCM_GPIO_GPFSEL_FSEL_OUTPUT)
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{
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bool value = (pinset & GPIO_OUTPUT_MASK) != GPIO_OUTPUT_CLEAR;
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bcm_gpio_write(pinset, value);
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}
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/* Finally configure the correct mode */
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bcm_gpio_fsel(pin, mode);
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return OK;
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}
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/************************************************************************************
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* Name: bcm_gpiowrite
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* Name: bcm_gpio_write
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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************************************************************************************/
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void bcm_gpiowrite(gpio_pinset_t pinset, bool value)
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void bcm_gpio_write(gpio_pinset_t pinset, bool value)
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{
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#warning Missing logic
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unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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uintptr_t regaddr;
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if (value)
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{
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regaddr = BCM_GPIO_GPSET(pin);
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}
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else
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{
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regaddr = BCM_GPIO_GPCLR(pin);
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}
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putreg32(BCM_GPIO_GPSET0_SET(pin), regaddr);
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}
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/************************************************************************************
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* Name: bcm_gpioread
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* Name: bcm_gpio_read
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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************************************************************************************/
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bool bcm_gpioread(gpio_pinset_t pinset)
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bool bcm_gpio_read(gpio_pinset_t pinset)
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{
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#warning Missing logic
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return false;
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unsigned int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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uintptr_t regaddr = BCM_GPIO_GPLEV(pin);
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uint32_t mask = BCM_GPIO_GPLEV0_LEV(pin);
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return (getreg32(regaddr) & mask) != 0;
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}
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@ -50,7 +50,7 @@
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* Pre-processor Definitions
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************************************************************************************/
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/* Bit-encoded input to bcm_configgpio() ********************************************/
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/* Bit-encoded input to bcm_gpio_config() ********************************************/
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/* 32-bit Encoding:
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*
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@ -76,6 +76,8 @@
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/* These bits set the pull up/down configuration of the pin:
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*
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* .... .... .... .... PP.. .... .... ....
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*
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* NOTE: The shifted values match the values of the GPPUD egister.
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*/
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#define GPIO_PUD_SHIFT (14) /* Bits 14-16: GPIO configuration bits */
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@ -109,8 +111,9 @@
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* .... .... .... .... .... .... V... ....
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*/
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#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Initial value of output */
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#define GPIO_OUTPUT_CLEAR (0)
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#define GPIO_OUTPUT_MASK (1 << 7) /* Bit 7: Initial value of output */
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# define GPIO_OUTPUT_CLEAR (0)
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# define GPIO_OUTPUT_SET (1 << 7)
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/* This identifies the GPIO pin:
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*
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@ -229,37 +232,37 @@ void bcm_gpio_irqinitialize(void);
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#endif
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/************************************************************************************
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* Name: bcm_configgpio
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* Name: bcm_gpio_config
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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*
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************************************************************************************/
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int bcm_configgpio(gpio_pinset_t cfgset);
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int bcm_gpio_config(gpio_pinset_t pinset);
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/************************************************************************************
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* Name: bcm_gpiowrite
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* Name: bcm_gpio_write
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*
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* Description:
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* Write one or zero to the selected GPIO pin
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*
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************************************************************************************/
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void bcm_gpiowrite(gpio_pinset_t pinset, bool value);
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void bcm_gpio_write(gpio_pinset_t pinset, bool value);
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/************************************************************************************
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* Name: bcm_gpioread
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* Name: bcm_gpio_read
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*
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* Description:
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* Read one or zero from the selected GPIO pin
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*
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************************************************************************************/
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bool bcm_gpioread(gpio_pinset_t pinset);
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bool bcm_gpio_read(gpio_pinset_t pinset);
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/************************************************************************************
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* Name: bcm_gpioirq
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* Name: bcm_gpio_irqconfig
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*
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* Description:
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* Configure an interrupt for the specified GPIO pin.
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@ -267,13 +270,13 @@ bool bcm_gpioread(gpio_pinset_t pinset);
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************************************************************************************/
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#ifdef CONFIG_BCM2708_GPIO_IRQ
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void bcm_gpioirq(gpio_pinset_t pinset);
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void bcm_gpio_irqconfig(gpio_pinset_t pinset);
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#else
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# define bcm_gpioirq(pinset)
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# define bcm_gpio_irqconfig(pinset)
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#endif
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/************************************************************************************
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* Name: bcm_gpioirqenable
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* Name: bcm_gpio_irqenable
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*
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* Description:
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* Enable the interrupt for specified GPIO IRQ
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@ -281,13 +284,13 @@ void bcm_gpioirq(gpio_pinset_t pinset);
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************************************************************************************/
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#ifdef CONFIG_BCM2708_GPIO_IRQ
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void bcm_gpioirqenable(int irq);
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void bcm_gpio_irqenable(int irq);
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#else
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# define bcm_gpioirqenable(irq)
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# define bcm_gpio_irqenable(irq)
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#endif
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/************************************************************************************
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* Name: bcm_gpioirqdisable
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* Name: bcm_gpio_irqdisable
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*
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* Description:
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* Disable the interrupt for specified GPIO IRQ
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@ -295,9 +298,9 @@ void bcm_gpioirqenable(int irq);
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************************************************************************************/
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#ifdef CONFIG_BCM2708_GPIO_IRQ
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void bcm_gpioirqdisable(int irq);
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void bcm_gpio_irqdisable(int irq);
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#else
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# define bcm_gpioirqdisable(irq)
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# define bcm_gpio_irqdisable(irq)
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#endif
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#undef EXTERN
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@ -62,40 +62,40 @@ void bcm_gpio_irqinitialize(void)
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}
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/************************************************************************************
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* Name: bcm_gpioirq
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* Name: bcm_gpio_irqconfig
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*
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* Description:
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* Configure an interrupt for the specified GPIO pin.
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*
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************************************************************************************/
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void bcm_gpioirq(gpio_pinset_t pinset)
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void bcm_gpio_irqconfig(gpio_pinset_t pinset)
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{
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#warning Missing Logic
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}
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/************************************************************************************
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* Name: bcm_gpioirqenable
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* Name: bcm_gpio_irqenable
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*
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* Description:
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* Enable the interrupt for specified GPIO IRQ
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*
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************************************************************************************/
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void bcm_gpioirqenable(int irq)
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void bcm_gpio_irqenable(int irq)
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{
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#warning Missing Logic
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}
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/************************************************************************************
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* Name: bcm_gpioirqdisable
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* Name: bcm_gpio_irqdisable
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*
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* Description:
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* Disable the interrupt for specified GPIO IRQ
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*
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************************************************************************************/
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void bcm_gpioirqdisable(int irq)
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void bcm_gpio_irqdisable(int irq)
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{
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#warning Missing Logic
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}
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@ -50,70 +50,109 @@
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/* GPIO Register Offsets ************************************************************/
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#define BCM_GPIO_GPFSEL0_OFFSET 0x0000 /* GPIO Function Select 0 */
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#define BCM_GPIO_GPFSEL1_OFFSET 0x0004 /* GPIO Function Select 1 */
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#define BCM_GPIO_GPFSEL2_OFFSET 0x0008 /* GPIO Function Select 2 */
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#define BCM_GPIO_GPFSEL3_OFFSET 0x000c /* GPIO Function Select 3 */
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#define BCM_GPIO_GPFSEL4_OFFSET 0x0010 /* GPIO Function Select 4 */
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#define BCM_GPIO_GPFSEL5_OFFSET 0x0014 /* GPIO Function Select 5 */
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#define BCM_GPIO_GPSET0_OFFSET 0x001c /* GPIO Pin Output Set 0 */
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#define BCM_GPIO_GPSET1_OFFSET 0x0020 /* GPIO Pin Output Set 1 */
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#define BCM_GPIO_GPCLR0_OFFSET 0x0028 /* GPIO Pin Output Clear 0 */
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#define BCM_GPIO_GPCLR1_OFFSET 0x002c /* GPIO Pin Output Clear 1 */
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#define BCM_GPIO_GPLEV0_OFFSET 0x0034 /* GPIO Pin Level 0 */
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#define BCM_GPIO_GPLEV1_OFFSET 0x0038 /* GPIO Pin Level 1 */
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#define BCM_GPIO_GPEDS0_OFFSET 0x0040 /* GPIO Pin Event Detect Status 0 */
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#define BCM_GPIO_GPEDS1_OFFSET 0x0044 /* GPIO Pin Event Detect Status 1 */
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#define BCM_GPIO_GPREN0_OFFSET 0x004c /* GPIO Pin Rising Edge Detect Enable 0 */
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#define BCM_GPIO_GPREN1_OFFSET 0x0050 /* GPIO Pin Rising Edge Detect Enable 1 */
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#define BCM_GPIO_GPFEN0_OFFSET 0x0058 /* GPIO Pin Falling Edge Detect Enable 0 */
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#define BCM_GPIO_GPFEN1_OFFSET 0x005c /* GPIO Pin Falling Edge Detect Enable 1 */
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#define BCM_GPIO_GPHEN0_OFFSET 0x0064 /* GPIO Pin High Detect Enable 0 */
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#define BCM_GPIO_GPHEN1_OFFSET 0x0068 /* GPIO Pin High Detect Enable 1 */
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#define BCM_GPIO_GPLEN0_OFFSET 0x0070 /* GPIO Pin Low Detect Enable 0 */
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#define BCM_GPIO_GPLEN1_OFFSET 0x0074 /* GPIO Pin Low Detect Enable 1 */
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#define BCM_GPIO_GPAREN0_OFFSET 0x007c /* GPIO Pin Async. Rising Edge Detect 0 */
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#define BCM_GPIO_GPAREN1_OFFSET 0x0080 /* GPIO Pin Async. Rising Edge Detect 1 */
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#define BCM_GPIO_GPAFEN0_OFFSET 0x0088 /* GPIO Pin Async. Falling Edge Detect 0 */
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#define BCM_GPIO_GPAFEN1_OFFSET 0x008c /* GPIO Pin Async. Falling Edge Detect 1 */
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#define BCM_GPIO_GPFSEL_INDEX(n) ((n) / 10)
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#define BCM_GPIO_GPFSEL_FIELD(n) ((n) % 10)
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#define BCM_GPIO_GPFSEL_OFFSET(n) (0x0000 + (BCM_GPIO_GPFSEL_INDEX(n) << 2))
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# define BCM_GPIO_GPFSEL0_OFFSET 0x0000 /* GPIO Function Select 0 */
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# define BCM_GPIO_GPFSEL1_OFFSET 0x0004 /* GPIO Function Select 1 */
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# define BCM_GPIO_GPFSEL2_OFFSET 0x0008 /* GPIO Function Select 2 */
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# define BCM_GPIO_GPFSEL3_OFFSET 0x000c /* GPIO Function Select 3 */
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# define BCM_GPIO_GPFSEL4_OFFSET 0x0010 /* GPIO Function Select 4 */
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# define BCM_GPIO_GPFSEL5_OFFSET 0x0014 /* GPIO Function Select 5 */
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#define BCM_GPIO_GPSET_OFFSET(n) (0x001c + (((n) >> 5) << 2))
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# define BCM_GPIO_GPSET0_OFFSET 0x001c /* GPIO Pin Output Set 0 */
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# define BCM_GPIO_GPSET1_OFFSET 0x0020 /* GPIO Pin Output Set 1 */
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#define BCM_GPIO_GPCLR_OFFSET(n) (0x0028 + (((n) >> 5) << 2))
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# define BCM_GPIO_GPCLR0_OFFSET 0x0028 /* GPIO Pin Output Clear 0 */
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# define BCM_GPIO_GPCLR1_OFFSET 0x002c /* GPIO Pin Output Clear 1 */
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#define BCM_GPIO_GPLEV_OFFSET(n) (0x0034 + (((n) >> 5) << 2))
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# define BCM_GPIO_GPLEV0_OFFSET 0x0034 /* GPIO Pin Level 0 */
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# define BCM_GPIO_GPLEV1_OFFSET 0x0038 /* GPIO Pin Level 1 */
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#define BCM_GPIO_GPEDS_OFFSET(n) (0x0040 + (((n) >> 5) << 2))
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# define BCM_GPIO_GPEDS0_OFFSET 0x0040 /* GPIO Pin Event Detect Status 0 */
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# define BCM_GPIO_GPEDS1_OFFSET 0x0044 /* GPIO Pin Event Detect Status 1 */
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#define BCM_GPIO_GPREN_OFFSET(n) (0x004c + (((n) >> 5) << 2))
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# define BCM_GPIO_GPREN0_OFFSET 0x004c /* GPIO Pin Rising Edge Detect Enable 0 */
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# define BCM_GPIO_GPREN1_OFFSET 0x0050 /* GPIO Pin Rising Edge Detect Enable 1 */
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#define BCM_GPIO_GPFEN_OFFSET(n) (0x0058 + (((n) >> 5) << 2))
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# define BCM_GPIO_GPFEN0_OFFSET 0x0058 /* GPIO Pin Falling Edge Detect Enable 0 */
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# define BCM_GPIO_GPFEN1_OFFSET 0x005c /* GPIO Pin Falling Edge Detect Enable 1 */
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#define BCM_GPIO_GPHEN_OFFSET(n) (0x0064 + (((n) >> 5) << 2))
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# define BCM_GPIO_GPHEN0_OFFSET 0x0064 /* GPIO Pin High Detect Enable 0 */
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# define BCM_GPIO_GPHEN1_OFFSET 0x0068 /* GPIO Pin High Detect Enable 1 */
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#define BCM_GPIO_GPLEN_OFFSET(n) (0x0070 + (((n) >> 5) << 2))
|
||||
# define BCM_GPIO_GPLEN0_OFFSET 0x0070 /* GPIO Pin Low Detect Enable 0 */
|
||||
# define BCM_GPIO_GPLEN1_OFFSET 0x0074 /* GPIO Pin Low Detect Enable 1 */
|
||||
#define BCM_GPIO_GPAREN_OFFSET(n) (0x007c + (((n) >> 5) << 2))
|
||||
# define BCM_GPIO_GPAREN0_OFFSET 0x007c /* GPIO Pin Async. Rising Edge Detect 0 */
|
||||
# define BCM_GPIO_GPAREN1_OFFSET 0x0080 /* GPIO Pin Async. Rising Edge Detect 1 */
|
||||
#define BCM_GPIO_GPAFEN_OFFSET(n) (0x0088 + (((n) >> 5) << 2))
|
||||
# define BCM_GPIO_GPAFEN0_OFFSET 0x0088 /* GPIO Pin Async. Falling Edge Detect 0 */
|
||||
# define BCM_GPIO_GPAFEN1_OFFSET 0x008c /* GPIO Pin Async. Falling Edge Detect 1 */
|
||||
#define BCM_GPIO_GPPUD_OFFSET 0x0094 /* GPIO Pin Pull-up/down Enable */
|
||||
#define BCM_GPIO_GPPUDCLK0_OFFSET 0x0098 /* GPIO Pin Pull-up/down Enable Clock 0 */
|
||||
#define BCM_GPIO_GPPUDCLK1_OFFSET 0x009c /* GPIO Pin Pull-up/down Enable Clock 1 */
|
||||
#define BCM_GPIO_GPPUDCLK_OFFSET(n) (0x0098 + (((n) >> 5) << 2))
|
||||
# define BCM_GPIO_GPPUDCLK0_OFFSET 0x0098 /* GPIO Pin Pull-up/down Enable Clock 0 */
|
||||
# define BCM_GPIO_GPPUDCLK1_OFFSET 0x009c /* GPIO Pin Pull-up/down Enable Clock 1 */
|
||||
|
||||
/* GPIO Register Addresses **********************************************************/
|
||||
|
||||
#define BCM_GPIO_GPFSEL0 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL0_OFFSET)
|
||||
#define BCM_GPIO_GPFSEL1 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL1_OFFSET)
|
||||
#define BCM_GPIO_GPFSEL2 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL2_OFFSET)
|
||||
#define BCM_GPIO_GPFSEL3 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL3_OFFSET)
|
||||
#define BCM_GPIO_GPFSEL4 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL4_OFFSET)
|
||||
#define BCM_GPIO_GPFSEL5 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL5_OFFSET)
|
||||
#define BCM_GPIO_GPSET0 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET0_OFFSET)
|
||||
#define BCM_GPIO_GPSET1 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET1_OFFSET)
|
||||
#define BCM_GPIO_GPCLR0 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR0_OFFSET)
|
||||
#define BCM_GPIO_GPCLR1 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR1_OFFSET)
|
||||
#define BCM_GPIO_GPLEV0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV0_OFFSET)
|
||||
#define BCM_GPIO_GPLEV1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV1_OFFSET)
|
||||
#define BCM_GPIO_GPEDS0 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS0_OFFSET)
|
||||
#define BCM_GPIO_GPEDS1 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS1_OFFSET)
|
||||
#define BCM_GPIO_GPREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPREN0_OFFSET)
|
||||
#define BCM_GPIO_GPREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPREN1_OFFSET)
|
||||
#define BCM_GPIO_GPFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN0_OFFSET)
|
||||
#define BCM_GPIO_GPFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN1_OFFSET)
|
||||
#define BCM_GPIO_GPHEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN0_OFFSET)
|
||||
#define BCM_GPIO_GPHEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN1_OFFSET)
|
||||
#define BCM_GPIO_GPLEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN0_OFFSET)
|
||||
#define BCM_GPIO_GPLEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN1_OFFSET)
|
||||
#define BCM_GPIO_GPAREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN0_OFFSET)
|
||||
#define BCM_GPIO_GPAREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN1_OFFSET)
|
||||
#define BCM_GPIO_GPAFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN0_OFFSET)
|
||||
#define BCM_GPIO_GPAFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN1_OFFSET)
|
||||
#define BCM_GPIO_GPFSEL(n) (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL_OFFSET(n))
|
||||
# define BCM_GPIO_GPFSEL0 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL0_OFFSET)
|
||||
# define BCM_GPIO_GPFSEL1 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL1_OFFSET)
|
||||
# define BCM_GPIO_GPFSEL2 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL2_OFFSET)
|
||||
# define BCM_GPIO_GPFSEL3 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL3_OFFSET)
|
||||
# define BCM_GPIO_GPFSEL4 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL4_OFFSET)
|
||||
# define BCM_GPIO_GPFSEL5 (BCM_GPIO_VBASE+BCM_GPIO_GPFSEL5_OFFSET)
|
||||
#define BCM_GPIO_GPSET(n) (BCM_GPIO_VBASE+BCM_GPIO_GPSET_OFFSET(n))
|
||||
# define BCM_GPIO_GPSET0 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET0_OFFSET)
|
||||
# define BCM_GPIO_GPSET1 (BCM_GPIO_VBASE+BCM_BCM_GPIO_GPSET1_OFFSET)
|
||||
#define BCM_GPIO_GPCLR(n) (BCM_GPIO_VBASE+BCM_GPIO_GPCLR_OFFSET(n))
|
||||
# define BCM_GPIO_GPCLR0 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR0_OFFSET)
|
||||
# define BCM_GPIO_GPCLR1 (BCM_GPIO_VBASE+BCM_GPIO_GPCLR1_OFFSET)
|
||||
#define BCM_GPIO_GPLEV(n) (BCM_GPIO_VBASE+BCM_GPIO_GPLEV_OFFSET(n))
|
||||
# define BCM_GPIO_GPLEV0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV0_OFFSET)
|
||||
# define BCM_GPIO_GPLEV1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEV1_OFFSET)
|
||||
#define BCM_GPIO_GPEDS(n) (BCM_GPIO_VBASE+BCM_GPIO_GPEDS_OFFSET(n))
|
||||
# define BCM_GPIO_GPEDS0 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS0_OFFSET)
|
||||
# define BCM_GPIO_GPEDS1 (BCM_GPIO_VBASE+BCM_GPIO_GPEDS1_OFFSET)
|
||||
#define BCM_GPIO_GPREN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPREN_OFFSET(n))
|
||||
# define BCM_GPIO_GPREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPREN0_OFFSET)
|
||||
# define BCM_GPIO_GPREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPREN1_OFFSET)
|
||||
#define BCM_GPIO_GPFEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPFEN_OFFSET(n))
|
||||
# define BCM_GPIO_GPFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN0_OFFSET)
|
||||
# define BCM_GPIO_GPFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPFEN1_OFFSET)
|
||||
#define BCM_GPIO_GPHEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPHEN_OFFSET(n))
|
||||
# define BCM_GPIO_GPHEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN0_OFFSET)
|
||||
# define BCM_GPIO_GPHEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPHEN1_OFFSET)
|
||||
#define BCM_GPIO_GPLEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPLEN_OFFSET(n))
|
||||
# define BCM_GPIO_GPLEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN0_OFFSET)
|
||||
# define BCM_GPIO_GPLEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPLEN1_OFFSET)
|
||||
#define BCM_GPIO_GPAREN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPAREN_OFFSET(n))
|
||||
# define BCM_GPIO_GPAREN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN0_OFFSET)
|
||||
# define BCM_GPIO_GPAREN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAREN1_OFFSET)
|
||||
#define BCM_GPIO_GPAFEN(n) (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN_OFFSET(n))
|
||||
# define BCM_GPIO_GPAFEN0 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN0_OFFSET)
|
||||
# define BCM_GPIO_GPAFEN1 (BCM_GPIO_VBASE+BCM_GPIO_GPAFEN1_OFFSET)
|
||||
#define BCM_GPIO_GPPUD (BCM_GPIO_VBASE+BCM_GPIO_GPPUD_OFFSET)
|
||||
#define BCM_GPIO_GPPUDCLK0 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK0_OFFSET)
|
||||
#define BCM_GPIO_GPPUDCLK1 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK1_OFFSET)
|
||||
#define BCM_GPIO_GPPUDCLK(n) (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK_OFFSET(n))
|
||||
# define BCM_GPIO_GPPUDCLK0 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK0_OFFSET)
|
||||
# define BCM_GPIO_GPPUDCLK1 (BCM_GPIO_VBASE+BCM_GPIO_GPPUDCLK1_OFFSET)
|
||||
|
||||
/* GPIO Register Bit Definitions ****************************************************/
|
||||
|
||||
#define BCM_GPIO_GPFSEL_FSEL_SHIFT(n) (3 * BCM_GPIO_GPFSEL_FIELD(n))
|
||||
#define BCM_GPIO_GPFSEL_FSEL_MASK(n) (7 << BCM_GPIO_GPFSEL_FSEL_SHIFT(n))
|
||||
# define BCM_GPIO_GPFSEL_FSEL(n,f) ((uint32_t)(f) << BCM_GPIO_GPFSEL_FSEL_SHIFT(n))
|
||||
# define BCM_GPIO_GPFSEL_FSEL_INPUT (0)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_OUTPUT (1)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_ALT0 (4)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_ALT1 (5)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_ALT2 (6)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_ALT3 (7)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_ALT4 (3)
|
||||
# define BCM_GPIO_GPFSEL_FSEL_ALT5 (2)
|
||||
|
||||
#define BCM_GPIO_GPFSEL_FSELx0_SHIFT 0
|
||||
#define BCM_GPIO_GPFSEL_FSELx0_MASK (7 << BCM_GPIO_GPFSEL_FSELx0_SHIFT)
|
||||
# define BCM_GPIO_GPFSEL_FSELx0_INPUT (0 << BCM_GPIO_GPFSEL_FSELx0_SHIFT)
|
||||
@ -215,41 +254,25 @@
|
||||
# define BCM_GPIO_GPFSEL_FSELx9_ALT4 (3 << BCM_GPIO_GPFSEL_FSELx9_SHIFT)
|
||||
# define BCM_GPIO_GPFSEL_FSELx9_ALT5 (2 << BCM_GPIO_GPFSEL_FSELx9_SHIFT)
|
||||
|
||||
#define BCM_GPIO_GPSET0_SET(n) (1 << n) /* Set GPIO pin n 0-31 */
|
||||
#define BCM_GPIO_GPSET1_SET(n) (1 << (n-32)) /* Set GPIO pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPCLR0_CLR(n) (1 << n) /* Clear GPIO pin n 0-31 */
|
||||
#define BCM_GPIO_GPCLR1_CLR(n) (1 << (n-32)) /* Clear GPIO pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPLEV0_LEV(n) (1 << n) /* Level of pin n 0-31 */
|
||||
#define BCM_GPIO_GPLEV1_LEV(n) (1 << (n-32)) /* Level of pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPEDS0_EDS(n) (1 << n) /* Event detected in pin n 0-31 */
|
||||
#define BCM_GPIO_GPEDS1_EDS(n) (1 << (n-32)) /* Event detected in pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPREN0_REN(n) (1 << n) /* Rising Edge Enable pin n 0-31 */
|
||||
#define BCM_GPIO_GPREN1_REN(n) (1 << (n-32)) /* Rising Edge Enable pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPFEN0_FEN(n) (1 << n) /* Falling Edge Enable pin n 0-31 */
|
||||
#define BCM_GPIO_GPFEN0_FEN(n) (1 << (n-32)) /* Falling Edge Enable pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPHEN0_HEN(n) (1 << n) /* High Detect Enable pin n 0-31 */
|
||||
#define BCM_GPIO_GPHEN1_HEN(n) (1 << (n-32)) /* High Detect Enable pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPLEN0_LEN(n) (1 << n) /* Low Detect Enable pin n 0-31 */
|
||||
#define BCM_GPIO_GPLEN1_LEN(n) (1 << (n-32)) /* Low Detect Enable pin n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPAREN0_AREN(n) (1 << n) /* Asynchronous Rising Edge Detect Enable n 0-31 */
|
||||
#define BCM_GPIO_GPAREN1_AREN(n) (1 << (n-32) /* Asynchronous Rising Edge Detect Enable n 32-53 */
|
||||
|
||||
#define BCM_GPIO_GPAFEN0_AFEN(n) (1 << n) /* Asynchronous Falling Edge Detect Enable n 0-31 */
|
||||
#define BCM_GPIO_GPAFEN1_AFEN(n) (1 << (n-32) /* Asynchronous Falling Edge Detect Enable n 32-53 */
|
||||
#define BCM_GPIO_GPSET0_SET(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPCLR0_CLR(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPLEV0_LEV(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPEDS0_EDS(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPREN0_REN(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPFEN0_FEN(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPHEN0_HEN(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPLEN0_LEN(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPAREN0_AREN(n) (1 << ((n) & 0x1f))
|
||||
#define BCM_GPIO_GPAFEN0_AFEN(n) (1 << ((n) & 0x1f))
|
||||
|
||||
#define BCM_GPIO_GPPUD_PUD_SHIFT 0 /* bit 0-1: Pull-up/down register */
|
||||
#define BCM_GPIO_GPPUD_PUD_MASK (3 << BCM_GPIO_GPPUD_PUD_SHIFT)
|
||||
#define BCM_GPIO_GPPUD_PUD_OFF (0 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Disable Pull-up/down */
|
||||
#define BCM_GPIO_GPPUD_PUD_PD (1 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-down */
|
||||
#define BCM_GPIO_GPPUD_PUD_PU (2 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-up */
|
||||
# define BCM_GPIO_GPPUD_PUD_OFF (0 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Disable Pull-up/down */
|
||||
# define BCM_GPIO_GPPUD_PUD_PD (1 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-down */
|
||||
# define BCM_GPIO_GPPUD_PUD_PU (2 << BCM_GPIO_GPPUD_PUD_SHIFT) /* Enable Pull-up */
|
||||
|
||||
#define BCM_GPIO_GPPUD_PUDCLK_SHIFT(n) ((n) & 0x1f)
|
||||
# define BCM_GPIO_GPPUD_PUDCLK_MASK(n) (1 << BCM_GPIO_GPPUD_PUDCLK_SHIFT(n))
|
||||
# define BCM_GPIO_GPPUD_PUDCLK(n,v) ((uint32_t)(v) << BCM_GPIO_GPPUD_PUDCLK_SHIFT(n))
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_BCM2708_CHIP_BCM2708_GPIO_H */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user