SAMA5D4: USART peripheral clock appears to be MCK/2
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@ -167,6 +167,12 @@
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#define BOARD_MCK_FREQUENCY (128000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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@ -125,6 +125,12 @@
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -124,6 +124,12 @@
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -63,6 +63,12 @@
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#define BOARD_PCK_FREQUENCY (sam_pck_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_MCK_FREQUENCY (sam_mck_frequency(BOARD_MAINOSC_FREQUENCY))
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -167,6 +167,12 @@
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#define BOARD_MCK_FREQUENCY (128000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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@ -125,6 +125,12 @@
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -124,6 +124,11 @@
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -63,6 +63,12 @@
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#define BOARD_PCK_FREQUENCY (sam_pck_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_MCK_FREQUENCY (sam_mck_frequency(BOARD_MAINOSC_FREQUENCY))
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/* On some SAMA5's, the clocking to peripherals may be divided down from MCK,
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* but not for the SAMA5D3.
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*/
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#define BOARD_USART_FREQUENCY BOARD_MCK_FREQUENCY
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -165,6 +165,13 @@
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#define BOARD_MCK_FREQUENCY (128000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8000000) /* ADCCLK: MCK / ((7+1)*2) */
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/* Clocking to certain peripherals may be MCK/2.
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*
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* REVISIT: I am not sure why this is. Perhaps because of H32MXDIV?
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*/
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#define BOARD_USART_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
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/* HSMCI clocking
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*
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* Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK)
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@ -123,6 +123,13 @@
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 2 / 1 / 3 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* Clocking to certain peripherals may be MCK/2.
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*
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* REVISIT: I am not sure why this is. Perhaps because of H32MXDIV?
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*/
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#define BOARD_USART_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -122,6 +122,13 @@
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#define BOARD_MCK_FREQUENCY (132000000) /* MCK: PLLACK / 1 / 1 / 4 */
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#define BOARD_ADCCLK_FREQUENCY (8250000) /* ADCCLK: MCK / ((7+1)*2) */
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/* Clocking to certain peripherals may be MCK/2.
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*
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* REVISIT: I am not sure why this is. Perhaps because of H32MXDIV?
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*/
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#define BOARD_USART_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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@ -63,6 +63,13 @@
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#define BOARD_PCK_FREQUENCY (sam_pck_frequency(BOARD_MAINOSC_FREQUENCY))
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#define BOARD_MCK_FREQUENCY (sam_mck_frequency(BOARD_MAINOSC_FREQUENCY))
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/* Clocking to certain peripherals may be MCK/2.
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*
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* REVISIT: I am not sure why this is. Perhaps because of H32MXDIV?
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*/
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#define BOARD_USART_FREQUENCY (BOARD_MCK_FREQUENCY >> 1)
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#if defined(CONFIG_SAMA5_EHCI) || defined(CONFIG_SAMA5_OHCI) || \
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defined(CONFIG_SAMA5_UDPHS)
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